Searched refs:SW_PAD_CTL_PAD_ENET1_TX_CLK (Results 1 – 2 of 2) sorted by relevance
15875 __IO uint32_t SW_PAD_CTL_PAD_ENET1_TX_CLK; /**< Pad Control Register, offset: 0x3D8 */ member16424 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_TX_CLK_REG(base) ((base)->SW_PAD_CTL_PAD_ENET1_TX_CLK)
21948 …__IO uint32_t SW_PAD_CTL_PAD_ENET1_TX_CLK; /**< SW_PAD_CTL_PAD_ENET1_TX_CLK SW PAD Con… member22419 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_TX_CLK_REG(base) ((base)->SW_PAD_CTL_PAD_ENET1_TX_CLK)
