Searched refs:SW_PAD_CTL_PAD_DRAM_SDQS3_P (Results 1 – 1 of 1) sorted by relevance
15836 __IO uint32_t SW_PAD_CTL_PAD_DRAM_SDQS3_P; /**< Pad Control Register, offset: 0x33C */ member16385 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_REG(base) ((base)->SW_PAD_CTL_PAD_DRAM_SDQS3_P)
