Searched refs:SW_PAD_CTL_PAD_DRAM_SDBA1 (Results 1 – 1 of 1) sorted by relevance
15828 __IO uint32_t SW_PAD_CTL_PAD_DRAM_SDBA1; /**< Pad Control Register, offset: 0x31C */ member16377 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1_REG(base) ((base)->SW_PAD_CTL_PAD_DRAM_SDBA1)
