Searched refs:SW_PAD_CTL_PAD_DRAM_DQM2 (Results 1 – 1 of 1) sorted by relevance
15818 __IO uint32_t SW_PAD_CTL_PAD_DRAM_DQM2; /**< Pad Control Register, offset: 0x2F4 */ member16367 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_REG(base) ((base)->SW_PAD_CTL_PAD_DRAM_DQM2)
