Searched refs:SW_PAD_CTL_PAD_DRAM_ADDR05 (Results 1 – 1 of 1) sorted by relevance
15805 __IO uint32_t SW_PAD_CTL_PAD_DRAM_ADDR05; /**< Pad Control Register, offset: 0x2C0 */ member16354 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05_REG(base) ((base)->SW_PAD_CTL_PAD_DRAM_ADDR05)
