Home
last modified time | relevance | path

Searched refs:SW_MUX_CTL_PAD_GPIO1_IO12 (Results 1 – 2 of 2) sorted by relevance

/hal_nxp-latest/imx/devices/MCIMX6X/
DMCIMX6X_M4.h15646 __IO uint32_t SW_MUX_CTL_PAD_GPIO1_IO12; /**< Pad Mux Register, offset: 0x44 */ member
16195 #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO12_REG(base) ((base)->SW_MUX_CTL_PAD_GPIO1_IO12)
/hal_nxp-latest/imx/devices/MCIMX7D/
DMCIMX7D_M4.h21650 …__IO uint32_t SW_MUX_CTL_PAD_GPIO1_IO12; /**< SW_MUX_CTL_PAD_GPIO1_IO12 SW MUX Contr… member
22121 #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO12_REG(base) ((base)->SW_MUX_CTL_PAD_GPIO1_IO12)