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Searched refs:SW_MUX_CTL_PAD_GPIO1_IO08 (Results 1 – 2 of 2) sorted by relevance

/hal_nxp-latest/imx/devices/MCIMX6X/
DMCIMX6X_M4.h15642 __IO uint32_t SW_MUX_CTL_PAD_GPIO1_IO08; /**< Pad Mux Register, offset: 0x34 */ member
16191 #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO08_REG(base) ((base)->SW_MUX_CTL_PAD_GPIO1_IO08)
/hal_nxp-latest/imx/devices/MCIMX7D/
DMCIMX7D_M4.h21646 …__IO uint32_t SW_MUX_CTL_PAD_GPIO1_IO08; /**< SW_MUX_CTL_PAD_GPIO1_IO08 SW MUX Contr… member
22117 #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO08_REG(base) ((base)->SW_MUX_CTL_PAD_GPIO1_IO08)