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Searched refs:SW_MUX_CTL_PAD_GPIO1_IO06 (Results 1 – 2 of 2) sorted by relevance

/hal_nxp-latest/imx/devices/MCIMX6X/
DMCIMX6X_M4.h15640 __IO uint32_t SW_MUX_CTL_PAD_GPIO1_IO06; /**< Pad Mux Register, offset: 0x2C */ member
16189 #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO06_REG(base) ((base)->SW_MUX_CTL_PAD_GPIO1_IO06)
/hal_nxp-latest/imx/devices/MCIMX7D/
DMCIMX7D_M4.h27238 …__IO uint32_t SW_MUX_CTL_PAD_GPIO1_IO06; /**< SW_MUX_CTL_PAD_GPIO1_IO06 SW MUX Contr… member
27270 #define IOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO1_IO06_REG(base) ((base)->SW_MUX_CTL_PAD_GPIO1_IO06)