Searched refs:SW_MUX_CTL_PAD_GPIO1_IO05 (Results 1 – 2 of 2) sorted by relevance
15639 __IO uint32_t SW_MUX_CTL_PAD_GPIO1_IO05; /**< Pad Mux Register, offset: 0x28 */ member16188 #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO05_REG(base) ((base)->SW_MUX_CTL_PAD_GPIO1_IO05)
27237 …__IO uint32_t SW_MUX_CTL_PAD_GPIO1_IO05; /**< SW_MUX_CTL_PAD_GPIO1_IO05 SW MUX Contr… member27269 #define IOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO1_IO05_REG(base) ((base)->SW_MUX_CTL_PAD_GPIO1_IO05)
