Home
last modified time | relevance | path

Searched refs:SW_MUX_CTL_PAD_GPIO1_IO04 (Results 1 – 2 of 2) sorted by relevance

/hal_nxp-latest/imx/devices/MCIMX6X/
DMCIMX6X_M4.h15638 __IO uint32_t SW_MUX_CTL_PAD_GPIO1_IO04; /**< Pad Mux Register, offset: 0x24 */ member
16187 #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO04_REG(base) ((base)->SW_MUX_CTL_PAD_GPIO1_IO04)
/hal_nxp-latest/imx/devices/MCIMX7D/
DMCIMX7D_M4.h27236 …__IO uint32_t SW_MUX_CTL_PAD_GPIO1_IO04; /**< SW_MUX_CTL_PAD_GPIO1_IO04 SW MUX Contr… member
27268 #define IOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO1_IO04_REG(base) ((base)->SW_MUX_CTL_PAD_GPIO1_IO04)