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Searched refs:SWREG23 (Results 1 – 13 of 13) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8ML6/
DMIMX8ML6_cm7.h105595 …__IO uint32_t SWREG23; /**< Base address for reference picture index 9 /… member
107796 …__I uint32_t SWREG23; /**< Decoder configure status register, offset: 0… member
111337 __IO uint32_t SWREG23; /**< intra Area, offset: 0x5C */ member
114973 __IO uint32_t SWREG23; /**< intra Area, offset: 0x5C */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8ML4/
DMIMX8ML4_cm7.h105595 …__IO uint32_t SWREG23; /**< Base address for reference picture index 9 /… member
107796 …__I uint32_t SWREG23; /**< Decoder configure status register, offset: 0… member
111337 __IO uint32_t SWREG23; /**< intra Area, offset: 0x5C */ member
114973 __IO uint32_t SWREG23; /**< intra Area, offset: 0x5C */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8ML3/
DMIMX8ML3_cm7.h105595 …__IO uint32_t SWREG23; /**< Base address for reference picture index 9 /… member
107796 …__I uint32_t SWREG23; /**< Decoder configure status register, offset: 0… member
111337 __IO uint32_t SWREG23; /**< intra Area, offset: 0x5C */ member
114973 __IO uint32_t SWREG23; /**< intra Area, offset: 0x5C */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8ML8/
DMIMX8ML8_dsp.h101244 …__IO uint32_t SWREG23; /**< Base address for reference picture index 9 /… member
103264 …__I uint32_t SWREG23; /**< Decoder configure status register, offset: 0… member
106505 __IO uint32_t SWREG23; /**< intra Area, offset: 0x5C */ member
110141 __IO uint32_t SWREG23; /**< intra Area, offset: 0x5C */ member
DMIMX8ML8_cm7.h105595 …__IO uint32_t SWREG23; /**< Base address for reference picture index 9 /… member
107796 …__I uint32_t SWREG23; /**< Decoder configure status register, offset: 0… member
111337 __IO uint32_t SWREG23; /**< intra Area, offset: 0x5C */ member
114973 __IO uint32_t SWREG23; /**< intra Area, offset: 0x5C */ member
DMIMX8ML8_ca53.h105628 …__IO uint32_t SWREG23; /**< Base address for reference picture index 9 /… member
107829 …__I uint32_t SWREG23; /**< Decoder configure status register, offset: 0… member
111370 __IO uint32_t SWREG23; /**< intra Area, offset: 0x5C */ member
115006 __IO uint32_t SWREG23; /**< intra Area, offset: 0x5C */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MM3/
DMIMX8MM3_cm4.h76314 …__IO uint32_t SWREG23; /**< Base address for reference picture index 9 /… member
78515 …__I uint32_t SWREG23; /**< Decoder configure status register, offset: 0… member
82056 __IO uint32_t SWREG23; /**< VPU H1 Register 23, offset: 0x5C */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MM5/
DMIMX8MM5_cm4.h76314 …__IO uint32_t SWREG23; /**< Base address for reference picture index 9 /… member
78515 …__I uint32_t SWREG23; /**< Decoder configure status register, offset: 0… member
82056 __IO uint32_t SWREG23; /**< VPU H1 Register 23, offset: 0x5C */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MM6/
DMIMX8MM6_cm4.h76314 …__IO uint32_t SWREG23; /**< Base address for reference picture index 9 /… member
78515 …__I uint32_t SWREG23; /**< Decoder configure status register, offset: 0… member
82056 __IO uint32_t SWREG23; /**< VPU H1 Register 23, offset: 0x5C */ member
DMIMX8MM6_ca53.h75778 …__IO uint32_t SWREG23; /**< Base address for reference picture index 9 /… member
77979 …__I uint32_t SWREG23; /**< Decoder configure status register, offset: 0… member
81520 __IO uint32_t SWREG23; /**< VPU H1 Register 23, offset: 0x5C */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MM1/
DMIMX8MM1_cm4.h76314 …__IO uint32_t SWREG23; /**< Base address for reference picture index 9 /… member
78515 …__I uint32_t SWREG23; /**< Decoder configure status register, offset: 0… member
82056 __IO uint32_t SWREG23; /**< VPU H1 Register 23, offset: 0x5C */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MM2/
DMIMX8MM2_cm4.h76314 …__IO uint32_t SWREG23; /**< Base address for reference picture index 9 /… member
78515 …__I uint32_t SWREG23; /**< Decoder configure status register, offset: 0… member
82056 __IO uint32_t SWREG23; /**< VPU H1 Register 23, offset: 0x5C */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MM4/
DMIMX8MM4_cm4.h76314 …__IO uint32_t SWREG23; /**< Base address for reference picture index 9 /… member
78515 …__I uint32_t SWREG23; /**< Decoder configure status register, offset: 0… member
82056 __IO uint32_t SWREG23; /**< VPU H1 Register 23, offset: 0x5C */ member