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Searched refs:SWM_PINASSIGN5_SPI0_SSEL3_IO_MASK (Results 1 – 8 of 8) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/devices/LPC824/
DLPC824.h6113 #define SWM_PINASSIGN5_SPI0_SSEL3_IO_MASK (0xFF00U) macro
6118 …t32_t)(((uint32_t)(x)) << SWM_PINASSIGN5_SPI0_SSEL3_IO_SHIFT)) & SWM_PINASSIGN5_SPI0_SSEL3_IO_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC822/
DLPC822.h6113 #define SWM_PINASSIGN5_SPI0_SSEL3_IO_MASK (0xFF00U) macro
6118 …t32_t)(((uint32_t)(x)) << SWM_PINASSIGN5_SPI0_SSEL3_IO_SHIFT)) & SWM_PINASSIGN5_SPI0_SSEL3_IO_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC834/
DLPC834.h5893 #define SWM_PINASSIGN5_SPI0_SSEL3_IO_MASK (0xFF00U) macro
5898 …t32_t)(((uint32_t)(x)) << SWM_PINASSIGN5_SPI0_SSEL3_IO_SHIFT)) & SWM_PINASSIGN5_SPI0_SSEL3_IO_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC832/
DLPC832.h5893 #define SWM_PINASSIGN5_SPI0_SSEL3_IO_MASK (0xFF00U) macro
5898 …t32_t)(((uint32_t)(x)) << SWM_PINASSIGN5_SPI0_SSEL3_IO_SHIFT)) & SWM_PINASSIGN5_SPI0_SSEL3_IO_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC844/
DLPC844.h6626 #define SWM_PINASSIGN5_SPI0_SSEL3_IO_MASK (0xFF00U) macro
6632 …t32_t)(((uint32_t)(x)) << SWM_PINASSIGN5_SPI0_SSEL3_IO_SHIFT)) & SWM_PINASSIGN5_SPI0_SSEL3_IO_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC845/
DLPC845.h7150 #define SWM_PINASSIGN5_SPI0_SSEL3_IO_MASK (0xFF00U) macro
7156 …t32_t)(((uint32_t)(x)) << SWM_PINASSIGN5_SPI0_SSEL3_IO_SHIFT)) & SWM_PINASSIGN5_SPI0_SSEL3_IO_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC865/
DLPC865.h8611 #define SWM_PINASSIGN5_SPI0_SSEL3_IO_MASK (0xFF00U) macro
8617 …t32_t)(((uint32_t)(x)) << SWM_PINASSIGN5_SPI0_SSEL3_IO_SHIFT)) & SWM_PINASSIGN5_SPI0_SSEL3_IO_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC864/
DLPC864.h8609 #define SWM_PINASSIGN5_SPI0_SSEL3_IO_MASK (0xFF00U) macro
8615 …t32_t)(((uint32_t)(x)) << SWM_PINASSIGN5_SPI0_SSEL3_IO_SHIFT)) & SWM_PINASSIGN5_SPI0_SSEL3_IO_MASK)