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Searched refs:STARTEN2_CLR (Results 1 – 7 of 7) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT595S/drivers/
Dfsl_power.c1336 SYSCTL0->STARTEN2_CLR = 1UL << (intNumber - 64U); in DisableDeepSleepIRQ()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT533S/drivers/
Dfsl_power.c1336 SYSCTL0->STARTEN2_CLR = 1UL << (intNumber - 64U); in DisableDeepSleepIRQ()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT555S/drivers/
Dfsl_power.c1336 SYSCTL0->STARTEN2_CLR = 1UL << (intNumber - 64U); in DisableDeepSleepIRQ()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT595S/
DMIMXRT595S_dsp.h34051 __IO uint32_t STARTEN2_CLR; /**< Start Enable 2, offset: 0x6C8 */ member
DMIMXRT595S_cm33.h43850 __IO uint32_t STARTEN2_CLR; /**< Start Enable 2, offset: 0x6C8 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT533S/
DMIMXRT533S.h42223 __IO uint32_t STARTEN2_CLR; /**< Start Enable 2, offset: 0x6C8 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT555S/
DMIMXRT555S.h43849 __IO uint32_t STARTEN2_CLR; /**< Start Enable 2, offset: 0x6C8 */ member