1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2024 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32Z2_SRX.h 10 * @version 2.3 11 * @date 2024-05-03 12 * @brief Peripheral Access Layer for S32Z2_SRX 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32Z2_SRX_H_) /* Check if memory map has not been already included */ 58 #define S32Z2_SRX_H_ 59 60 #include "S32Z2_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- SRX Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup SRX_Peripheral_Access_Layer SRX Peripheral Access Layer 68 * @{ 69 */ 70 71 /** SRX - Size of Registers Arrays */ 72 #define SRX_CNL_COUNT 8u 73 74 /** SRX - Register Layout Typedef */ 75 typedef struct { 76 __IO uint32_t GBL_CTRL; /**< Global Control Register, offset: 0x0 */ 77 __IO uint32_t CHNL_EN; /**< Channel Enable Register, offset: 0x4 */ 78 __IO uint32_t SLOW_MSG_UVF; /**< Slow Channel Status, offset: 0x8 */ 79 __IO uint32_t FMSG_RDY; /**< Fast Message Ready Status Register, offset: 0xC */ 80 __IO uint32_t SMSG_RDY; /**< Slow Serial Message Ready Status Register, offset: 0x10 */ 81 __IO uint32_t CHNL_FIFO_EN; /**< Channel FIFO Enable, offset: 0x14 */ 82 __IO uint32_t DATA_CTRL1; /**< Data Control Register 1, offset: 0x18 */ 83 uint8_t RESERVED_0[4]; 84 __IO uint32_t CHNL_OVF_UVF; /**< Fast Channel Status, offset: 0x20 */ 85 __IO uint32_t FDMA_CTRL; /**< Fast Message DMA Control Register, offset: 0x24 */ 86 __IO uint32_t SDMA_CTRL; /**< Slow Serial Message DMA Control Register, offset: 0x28 */ 87 __IO uint32_t CHNL_NB_REORD1; /**< Channel Nibble Reorder 1, offset: 0x2C */ 88 uint8_t RESERVED_1[4]; 89 __IO uint32_t FMSG_RDY_IE; /**< Fast Message Ready Interrupt Control Register, offset: 0x34 */ 90 __IO uint32_t SMSG_RDY_IE; /**< Slow Serial Message Ready Interrupt Enable Register, offset: 0x38 */ 91 uint8_t RESERVED_2[36]; 92 struct SRX_CNL { /* offset: 0x60, array step: 0x44 */ 93 __IO uint32_t CH_CLK_CTRL; /**< Channel '0' Clock Control Register..Channel '7' Clock Control Register, array offset: 0x60, array step: 0x44 */ 94 __IO uint32_t CH_STATUS; /**< Channel '0' Status Register..Channel '7' Status Register, array offset: 0x64, array step: 0x44 */ 95 __IO uint32_t CH_CONFIG; /**< Channel '0' Configuration Register..Channel '7' Configuration Register, array offset: 0x68, array step: 0x44 */ 96 __I uint32_t CH_FMSG_DATA; /**< Channel '0' Fast Message Data Read Register..Channel '7' Fast Message Data Read Register, array offset: 0x6C, array step: 0x44 */ 97 __I uint32_t CH_FMSG_CRC; /**< Channel '0' Fast Message CRC Read Register..Channel '7' Fast Message CRC Read Register, array offset: 0x70, array step: 0x44 */ 98 __I uint32_t CH_FMSG_TS; /**< Channel '0' Fast Message Time Stamp Read Register..Channel '7' Fast Message Time Stamp Read Register, array offset: 0x74, array step: 0x44 */ 99 __I uint32_t CH_SMSG_BIT3; /**< Channel '0' Serial Message Read Register (Bit 3)..Channel '7' Serial Message Read Register (Bit 3), array offset: 0x78, array step: 0x44 */ 100 __I uint32_t CH_SMSG_BIT2; /**< Channel '0' Serial Message Read Register (Bit 2)..Channel '7' Serial Message Read Register (Bit 2), array offset: 0x7C, array step: 0x44 */ 101 __I uint32_t CH_SMSG_TS; /**< Channel '0' Serial Message Time Stamp Read..Channel '7' Serial Message Time Stamp Read, array offset: 0x80, array step: 0x44 */ 102 __I uint32_t CH_F_DMA_RD; /**< Channel '0' DMA Fast Message Data Read..Channel '7' DMA Fast Message Data Read, array offset: 0x84, array step: 0x44 */ 103 __I uint32_t CH_F_DMA_CRC; /**< Channel '0' DMA Fast Message CRC Read..Channel '7' DMA Fast Message CRC Read, array offset: 0x88, array step: 0x44 */ 104 __I uint32_t CH_F_DMA_TS; /**< Channel '0' DMA Fast Message Time Stamp Read..Channel '7' DMA Fast Message Time Stamp Read, array offset: 0x8C, array step: 0x44 */ 105 __I uint32_t CH_S_DMA_RD; /**< Channel '0' DMA Slow Serial Message Bit3 Read..Channel '7' DMA Slow Serial Message Bit3 Read, array offset: 0x90, array step: 0x44 */ 106 __I uint32_t CH_S_DMA_CRC; /**< Channel '0' DMA Slow Serial Message Bit2 Read..Channel '7' DMA Slow Serial Message Bit2 Read, array offset: 0x94, array step: 0x44 */ 107 __I uint32_t CH_S_DMA_TS; /**< Channel '0' DMA Slow Serial Message Time Stamp Read..Channel '7' DMA Slow Serial Message Time Stamp Read, array offset: 0x98, array step: 0x44 */ 108 __I uint32_t CHNL_TIMESTAMP; /**< Channel '0' Time Stamp..Channel '7' Time Stamp, array offset: 0x9C, array step: 0x44 */ 109 __IO uint32_t CHNL_COUNTER; /**< Channel '0' Counter..Channel '7' Counter, array offset: 0xA0, array step: 0x44 */ 110 } CNL[SRX_CNL_COUNT]; 111 } SRX_Type, *SRX_MemMapPtr; 112 113 /** Number of instances of the SRX module. */ 114 #define SRX_INSTANCE_COUNT (2u) 115 116 /* SRX - Peripheral instance base addresses */ 117 /** Peripheral SRX_0 base address */ 118 #define IP_SRX_0_BASE (0x40A50000u) 119 /** Peripheral SRX_0 base pointer */ 120 #define IP_SRX_0 ((SRX_Type *)IP_SRX_0_BASE) 121 /** Peripheral SRX_1 base address */ 122 #define IP_SRX_1_BASE (0x42050000u) 123 /** Peripheral SRX_1 base pointer */ 124 #define IP_SRX_1 ((SRX_Type *)IP_SRX_1_BASE) 125 /** Array initializer of SRX peripheral base addresses */ 126 #define IP_SRX_BASE_ADDRS { IP_SRX_0_BASE, IP_SRX_1_BASE } 127 /** Array initializer of SRX peripheral base pointers */ 128 #define IP_SRX_BASE_PTRS { IP_SRX_0, IP_SRX_1 } 129 130 /* ---------------------------------------------------------------------------- 131 -- SRX Register Masks 132 ---------------------------------------------------------------------------- */ 133 134 /*! 135 * @addtogroup SRX_Register_Masks SRX Register Masks 136 * @{ 137 */ 138 139 /*! @name GBL_CTRL - Global Control Register */ 140 /*! @{ */ 141 142 #define SRX_GBL_CTRL_SENT_EN_MASK (0x1U) 143 #define SRX_GBL_CTRL_SENT_EN_SHIFT (0U) 144 #define SRX_GBL_CTRL_SENT_EN_WIDTH (1U) 145 #define SRX_GBL_CTRL_SENT_EN(x) (((uint32_t)(((uint32_t)(x)) << SRX_GBL_CTRL_SENT_EN_SHIFT)) & SRX_GBL_CTRL_SENT_EN_MASK) 146 147 #define SRX_GBL_CTRL_DBG_FRZ_MASK (0x4U) 148 #define SRX_GBL_CTRL_DBG_FRZ_SHIFT (2U) 149 #define SRX_GBL_CTRL_DBG_FRZ_WIDTH (1U) 150 #define SRX_GBL_CTRL_DBG_FRZ(x) (((uint32_t)(((uint32_t)(x)) << SRX_GBL_CTRL_DBG_FRZ_SHIFT)) & SRX_GBL_CTRL_DBG_FRZ_MASK) 151 152 #define SRX_GBL_CTRL_FAST_CLR_MASK (0x10U) 153 #define SRX_GBL_CTRL_FAST_CLR_SHIFT (4U) 154 #define SRX_GBL_CTRL_FAST_CLR_WIDTH (1U) 155 #define SRX_GBL_CTRL_FAST_CLR(x) (((uint32_t)(((uint32_t)(x)) << SRX_GBL_CTRL_FAST_CLR_SHIFT)) & SRX_GBL_CTRL_FAST_CLR_MASK) 156 157 #define SRX_GBL_CTRL_SMDUIE_MASK (0x100U) 158 #define SRX_GBL_CTRL_SMDUIE_SHIFT (8U) 159 #define SRX_GBL_CTRL_SMDUIE_WIDTH (1U) 160 #define SRX_GBL_CTRL_SMDUIE(x) (((uint32_t)(((uint32_t)(x)) << SRX_GBL_CTRL_SMDUIE_SHIFT)) & SRX_GBL_CTRL_SMDUIE_MASK) 161 162 #define SRX_GBL_CTRL_FMDUIE_MASK (0x200U) 163 #define SRX_GBL_CTRL_FMDUIE_SHIFT (9U) 164 #define SRX_GBL_CTRL_FMDUIE_WIDTH (1U) 165 #define SRX_GBL_CTRL_FMDUIE(x) (((uint32_t)(((uint32_t)(x)) << SRX_GBL_CTRL_FMDUIE_SHIFT)) & SRX_GBL_CTRL_FMDUIE_MASK) 166 167 #define SRX_GBL_CTRL_FMFOIE_MASK (0x400U) 168 #define SRX_GBL_CTRL_FMFOIE_SHIFT (10U) 169 #define SRX_GBL_CTRL_FMFOIE_WIDTH (1U) 170 #define SRX_GBL_CTRL_FMFOIE(x) (((uint32_t)(((uint32_t)(x)) << SRX_GBL_CTRL_FMFOIE_SHIFT)) & SRX_GBL_CTRL_FMFOIE_MASK) 171 172 #define SRX_GBL_CTRL_FIFOWM_MASK (0x1F0000U) 173 #define SRX_GBL_CTRL_FIFOWM_SHIFT (16U) 174 #define SRX_GBL_CTRL_FIFOWM_WIDTH (5U) 175 #define SRX_GBL_CTRL_FIFOWM(x) (((uint32_t)(((uint32_t)(x)) << SRX_GBL_CTRL_FIFOWM_SHIFT)) & SRX_GBL_CTRL_FIFOWM_MASK) 176 177 #define SRX_GBL_CTRL_TSPRSC_MASK (0xFF000000U) 178 #define SRX_GBL_CTRL_TSPRSC_SHIFT (24U) 179 #define SRX_GBL_CTRL_TSPRSC_WIDTH (8U) 180 #define SRX_GBL_CTRL_TSPRSC(x) (((uint32_t)(((uint32_t)(x)) << SRX_GBL_CTRL_TSPRSC_SHIFT)) & SRX_GBL_CTRL_TSPRSC_MASK) 181 /*! @} */ 182 183 /*! @name CHNL_EN - Channel Enable Register */ 184 /*! @{ */ 185 186 #define SRX_CHNL_EN_EN_CH_MASK (0xFFU) 187 #define SRX_CHNL_EN_EN_CH_SHIFT (0U) 188 #define SRX_CHNL_EN_EN_CH_WIDTH (8U) 189 #define SRX_CHNL_EN_EN_CH(x) (((uint32_t)(((uint32_t)(x)) << SRX_CHNL_EN_EN_CH_SHIFT)) & SRX_CHNL_EN_EN_CH_MASK) 190 /*! @} */ 191 192 /*! @name SLOW_MSG_UVF - Slow Channel Status */ 193 /*! @{ */ 194 195 #define SRX_SLOW_MSG_UVF_CH0_SMDU_MASK (0x1U) 196 #define SRX_SLOW_MSG_UVF_CH0_SMDU_SHIFT (0U) 197 #define SRX_SLOW_MSG_UVF_CH0_SMDU_WIDTH (1U) 198 #define SRX_SLOW_MSG_UVF_CH0_SMDU(x) (((uint32_t)(((uint32_t)(x)) << SRX_SLOW_MSG_UVF_CH0_SMDU_SHIFT)) & SRX_SLOW_MSG_UVF_CH0_SMDU_MASK) 199 200 #define SRX_SLOW_MSG_UVF_CH1_SMDU_MASK (0x2U) 201 #define SRX_SLOW_MSG_UVF_CH1_SMDU_SHIFT (1U) 202 #define SRX_SLOW_MSG_UVF_CH1_SMDU_WIDTH (1U) 203 #define SRX_SLOW_MSG_UVF_CH1_SMDU(x) (((uint32_t)(((uint32_t)(x)) << SRX_SLOW_MSG_UVF_CH1_SMDU_SHIFT)) & SRX_SLOW_MSG_UVF_CH1_SMDU_MASK) 204 205 #define SRX_SLOW_MSG_UVF_CH2_SMDU_MASK (0x4U) 206 #define SRX_SLOW_MSG_UVF_CH2_SMDU_SHIFT (2U) 207 #define SRX_SLOW_MSG_UVF_CH2_SMDU_WIDTH (1U) 208 #define SRX_SLOW_MSG_UVF_CH2_SMDU(x) (((uint32_t)(((uint32_t)(x)) << SRX_SLOW_MSG_UVF_CH2_SMDU_SHIFT)) & SRX_SLOW_MSG_UVF_CH2_SMDU_MASK) 209 210 #define SRX_SLOW_MSG_UVF_CH3_SMDU_MASK (0x8U) 211 #define SRX_SLOW_MSG_UVF_CH3_SMDU_SHIFT (3U) 212 #define SRX_SLOW_MSG_UVF_CH3_SMDU_WIDTH (1U) 213 #define SRX_SLOW_MSG_UVF_CH3_SMDU(x) (((uint32_t)(((uint32_t)(x)) << SRX_SLOW_MSG_UVF_CH3_SMDU_SHIFT)) & SRX_SLOW_MSG_UVF_CH3_SMDU_MASK) 214 215 #define SRX_SLOW_MSG_UVF_CH4_SMDU_MASK (0x10U) 216 #define SRX_SLOW_MSG_UVF_CH4_SMDU_SHIFT (4U) 217 #define SRX_SLOW_MSG_UVF_CH4_SMDU_WIDTH (1U) 218 #define SRX_SLOW_MSG_UVF_CH4_SMDU(x) (((uint32_t)(((uint32_t)(x)) << SRX_SLOW_MSG_UVF_CH4_SMDU_SHIFT)) & SRX_SLOW_MSG_UVF_CH4_SMDU_MASK) 219 220 #define SRX_SLOW_MSG_UVF_CH5_SMDU_MASK (0x20U) 221 #define SRX_SLOW_MSG_UVF_CH5_SMDU_SHIFT (5U) 222 #define SRX_SLOW_MSG_UVF_CH5_SMDU_WIDTH (1U) 223 #define SRX_SLOW_MSG_UVF_CH5_SMDU(x) (((uint32_t)(((uint32_t)(x)) << SRX_SLOW_MSG_UVF_CH5_SMDU_SHIFT)) & SRX_SLOW_MSG_UVF_CH5_SMDU_MASK) 224 225 #define SRX_SLOW_MSG_UVF_CH6_SMDU_MASK (0x40U) 226 #define SRX_SLOW_MSG_UVF_CH6_SMDU_SHIFT (6U) 227 #define SRX_SLOW_MSG_UVF_CH6_SMDU_WIDTH (1U) 228 #define SRX_SLOW_MSG_UVF_CH6_SMDU(x) (((uint32_t)(((uint32_t)(x)) << SRX_SLOW_MSG_UVF_CH6_SMDU_SHIFT)) & SRX_SLOW_MSG_UVF_CH6_SMDU_MASK) 229 230 #define SRX_SLOW_MSG_UVF_CH7_SMDU_MASK (0x80U) 231 #define SRX_SLOW_MSG_UVF_CH7_SMDU_SHIFT (7U) 232 #define SRX_SLOW_MSG_UVF_CH7_SMDU_WIDTH (1U) 233 #define SRX_SLOW_MSG_UVF_CH7_SMDU(x) (((uint32_t)(((uint32_t)(x)) << SRX_SLOW_MSG_UVF_CH7_SMDU_SHIFT)) & SRX_SLOW_MSG_UVF_CH7_SMDU_MASK) 234 /*! @} */ 235 236 /*! @name FMSG_RDY - Fast Message Ready Status Register */ 237 /*! @{ */ 238 239 #define SRX_FMSG_RDY_F_RDY0_MASK (0x1U) 240 #define SRX_FMSG_RDY_F_RDY0_SHIFT (0U) 241 #define SRX_FMSG_RDY_F_RDY0_WIDTH (1U) 242 #define SRX_FMSG_RDY_F_RDY0(x) (((uint32_t)(((uint32_t)(x)) << SRX_FMSG_RDY_F_RDY0_SHIFT)) & SRX_FMSG_RDY_F_RDY0_MASK) 243 244 #define SRX_FMSG_RDY_F_RDY1_MASK (0x2U) 245 #define SRX_FMSG_RDY_F_RDY1_SHIFT (1U) 246 #define SRX_FMSG_RDY_F_RDY1_WIDTH (1U) 247 #define SRX_FMSG_RDY_F_RDY1(x) (((uint32_t)(((uint32_t)(x)) << SRX_FMSG_RDY_F_RDY1_SHIFT)) & SRX_FMSG_RDY_F_RDY1_MASK) 248 249 #define SRX_FMSG_RDY_F_RDY2_MASK (0x4U) 250 #define SRX_FMSG_RDY_F_RDY2_SHIFT (2U) 251 #define SRX_FMSG_RDY_F_RDY2_WIDTH (1U) 252 #define SRX_FMSG_RDY_F_RDY2(x) (((uint32_t)(((uint32_t)(x)) << SRX_FMSG_RDY_F_RDY2_SHIFT)) & SRX_FMSG_RDY_F_RDY2_MASK) 253 254 #define SRX_FMSG_RDY_F_RDY3_MASK (0x8U) 255 #define SRX_FMSG_RDY_F_RDY3_SHIFT (3U) 256 #define SRX_FMSG_RDY_F_RDY3_WIDTH (1U) 257 #define SRX_FMSG_RDY_F_RDY3(x) (((uint32_t)(((uint32_t)(x)) << SRX_FMSG_RDY_F_RDY3_SHIFT)) & SRX_FMSG_RDY_F_RDY3_MASK) 258 259 #define SRX_FMSG_RDY_F_RDY4_MASK (0x10U) 260 #define SRX_FMSG_RDY_F_RDY4_SHIFT (4U) 261 #define SRX_FMSG_RDY_F_RDY4_WIDTH (1U) 262 #define SRX_FMSG_RDY_F_RDY4(x) (((uint32_t)(((uint32_t)(x)) << SRX_FMSG_RDY_F_RDY4_SHIFT)) & SRX_FMSG_RDY_F_RDY4_MASK) 263 264 #define SRX_FMSG_RDY_F_RDY5_MASK (0x20U) 265 #define SRX_FMSG_RDY_F_RDY5_SHIFT (5U) 266 #define SRX_FMSG_RDY_F_RDY5_WIDTH (1U) 267 #define SRX_FMSG_RDY_F_RDY5(x) (((uint32_t)(((uint32_t)(x)) << SRX_FMSG_RDY_F_RDY5_SHIFT)) & SRX_FMSG_RDY_F_RDY5_MASK) 268 269 #define SRX_FMSG_RDY_F_RDY6_MASK (0x40U) 270 #define SRX_FMSG_RDY_F_RDY6_SHIFT (6U) 271 #define SRX_FMSG_RDY_F_RDY6_WIDTH (1U) 272 #define SRX_FMSG_RDY_F_RDY6(x) (((uint32_t)(((uint32_t)(x)) << SRX_FMSG_RDY_F_RDY6_SHIFT)) & SRX_FMSG_RDY_F_RDY6_MASK) 273 274 #define SRX_FMSG_RDY_F_RDY7_MASK (0x80U) 275 #define SRX_FMSG_RDY_F_RDY7_SHIFT (7U) 276 #define SRX_FMSG_RDY_F_RDY7_WIDTH (1U) 277 #define SRX_FMSG_RDY_F_RDY7(x) (((uint32_t)(((uint32_t)(x)) << SRX_FMSG_RDY_F_RDY7_SHIFT)) & SRX_FMSG_RDY_F_RDY7_MASK) 278 /*! @} */ 279 280 /*! @name SMSG_RDY - Slow Serial Message Ready Status Register */ 281 /*! @{ */ 282 283 #define SRX_SMSG_RDY_S_RDY0_MASK (0x1U) 284 #define SRX_SMSG_RDY_S_RDY0_SHIFT (0U) 285 #define SRX_SMSG_RDY_S_RDY0_WIDTH (1U) 286 #define SRX_SMSG_RDY_S_RDY0(x) (((uint32_t)(((uint32_t)(x)) << SRX_SMSG_RDY_S_RDY0_SHIFT)) & SRX_SMSG_RDY_S_RDY0_MASK) 287 288 #define SRX_SMSG_RDY_S_RDY1_MASK (0x2U) 289 #define SRX_SMSG_RDY_S_RDY1_SHIFT (1U) 290 #define SRX_SMSG_RDY_S_RDY1_WIDTH (1U) 291 #define SRX_SMSG_RDY_S_RDY1(x) (((uint32_t)(((uint32_t)(x)) << SRX_SMSG_RDY_S_RDY1_SHIFT)) & SRX_SMSG_RDY_S_RDY1_MASK) 292 293 #define SRX_SMSG_RDY_S_RDY2_MASK (0x4U) 294 #define SRX_SMSG_RDY_S_RDY2_SHIFT (2U) 295 #define SRX_SMSG_RDY_S_RDY2_WIDTH (1U) 296 #define SRX_SMSG_RDY_S_RDY2(x) (((uint32_t)(((uint32_t)(x)) << SRX_SMSG_RDY_S_RDY2_SHIFT)) & SRX_SMSG_RDY_S_RDY2_MASK) 297 298 #define SRX_SMSG_RDY_S_RDY3_MASK (0x8U) 299 #define SRX_SMSG_RDY_S_RDY3_SHIFT (3U) 300 #define SRX_SMSG_RDY_S_RDY3_WIDTH (1U) 301 #define SRX_SMSG_RDY_S_RDY3(x) (((uint32_t)(((uint32_t)(x)) << SRX_SMSG_RDY_S_RDY3_SHIFT)) & SRX_SMSG_RDY_S_RDY3_MASK) 302 303 #define SRX_SMSG_RDY_S_RDY4_MASK (0x10U) 304 #define SRX_SMSG_RDY_S_RDY4_SHIFT (4U) 305 #define SRX_SMSG_RDY_S_RDY4_WIDTH (1U) 306 #define SRX_SMSG_RDY_S_RDY4(x) (((uint32_t)(((uint32_t)(x)) << SRX_SMSG_RDY_S_RDY4_SHIFT)) & SRX_SMSG_RDY_S_RDY4_MASK) 307 308 #define SRX_SMSG_RDY_S_RDY5_MASK (0x20U) 309 #define SRX_SMSG_RDY_S_RDY5_SHIFT (5U) 310 #define SRX_SMSG_RDY_S_RDY5_WIDTH (1U) 311 #define SRX_SMSG_RDY_S_RDY5(x) (((uint32_t)(((uint32_t)(x)) << SRX_SMSG_RDY_S_RDY5_SHIFT)) & SRX_SMSG_RDY_S_RDY5_MASK) 312 313 #define SRX_SMSG_RDY_S_RDY6_MASK (0x40U) 314 #define SRX_SMSG_RDY_S_RDY6_SHIFT (6U) 315 #define SRX_SMSG_RDY_S_RDY6_WIDTH (1U) 316 #define SRX_SMSG_RDY_S_RDY6(x) (((uint32_t)(((uint32_t)(x)) << SRX_SMSG_RDY_S_RDY6_SHIFT)) & SRX_SMSG_RDY_S_RDY6_MASK) 317 318 #define SRX_SMSG_RDY_S_RDY7_MASK (0x80U) 319 #define SRX_SMSG_RDY_S_RDY7_SHIFT (7U) 320 #define SRX_SMSG_RDY_S_RDY7_WIDTH (1U) 321 #define SRX_SMSG_RDY_S_RDY7(x) (((uint32_t)(((uint32_t)(x)) << SRX_SMSG_RDY_S_RDY7_SHIFT)) & SRX_SMSG_RDY_S_RDY7_MASK) 322 /*! @} */ 323 324 /*! @name CHNL_FIFO_EN - Channel FIFO Enable */ 325 /*! @{ */ 326 327 #define SRX_CHNL_FIFO_EN_CH0FIFO_EN_MASK (0x1U) 328 #define SRX_CHNL_FIFO_EN_CH0FIFO_EN_SHIFT (0U) 329 #define SRX_CHNL_FIFO_EN_CH0FIFO_EN_WIDTH (1U) 330 #define SRX_CHNL_FIFO_EN_CH0FIFO_EN(x) (((uint32_t)(((uint32_t)(x)) << SRX_CHNL_FIFO_EN_CH0FIFO_EN_SHIFT)) & SRX_CHNL_FIFO_EN_CH0FIFO_EN_MASK) 331 332 #define SRX_CHNL_FIFO_EN_CH1FIFO_EN_MASK (0x2U) 333 #define SRX_CHNL_FIFO_EN_CH1FIFO_EN_SHIFT (1U) 334 #define SRX_CHNL_FIFO_EN_CH1FIFO_EN_WIDTH (1U) 335 #define SRX_CHNL_FIFO_EN_CH1FIFO_EN(x) (((uint32_t)(((uint32_t)(x)) << SRX_CHNL_FIFO_EN_CH1FIFO_EN_SHIFT)) & SRX_CHNL_FIFO_EN_CH1FIFO_EN_MASK) 336 337 #define SRX_CHNL_FIFO_EN_CH2FIFO_EN_MASK (0x4U) 338 #define SRX_CHNL_FIFO_EN_CH2FIFO_EN_SHIFT (2U) 339 #define SRX_CHNL_FIFO_EN_CH2FIFO_EN_WIDTH (1U) 340 #define SRX_CHNL_FIFO_EN_CH2FIFO_EN(x) (((uint32_t)(((uint32_t)(x)) << SRX_CHNL_FIFO_EN_CH2FIFO_EN_SHIFT)) & SRX_CHNL_FIFO_EN_CH2FIFO_EN_MASK) 341 342 #define SRX_CHNL_FIFO_EN_CH3FIFO_EN_MASK (0x8U) 343 #define SRX_CHNL_FIFO_EN_CH3FIFO_EN_SHIFT (3U) 344 #define SRX_CHNL_FIFO_EN_CH3FIFO_EN_WIDTH (1U) 345 #define SRX_CHNL_FIFO_EN_CH3FIFO_EN(x) (((uint32_t)(((uint32_t)(x)) << SRX_CHNL_FIFO_EN_CH3FIFO_EN_SHIFT)) & SRX_CHNL_FIFO_EN_CH3FIFO_EN_MASK) 346 347 #define SRX_CHNL_FIFO_EN_CH4FIFO_EN_MASK (0x10U) 348 #define SRX_CHNL_FIFO_EN_CH4FIFO_EN_SHIFT (4U) 349 #define SRX_CHNL_FIFO_EN_CH4FIFO_EN_WIDTH (1U) 350 #define SRX_CHNL_FIFO_EN_CH4FIFO_EN(x) (((uint32_t)(((uint32_t)(x)) << SRX_CHNL_FIFO_EN_CH4FIFO_EN_SHIFT)) & SRX_CHNL_FIFO_EN_CH4FIFO_EN_MASK) 351 352 #define SRX_CHNL_FIFO_EN_CH5FIFO_EN_MASK (0x20U) 353 #define SRX_CHNL_FIFO_EN_CH5FIFO_EN_SHIFT (5U) 354 #define SRX_CHNL_FIFO_EN_CH5FIFO_EN_WIDTH (1U) 355 #define SRX_CHNL_FIFO_EN_CH5FIFO_EN(x) (((uint32_t)(((uint32_t)(x)) << SRX_CHNL_FIFO_EN_CH5FIFO_EN_SHIFT)) & SRX_CHNL_FIFO_EN_CH5FIFO_EN_MASK) 356 357 #define SRX_CHNL_FIFO_EN_CH6FIFO_EN_MASK (0x40U) 358 #define SRX_CHNL_FIFO_EN_CH6FIFO_EN_SHIFT (6U) 359 #define SRX_CHNL_FIFO_EN_CH6FIFO_EN_WIDTH (1U) 360 #define SRX_CHNL_FIFO_EN_CH6FIFO_EN(x) (((uint32_t)(((uint32_t)(x)) << SRX_CHNL_FIFO_EN_CH6FIFO_EN_SHIFT)) & SRX_CHNL_FIFO_EN_CH6FIFO_EN_MASK) 361 362 #define SRX_CHNL_FIFO_EN_CH7FIFO_EN_MASK (0x80U) 363 #define SRX_CHNL_FIFO_EN_CH7FIFO_EN_SHIFT (7U) 364 #define SRX_CHNL_FIFO_EN_CH7FIFO_EN_WIDTH (1U) 365 #define SRX_CHNL_FIFO_EN_CH7FIFO_EN(x) (((uint32_t)(((uint32_t)(x)) << SRX_CHNL_FIFO_EN_CH7FIFO_EN_SHIFT)) & SRX_CHNL_FIFO_EN_CH7FIFO_EN_MASK) 366 /*! @} */ 367 368 /*! @name DATA_CTRL1 - Data Control Register 1 */ 369 /*! @{ */ 370 371 #define SRX_DATA_CTRL1_NIBBCH7_MASK (0x7U) 372 #define SRX_DATA_CTRL1_NIBBCH7_SHIFT (0U) 373 #define SRX_DATA_CTRL1_NIBBCH7_WIDTH (3U) 374 #define SRX_DATA_CTRL1_NIBBCH7(x) (((uint32_t)(((uint32_t)(x)) << SRX_DATA_CTRL1_NIBBCH7_SHIFT)) & SRX_DATA_CTRL1_NIBBCH7_MASK) 375 376 #define SRX_DATA_CTRL1_NIBBCH6_MASK (0x70U) 377 #define SRX_DATA_CTRL1_NIBBCH6_SHIFT (4U) 378 #define SRX_DATA_CTRL1_NIBBCH6_WIDTH (3U) 379 #define SRX_DATA_CTRL1_NIBBCH6(x) (((uint32_t)(((uint32_t)(x)) << SRX_DATA_CTRL1_NIBBCH6_SHIFT)) & SRX_DATA_CTRL1_NIBBCH6_MASK) 380 381 #define SRX_DATA_CTRL1_NIBBCH5_MASK (0x700U) 382 #define SRX_DATA_CTRL1_NIBBCH5_SHIFT (8U) 383 #define SRX_DATA_CTRL1_NIBBCH5_WIDTH (3U) 384 #define SRX_DATA_CTRL1_NIBBCH5(x) (((uint32_t)(((uint32_t)(x)) << SRX_DATA_CTRL1_NIBBCH5_SHIFT)) & SRX_DATA_CTRL1_NIBBCH5_MASK) 385 386 #define SRX_DATA_CTRL1_NIBBCH4_MASK (0x7000U) 387 #define SRX_DATA_CTRL1_NIBBCH4_SHIFT (12U) 388 #define SRX_DATA_CTRL1_NIBBCH4_WIDTH (3U) 389 #define SRX_DATA_CTRL1_NIBBCH4(x) (((uint32_t)(((uint32_t)(x)) << SRX_DATA_CTRL1_NIBBCH4_SHIFT)) & SRX_DATA_CTRL1_NIBBCH4_MASK) 390 391 #define SRX_DATA_CTRL1_NIBBCH3_MASK (0x70000U) 392 #define SRX_DATA_CTRL1_NIBBCH3_SHIFT (16U) 393 #define SRX_DATA_CTRL1_NIBBCH3_WIDTH (3U) 394 #define SRX_DATA_CTRL1_NIBBCH3(x) (((uint32_t)(((uint32_t)(x)) << SRX_DATA_CTRL1_NIBBCH3_SHIFT)) & SRX_DATA_CTRL1_NIBBCH3_MASK) 395 396 #define SRX_DATA_CTRL1_NIBBCH2_MASK (0x700000U) 397 #define SRX_DATA_CTRL1_NIBBCH2_SHIFT (20U) 398 #define SRX_DATA_CTRL1_NIBBCH2_WIDTH (3U) 399 #define SRX_DATA_CTRL1_NIBBCH2(x) (((uint32_t)(((uint32_t)(x)) << SRX_DATA_CTRL1_NIBBCH2_SHIFT)) & SRX_DATA_CTRL1_NIBBCH2_MASK) 400 401 #define SRX_DATA_CTRL1_NIBBCH1_MASK (0x7000000U) 402 #define SRX_DATA_CTRL1_NIBBCH1_SHIFT (24U) 403 #define SRX_DATA_CTRL1_NIBBCH1_WIDTH (3U) 404 #define SRX_DATA_CTRL1_NIBBCH1(x) (((uint32_t)(((uint32_t)(x)) << SRX_DATA_CTRL1_NIBBCH1_SHIFT)) & SRX_DATA_CTRL1_NIBBCH1_MASK) 405 406 #define SRX_DATA_CTRL1_NIBBCH0_MASK (0x70000000U) 407 #define SRX_DATA_CTRL1_NIBBCH0_SHIFT (28U) 408 #define SRX_DATA_CTRL1_NIBBCH0_WIDTH (3U) 409 #define SRX_DATA_CTRL1_NIBBCH0(x) (((uint32_t)(((uint32_t)(x)) << SRX_DATA_CTRL1_NIBBCH0_SHIFT)) & SRX_DATA_CTRL1_NIBBCH0_MASK) 410 /*! @} */ 411 412 /*! @name CHNL_OVF_UVF - Fast Channel Status */ 413 /*! @{ */ 414 415 #define SRX_CHNL_OVF_UVF_FDMU_CH0_MASK (0x1U) 416 #define SRX_CHNL_OVF_UVF_FDMU_CH0_SHIFT (0U) 417 #define SRX_CHNL_OVF_UVF_FDMU_CH0_WIDTH (1U) 418 #define SRX_CHNL_OVF_UVF_FDMU_CH0(x) (((uint32_t)(((uint32_t)(x)) << SRX_CHNL_OVF_UVF_FDMU_CH0_SHIFT)) & SRX_CHNL_OVF_UVF_FDMU_CH0_MASK) 419 420 #define SRX_CHNL_OVF_UVF_FDMU_CH1_MASK (0x2U) 421 #define SRX_CHNL_OVF_UVF_FDMU_CH1_SHIFT (1U) 422 #define SRX_CHNL_OVF_UVF_FDMU_CH1_WIDTH (1U) 423 #define SRX_CHNL_OVF_UVF_FDMU_CH1(x) (((uint32_t)(((uint32_t)(x)) << SRX_CHNL_OVF_UVF_FDMU_CH1_SHIFT)) & SRX_CHNL_OVF_UVF_FDMU_CH1_MASK) 424 425 #define SRX_CHNL_OVF_UVF_FDMU_CH2_MASK (0x4U) 426 #define SRX_CHNL_OVF_UVF_FDMU_CH2_SHIFT (2U) 427 #define SRX_CHNL_OVF_UVF_FDMU_CH2_WIDTH (1U) 428 #define SRX_CHNL_OVF_UVF_FDMU_CH2(x) (((uint32_t)(((uint32_t)(x)) << SRX_CHNL_OVF_UVF_FDMU_CH2_SHIFT)) & SRX_CHNL_OVF_UVF_FDMU_CH2_MASK) 429 430 #define SRX_CHNL_OVF_UVF_FDMU_CH3_MASK (0x8U) 431 #define SRX_CHNL_OVF_UVF_FDMU_CH3_SHIFT (3U) 432 #define SRX_CHNL_OVF_UVF_FDMU_CH3_WIDTH (1U) 433 #define SRX_CHNL_OVF_UVF_FDMU_CH3(x) (((uint32_t)(((uint32_t)(x)) << SRX_CHNL_OVF_UVF_FDMU_CH3_SHIFT)) & SRX_CHNL_OVF_UVF_FDMU_CH3_MASK) 434 435 #define SRX_CHNL_OVF_UVF_FDMU_CH4_MASK (0x10U) 436 #define SRX_CHNL_OVF_UVF_FDMU_CH4_SHIFT (4U) 437 #define SRX_CHNL_OVF_UVF_FDMU_CH4_WIDTH (1U) 438 #define SRX_CHNL_OVF_UVF_FDMU_CH4(x) (((uint32_t)(((uint32_t)(x)) << SRX_CHNL_OVF_UVF_FDMU_CH4_SHIFT)) & SRX_CHNL_OVF_UVF_FDMU_CH4_MASK) 439 440 #define SRX_CHNL_OVF_UVF_FDMU_CH5_MASK (0x20U) 441 #define SRX_CHNL_OVF_UVF_FDMU_CH5_SHIFT (5U) 442 #define SRX_CHNL_OVF_UVF_FDMU_CH5_WIDTH (1U) 443 #define SRX_CHNL_OVF_UVF_FDMU_CH5(x) (((uint32_t)(((uint32_t)(x)) << SRX_CHNL_OVF_UVF_FDMU_CH5_SHIFT)) & SRX_CHNL_OVF_UVF_FDMU_CH5_MASK) 444 445 #define SRX_CHNL_OVF_UVF_FDMU_CH6_MASK (0x40U) 446 #define SRX_CHNL_OVF_UVF_FDMU_CH6_SHIFT (6U) 447 #define SRX_CHNL_OVF_UVF_FDMU_CH6_WIDTH (1U) 448 #define SRX_CHNL_OVF_UVF_FDMU_CH6(x) (((uint32_t)(((uint32_t)(x)) << SRX_CHNL_OVF_UVF_FDMU_CH6_SHIFT)) & SRX_CHNL_OVF_UVF_FDMU_CH6_MASK) 449 450 #define SRX_CHNL_OVF_UVF_FDMU_CH7_MASK (0x80U) 451 #define SRX_CHNL_OVF_UVF_FDMU_CH7_SHIFT (7U) 452 #define SRX_CHNL_OVF_UVF_FDMU_CH7_WIDTH (1U) 453 #define SRX_CHNL_OVF_UVF_FDMU_CH7(x) (((uint32_t)(((uint32_t)(x)) << SRX_CHNL_OVF_UVF_FDMU_CH7_SHIFT)) & SRX_CHNL_OVF_UVF_FDMU_CH7_MASK) 454 455 #define SRX_CHNL_OVF_UVF_FMFO_CH0_MASK (0x10000U) 456 #define SRX_CHNL_OVF_UVF_FMFO_CH0_SHIFT (16U) 457 #define SRX_CHNL_OVF_UVF_FMFO_CH0_WIDTH (1U) 458 #define SRX_CHNL_OVF_UVF_FMFO_CH0(x) (((uint32_t)(((uint32_t)(x)) << SRX_CHNL_OVF_UVF_FMFO_CH0_SHIFT)) & SRX_CHNL_OVF_UVF_FMFO_CH0_MASK) 459 460 #define SRX_CHNL_OVF_UVF_FMFO_CH1_MASK (0x20000U) 461 #define SRX_CHNL_OVF_UVF_FMFO_CH1_SHIFT (17U) 462 #define SRX_CHNL_OVF_UVF_FMFO_CH1_WIDTH (1U) 463 #define SRX_CHNL_OVF_UVF_FMFO_CH1(x) (((uint32_t)(((uint32_t)(x)) << SRX_CHNL_OVF_UVF_FMFO_CH1_SHIFT)) & SRX_CHNL_OVF_UVF_FMFO_CH1_MASK) 464 465 #define SRX_CHNL_OVF_UVF_FMFO_CH2_MASK (0x40000U) 466 #define SRX_CHNL_OVF_UVF_FMFO_CH2_SHIFT (18U) 467 #define SRX_CHNL_OVF_UVF_FMFO_CH2_WIDTH (1U) 468 #define SRX_CHNL_OVF_UVF_FMFO_CH2(x) (((uint32_t)(((uint32_t)(x)) << SRX_CHNL_OVF_UVF_FMFO_CH2_SHIFT)) & SRX_CHNL_OVF_UVF_FMFO_CH2_MASK) 469 470 #define SRX_CHNL_OVF_UVF_FMFO_CH3_MASK (0x80000U) 471 #define SRX_CHNL_OVF_UVF_FMFO_CH3_SHIFT (19U) 472 #define SRX_CHNL_OVF_UVF_FMFO_CH3_WIDTH (1U) 473 #define SRX_CHNL_OVF_UVF_FMFO_CH3(x) (((uint32_t)(((uint32_t)(x)) << SRX_CHNL_OVF_UVF_FMFO_CH3_SHIFT)) & SRX_CHNL_OVF_UVF_FMFO_CH3_MASK) 474 475 #define SRX_CHNL_OVF_UVF_FMFO_CH4_MASK (0x100000U) 476 #define SRX_CHNL_OVF_UVF_FMFO_CH4_SHIFT (20U) 477 #define SRX_CHNL_OVF_UVF_FMFO_CH4_WIDTH (1U) 478 #define SRX_CHNL_OVF_UVF_FMFO_CH4(x) (((uint32_t)(((uint32_t)(x)) << SRX_CHNL_OVF_UVF_FMFO_CH4_SHIFT)) & SRX_CHNL_OVF_UVF_FMFO_CH4_MASK) 479 480 #define SRX_CHNL_OVF_UVF_FMFO_CH5_MASK (0x200000U) 481 #define SRX_CHNL_OVF_UVF_FMFO_CH5_SHIFT (21U) 482 #define SRX_CHNL_OVF_UVF_FMFO_CH5_WIDTH (1U) 483 #define SRX_CHNL_OVF_UVF_FMFO_CH5(x) (((uint32_t)(((uint32_t)(x)) << SRX_CHNL_OVF_UVF_FMFO_CH5_SHIFT)) & SRX_CHNL_OVF_UVF_FMFO_CH5_MASK) 484 485 #define SRX_CHNL_OVF_UVF_FMFO_CH6_MASK (0x400000U) 486 #define SRX_CHNL_OVF_UVF_FMFO_CH6_SHIFT (22U) 487 #define SRX_CHNL_OVF_UVF_FMFO_CH6_WIDTH (1U) 488 #define SRX_CHNL_OVF_UVF_FMFO_CH6(x) (((uint32_t)(((uint32_t)(x)) << SRX_CHNL_OVF_UVF_FMFO_CH6_SHIFT)) & SRX_CHNL_OVF_UVF_FMFO_CH6_MASK) 489 490 #define SRX_CHNL_OVF_UVF_FMFO_CH7_MASK (0x800000U) 491 #define SRX_CHNL_OVF_UVF_FMFO_CH7_SHIFT (23U) 492 #define SRX_CHNL_OVF_UVF_FMFO_CH7_WIDTH (1U) 493 #define SRX_CHNL_OVF_UVF_FMFO_CH7(x) (((uint32_t)(((uint32_t)(x)) << SRX_CHNL_OVF_UVF_FMFO_CH7_SHIFT)) & SRX_CHNL_OVF_UVF_FMFO_CH7_MASK) 494 /*! @} */ 495 496 /*! @name FDMA_CTRL - Fast Message DMA Control Register */ 497 /*! @{ */ 498 499 #define SRX_FDMA_CTRL_FDMA_EN_MASK (0xFFU) 500 #define SRX_FDMA_CTRL_FDMA_EN_SHIFT (0U) 501 #define SRX_FDMA_CTRL_FDMA_EN_WIDTH (8U) 502 #define SRX_FDMA_CTRL_FDMA_EN(x) (((uint32_t)(((uint32_t)(x)) << SRX_FDMA_CTRL_FDMA_EN_SHIFT)) & SRX_FDMA_CTRL_FDMA_EN_MASK) 503 /*! @} */ 504 505 /*! @name SDMA_CTRL - Slow Serial Message DMA Control Register */ 506 /*! @{ */ 507 508 #define SRX_SDMA_CTRL_SDMA_EN_MASK (0xFFU) 509 #define SRX_SDMA_CTRL_SDMA_EN_SHIFT (0U) 510 #define SRX_SDMA_CTRL_SDMA_EN_WIDTH (8U) 511 #define SRX_SDMA_CTRL_SDMA_EN(x) (((uint32_t)(((uint32_t)(x)) << SRX_SDMA_CTRL_SDMA_EN_SHIFT)) & SRX_SDMA_CTRL_SDMA_EN_MASK) 512 /*! @} */ 513 514 /*! @name CHNL_NB_REORD1 - Channel Nibble Reorder 1 */ 515 /*! @{ */ 516 517 #define SRX_CHNL_NB_REORD1_DATAORD7_MASK (0xFU) 518 #define SRX_CHNL_NB_REORD1_DATAORD7_SHIFT (0U) 519 #define SRX_CHNL_NB_REORD1_DATAORD7_WIDTH (4U) 520 #define SRX_CHNL_NB_REORD1_DATAORD7(x) (((uint32_t)(((uint32_t)(x)) << SRX_CHNL_NB_REORD1_DATAORD7_SHIFT)) & SRX_CHNL_NB_REORD1_DATAORD7_MASK) 521 522 #define SRX_CHNL_NB_REORD1_DATAORD6_MASK (0xF0U) 523 #define SRX_CHNL_NB_REORD1_DATAORD6_SHIFT (4U) 524 #define SRX_CHNL_NB_REORD1_DATAORD6_WIDTH (4U) 525 #define SRX_CHNL_NB_REORD1_DATAORD6(x) (((uint32_t)(((uint32_t)(x)) << SRX_CHNL_NB_REORD1_DATAORD6_SHIFT)) & SRX_CHNL_NB_REORD1_DATAORD6_MASK) 526 527 #define SRX_CHNL_NB_REORD1_DATAORD5_MASK (0xF00U) 528 #define SRX_CHNL_NB_REORD1_DATAORD5_SHIFT (8U) 529 #define SRX_CHNL_NB_REORD1_DATAORD5_WIDTH (4U) 530 #define SRX_CHNL_NB_REORD1_DATAORD5(x) (((uint32_t)(((uint32_t)(x)) << SRX_CHNL_NB_REORD1_DATAORD5_SHIFT)) & SRX_CHNL_NB_REORD1_DATAORD5_MASK) 531 532 #define SRX_CHNL_NB_REORD1_DATAORD4_MASK (0xF000U) 533 #define SRX_CHNL_NB_REORD1_DATAORD4_SHIFT (12U) 534 #define SRX_CHNL_NB_REORD1_DATAORD4_WIDTH (4U) 535 #define SRX_CHNL_NB_REORD1_DATAORD4(x) (((uint32_t)(((uint32_t)(x)) << SRX_CHNL_NB_REORD1_DATAORD4_SHIFT)) & SRX_CHNL_NB_REORD1_DATAORD4_MASK) 536 537 #define SRX_CHNL_NB_REORD1_DATAORD3_MASK (0xF0000U) 538 #define SRX_CHNL_NB_REORD1_DATAORD3_SHIFT (16U) 539 #define SRX_CHNL_NB_REORD1_DATAORD3_WIDTH (4U) 540 #define SRX_CHNL_NB_REORD1_DATAORD3(x) (((uint32_t)(((uint32_t)(x)) << SRX_CHNL_NB_REORD1_DATAORD3_SHIFT)) & SRX_CHNL_NB_REORD1_DATAORD3_MASK) 541 542 #define SRX_CHNL_NB_REORD1_DATAORD2_MASK (0xF00000U) 543 #define SRX_CHNL_NB_REORD1_DATAORD2_SHIFT (20U) 544 #define SRX_CHNL_NB_REORD1_DATAORD2_WIDTH (4U) 545 #define SRX_CHNL_NB_REORD1_DATAORD2(x) (((uint32_t)(((uint32_t)(x)) << SRX_CHNL_NB_REORD1_DATAORD2_SHIFT)) & SRX_CHNL_NB_REORD1_DATAORD2_MASK) 546 547 #define SRX_CHNL_NB_REORD1_DATAORD1_MASK (0xF000000U) 548 #define SRX_CHNL_NB_REORD1_DATAORD1_SHIFT (24U) 549 #define SRX_CHNL_NB_REORD1_DATAORD1_WIDTH (4U) 550 #define SRX_CHNL_NB_REORD1_DATAORD1(x) (((uint32_t)(((uint32_t)(x)) << SRX_CHNL_NB_REORD1_DATAORD1_SHIFT)) & SRX_CHNL_NB_REORD1_DATAORD1_MASK) 551 552 #define SRX_CHNL_NB_REORD1_DATAORD0_MASK (0xF0000000U) 553 #define SRX_CHNL_NB_REORD1_DATAORD0_SHIFT (28U) 554 #define SRX_CHNL_NB_REORD1_DATAORD0_WIDTH (4U) 555 #define SRX_CHNL_NB_REORD1_DATAORD0(x) (((uint32_t)(((uint32_t)(x)) << SRX_CHNL_NB_REORD1_DATAORD0_SHIFT)) & SRX_CHNL_NB_REORD1_DATAORD0_MASK) 556 /*! @} */ 557 558 /*! @name FMSG_RDY_IE - Fast Message Ready Interrupt Control Register */ 559 /*! @{ */ 560 561 #define SRX_FMSG_RDY_IE_FRDY_IE0_MASK (0x1U) 562 #define SRX_FMSG_RDY_IE_FRDY_IE0_SHIFT (0U) 563 #define SRX_FMSG_RDY_IE_FRDY_IE0_WIDTH (1U) 564 #define SRX_FMSG_RDY_IE_FRDY_IE0(x) (((uint32_t)(((uint32_t)(x)) << SRX_FMSG_RDY_IE_FRDY_IE0_SHIFT)) & SRX_FMSG_RDY_IE_FRDY_IE0_MASK) 565 566 #define SRX_FMSG_RDY_IE_FRDY_IE1_MASK (0x2U) 567 #define SRX_FMSG_RDY_IE_FRDY_IE1_SHIFT (1U) 568 #define SRX_FMSG_RDY_IE_FRDY_IE1_WIDTH (1U) 569 #define SRX_FMSG_RDY_IE_FRDY_IE1(x) (((uint32_t)(((uint32_t)(x)) << SRX_FMSG_RDY_IE_FRDY_IE1_SHIFT)) & SRX_FMSG_RDY_IE_FRDY_IE1_MASK) 570 571 #define SRX_FMSG_RDY_IE_FRDY_IE2_MASK (0x4U) 572 #define SRX_FMSG_RDY_IE_FRDY_IE2_SHIFT (2U) 573 #define SRX_FMSG_RDY_IE_FRDY_IE2_WIDTH (1U) 574 #define SRX_FMSG_RDY_IE_FRDY_IE2(x) (((uint32_t)(((uint32_t)(x)) << SRX_FMSG_RDY_IE_FRDY_IE2_SHIFT)) & SRX_FMSG_RDY_IE_FRDY_IE2_MASK) 575 576 #define SRX_FMSG_RDY_IE_FRDY_IE3_MASK (0x8U) 577 #define SRX_FMSG_RDY_IE_FRDY_IE3_SHIFT (3U) 578 #define SRX_FMSG_RDY_IE_FRDY_IE3_WIDTH (1U) 579 #define SRX_FMSG_RDY_IE_FRDY_IE3(x) (((uint32_t)(((uint32_t)(x)) << SRX_FMSG_RDY_IE_FRDY_IE3_SHIFT)) & SRX_FMSG_RDY_IE_FRDY_IE3_MASK) 580 581 #define SRX_FMSG_RDY_IE_FRDY_IE4_MASK (0x10U) 582 #define SRX_FMSG_RDY_IE_FRDY_IE4_SHIFT (4U) 583 #define SRX_FMSG_RDY_IE_FRDY_IE4_WIDTH (1U) 584 #define SRX_FMSG_RDY_IE_FRDY_IE4(x) (((uint32_t)(((uint32_t)(x)) << SRX_FMSG_RDY_IE_FRDY_IE4_SHIFT)) & SRX_FMSG_RDY_IE_FRDY_IE4_MASK) 585 586 #define SRX_FMSG_RDY_IE_FRDY_IE5_MASK (0x20U) 587 #define SRX_FMSG_RDY_IE_FRDY_IE5_SHIFT (5U) 588 #define SRX_FMSG_RDY_IE_FRDY_IE5_WIDTH (1U) 589 #define SRX_FMSG_RDY_IE_FRDY_IE5(x) (((uint32_t)(((uint32_t)(x)) << SRX_FMSG_RDY_IE_FRDY_IE5_SHIFT)) & SRX_FMSG_RDY_IE_FRDY_IE5_MASK) 590 591 #define SRX_FMSG_RDY_IE_FRDY_IE6_MASK (0x40U) 592 #define SRX_FMSG_RDY_IE_FRDY_IE6_SHIFT (6U) 593 #define SRX_FMSG_RDY_IE_FRDY_IE6_WIDTH (1U) 594 #define SRX_FMSG_RDY_IE_FRDY_IE6(x) (((uint32_t)(((uint32_t)(x)) << SRX_FMSG_RDY_IE_FRDY_IE6_SHIFT)) & SRX_FMSG_RDY_IE_FRDY_IE6_MASK) 595 596 #define SRX_FMSG_RDY_IE_FRDY_IE7_MASK (0x80U) 597 #define SRX_FMSG_RDY_IE_FRDY_IE7_SHIFT (7U) 598 #define SRX_FMSG_RDY_IE_FRDY_IE7_WIDTH (1U) 599 #define SRX_FMSG_RDY_IE_FRDY_IE7(x) (((uint32_t)(((uint32_t)(x)) << SRX_FMSG_RDY_IE_FRDY_IE7_SHIFT)) & SRX_FMSG_RDY_IE_FRDY_IE7_MASK) 600 /*! @} */ 601 602 /*! @name SMSG_RDY_IE - Slow Serial Message Ready Interrupt Enable Register */ 603 /*! @{ */ 604 605 #define SRX_SMSG_RDY_IE_SRDY_IE0_MASK (0x1U) 606 #define SRX_SMSG_RDY_IE_SRDY_IE0_SHIFT (0U) 607 #define SRX_SMSG_RDY_IE_SRDY_IE0_WIDTH (1U) 608 #define SRX_SMSG_RDY_IE_SRDY_IE0(x) (((uint32_t)(((uint32_t)(x)) << SRX_SMSG_RDY_IE_SRDY_IE0_SHIFT)) & SRX_SMSG_RDY_IE_SRDY_IE0_MASK) 609 610 #define SRX_SMSG_RDY_IE_SRDY_IE1_MASK (0x2U) 611 #define SRX_SMSG_RDY_IE_SRDY_IE1_SHIFT (1U) 612 #define SRX_SMSG_RDY_IE_SRDY_IE1_WIDTH (1U) 613 #define SRX_SMSG_RDY_IE_SRDY_IE1(x) (((uint32_t)(((uint32_t)(x)) << SRX_SMSG_RDY_IE_SRDY_IE1_SHIFT)) & SRX_SMSG_RDY_IE_SRDY_IE1_MASK) 614 615 #define SRX_SMSG_RDY_IE_SRDY_IE2_MASK (0x4U) 616 #define SRX_SMSG_RDY_IE_SRDY_IE2_SHIFT (2U) 617 #define SRX_SMSG_RDY_IE_SRDY_IE2_WIDTH (1U) 618 #define SRX_SMSG_RDY_IE_SRDY_IE2(x) (((uint32_t)(((uint32_t)(x)) << SRX_SMSG_RDY_IE_SRDY_IE2_SHIFT)) & SRX_SMSG_RDY_IE_SRDY_IE2_MASK) 619 620 #define SRX_SMSG_RDY_IE_SRDY_IE3_MASK (0x8U) 621 #define SRX_SMSG_RDY_IE_SRDY_IE3_SHIFT (3U) 622 #define SRX_SMSG_RDY_IE_SRDY_IE3_WIDTH (1U) 623 #define SRX_SMSG_RDY_IE_SRDY_IE3(x) (((uint32_t)(((uint32_t)(x)) << SRX_SMSG_RDY_IE_SRDY_IE3_SHIFT)) & SRX_SMSG_RDY_IE_SRDY_IE3_MASK) 624 625 #define SRX_SMSG_RDY_IE_SRDY_IE4_MASK (0x10U) 626 #define SRX_SMSG_RDY_IE_SRDY_IE4_SHIFT (4U) 627 #define SRX_SMSG_RDY_IE_SRDY_IE4_WIDTH (1U) 628 #define SRX_SMSG_RDY_IE_SRDY_IE4(x) (((uint32_t)(((uint32_t)(x)) << SRX_SMSG_RDY_IE_SRDY_IE4_SHIFT)) & SRX_SMSG_RDY_IE_SRDY_IE4_MASK) 629 630 #define SRX_SMSG_RDY_IE_SRDY_IE5_MASK (0x20U) 631 #define SRX_SMSG_RDY_IE_SRDY_IE5_SHIFT (5U) 632 #define SRX_SMSG_RDY_IE_SRDY_IE5_WIDTH (1U) 633 #define SRX_SMSG_RDY_IE_SRDY_IE5(x) (((uint32_t)(((uint32_t)(x)) << SRX_SMSG_RDY_IE_SRDY_IE5_SHIFT)) & SRX_SMSG_RDY_IE_SRDY_IE5_MASK) 634 635 #define SRX_SMSG_RDY_IE_SRDY_IE6_MASK (0x40U) 636 #define SRX_SMSG_RDY_IE_SRDY_IE6_SHIFT (6U) 637 #define SRX_SMSG_RDY_IE_SRDY_IE6_WIDTH (1U) 638 #define SRX_SMSG_RDY_IE_SRDY_IE6(x) (((uint32_t)(((uint32_t)(x)) << SRX_SMSG_RDY_IE_SRDY_IE6_SHIFT)) & SRX_SMSG_RDY_IE_SRDY_IE6_MASK) 639 640 #define SRX_SMSG_RDY_IE_SRDY_IE7_MASK (0x80U) 641 #define SRX_SMSG_RDY_IE_SRDY_IE7_SHIFT (7U) 642 #define SRX_SMSG_RDY_IE_SRDY_IE7_WIDTH (1U) 643 #define SRX_SMSG_RDY_IE_SRDY_IE7(x) (((uint32_t)(((uint32_t)(x)) << SRX_SMSG_RDY_IE_SRDY_IE7_SHIFT)) & SRX_SMSG_RDY_IE_SRDY_IE7_MASK) 644 /*! @} */ 645 646 /*! @name CH_CLK_CTRL - Channel '0' Clock Control Register..Channel '7' Clock Control Register */ 647 /*! @{ */ 648 649 #define SRX_CH_CLK_CTRL_PRSC_MASK (0x3FFFU) 650 #define SRX_CH_CLK_CTRL_PRSC_SHIFT (0U) 651 #define SRX_CH_CLK_CTRL_PRSC_WIDTH (14U) 652 #define SRX_CH_CLK_CTRL_PRSC(x) (((uint32_t)(((uint32_t)(x)) << SRX_CH_CLK_CTRL_PRSC_SHIFT)) & SRX_CH_CLK_CTRL_PRSC_MASK) 653 654 #define SRX_CH_CLK_CTRL_COMP_EN_MASK (0x8000U) 655 #define SRX_CH_CLK_CTRL_COMP_EN_SHIFT (15U) 656 #define SRX_CH_CLK_CTRL_COMP_EN_WIDTH (1U) 657 #define SRX_CH_CLK_CTRL_COMP_EN(x) (((uint32_t)(((uint32_t)(x)) << SRX_CH_CLK_CTRL_COMP_EN_SHIFT)) & SRX_CH_CLK_CTRL_COMP_EN_MASK) 658 659 #define SRX_CH_CLK_CTRL_CM_PRSC_MASK (0x7FFF0000U) 660 #define SRX_CH_CLK_CTRL_CM_PRSC_SHIFT (16U) 661 #define SRX_CH_CLK_CTRL_CM_PRSC_WIDTH (15U) 662 #define SRX_CH_CLK_CTRL_CM_PRSC(x) (((uint32_t)(((uint32_t)(x)) << SRX_CH_CLK_CTRL_CM_PRSC_SHIFT)) & SRX_CH_CLK_CTRL_CM_PRSC_MASK) 663 /*! @} */ 664 665 /*! @name CH_STATUS - Channel '0' Status Register..Channel '7' Status Register */ 666 /*! @{ */ 667 668 #define SRX_CH_STATUS_NUM_EDGES_ERR_MASK (0x10000U) 669 #define SRX_CH_STATUS_NUM_EDGES_ERR_SHIFT (16U) 670 #define SRX_CH_STATUS_NUM_EDGES_ERR_WIDTH (1U) 671 #define SRX_CH_STATUS_NUM_EDGES_ERR(x) (((uint32_t)(((uint32_t)(x)) << SRX_CH_STATUS_NUM_EDGES_ERR_SHIFT)) & SRX_CH_STATUS_NUM_EDGES_ERR_MASK) 672 673 #define SRX_CH_STATUS_FMSG_CRC_ERR_MASK (0x20000U) 674 #define SRX_CH_STATUS_FMSG_CRC_ERR_SHIFT (17U) 675 #define SRX_CH_STATUS_FMSG_CRC_ERR_WIDTH (1U) 676 #define SRX_CH_STATUS_FMSG_CRC_ERR(x) (((uint32_t)(((uint32_t)(x)) << SRX_CH_STATUS_FMSG_CRC_ERR_SHIFT)) & SRX_CH_STATUS_FMSG_CRC_ERR_MASK) 677 678 #define SRX_CH_STATUS_SMSG_CRC_ERR_MASK (0x40000U) 679 #define SRX_CH_STATUS_SMSG_CRC_ERR_SHIFT (18U) 680 #define SRX_CH_STATUS_SMSG_CRC_ERR_WIDTH (1U) 681 #define SRX_CH_STATUS_SMSG_CRC_ERR(x) (((uint32_t)(((uint32_t)(x)) << SRX_CH_STATUS_SMSG_CRC_ERR_SHIFT)) & SRX_CH_STATUS_SMSG_CRC_ERR_MASK) 682 683 #define SRX_CH_STATUS_NIB_VAL_ERR_HIGH_MASK (0x80000U) 684 #define SRX_CH_STATUS_NIB_VAL_ERR_HIGH_SHIFT (19U) 685 #define SRX_CH_STATUS_NIB_VAL_ERR_HIGH_WIDTH (1U) 686 #define SRX_CH_STATUS_NIB_VAL_ERR_HIGH(x) (((uint32_t)(((uint32_t)(x)) << SRX_CH_STATUS_NIB_VAL_ERR_HIGH_SHIFT)) & SRX_CH_STATUS_NIB_VAL_ERR_HIGH_MASK) 687 688 #define SRX_CH_STATUS_CAL_DIAG_ERR_MASK (0x100000U) 689 #define SRX_CH_STATUS_CAL_DIAG_ERR_SHIFT (20U) 690 #define SRX_CH_STATUS_CAL_DIAG_ERR_WIDTH (1U) 691 #define SRX_CH_STATUS_CAL_DIAG_ERR(x) (((uint32_t)(((uint32_t)(x)) << SRX_CH_STATUS_CAL_DIAG_ERR_SHIFT)) & SRX_CH_STATUS_CAL_DIAG_ERR_MASK) 692 693 #define SRX_CH_STATUS_CAL_LEN_ERR_MASK (0x200000U) 694 #define SRX_CH_STATUS_CAL_LEN_ERR_SHIFT (21U) 695 #define SRX_CH_STATUS_CAL_LEN_ERR_WIDTH (1U) 696 #define SRX_CH_STATUS_CAL_LEN_ERR(x) (((uint32_t)(((uint32_t)(x)) << SRX_CH_STATUS_CAL_LEN_ERR_SHIFT)) & SRX_CH_STATUS_CAL_LEN_ERR_MASK) 697 698 #define SRX_CH_STATUS_PP_DIAG_ERR_MASK (0x400000U) 699 #define SRX_CH_STATUS_PP_DIAG_ERR_SHIFT (22U) 700 #define SRX_CH_STATUS_PP_DIAG_ERR_WIDTH (1U) 701 #define SRX_CH_STATUS_PP_DIAG_ERR(x) (((uint32_t)(((uint32_t)(x)) << SRX_CH_STATUS_PP_DIAG_ERR_SHIFT)) & SRX_CH_STATUS_PP_DIAG_ERR_MASK) 702 703 #define SRX_CH_STATUS_NIB_VAL_ERR_LOW_MASK (0x800000U) 704 #define SRX_CH_STATUS_NIB_VAL_ERR_LOW_SHIFT (23U) 705 #define SRX_CH_STATUS_NIB_VAL_ERR_LOW_WIDTH (1U) 706 #define SRX_CH_STATUS_NIB_VAL_ERR_LOW(x) (((uint32_t)(((uint32_t)(x)) << SRX_CH_STATUS_NIB_VAL_ERR_LOW_SHIFT)) & SRX_CH_STATUS_NIB_VAL_ERR_LOW_MASK) 707 708 #define SRX_CH_STATUS_FMSG_OFLW_MASK (0x1000000U) 709 #define SRX_CH_STATUS_FMSG_OFLW_SHIFT (24U) 710 #define SRX_CH_STATUS_FMSG_OFLW_WIDTH (1U) 711 #define SRX_CH_STATUS_FMSG_OFLW(x) (((uint32_t)(((uint32_t)(x)) << SRX_CH_STATUS_FMSG_OFLW_SHIFT)) & SRX_CH_STATUS_FMSG_OFLW_MASK) 712 713 #define SRX_CH_STATUS_SMSG_OFLW_MASK (0x2000000U) 714 #define SRX_CH_STATUS_SMSG_OFLW_SHIFT (25U) 715 #define SRX_CH_STATUS_SMSG_OFLW_WIDTH (1U) 716 #define SRX_CH_STATUS_SMSG_OFLW(x) (((uint32_t)(((uint32_t)(x)) << SRX_CH_STATUS_SMSG_OFLW_SHIFT)) & SRX_CH_STATUS_SMSG_OFLW_MASK) 717 718 #define SRX_CH_STATUS_CAL_20_25_MASK (0x4000000U) 719 #define SRX_CH_STATUS_CAL_20_25_SHIFT (26U) 720 #define SRX_CH_STATUS_CAL_20_25_WIDTH (1U) 721 #define SRX_CH_STATUS_CAL_20_25(x) (((uint32_t)(((uint32_t)(x)) << SRX_CH_STATUS_CAL_20_25_SHIFT)) & SRX_CH_STATUS_CAL_20_25_MASK) 722 723 #define SRX_CH_STATUS_CAL_RESYNC_MASK (0x8000000U) 724 #define SRX_CH_STATUS_CAL_RESYNC_SHIFT (27U) 725 #define SRX_CH_STATUS_CAL_RESYNC_WIDTH (1U) 726 #define SRX_CH_STATUS_CAL_RESYNC(x) (((uint32_t)(((uint32_t)(x)) << SRX_CH_STATUS_CAL_RESYNC_SHIFT)) & SRX_CH_STATUS_CAL_RESYNC_MASK) 727 728 #define SRX_CH_STATUS_BUS_IDLE_MASK (0x80000000U) 729 #define SRX_CH_STATUS_BUS_IDLE_SHIFT (31U) 730 #define SRX_CH_STATUS_BUS_IDLE_WIDTH (1U) 731 #define SRX_CH_STATUS_BUS_IDLE(x) (((uint32_t)(((uint32_t)(x)) << SRX_CH_STATUS_BUS_IDLE_SHIFT)) & SRX_CH_STATUS_BUS_IDLE_MASK) 732 /*! @} */ 733 734 /*! @name CH_CONFIG - Channel '0' Configuration Register..Channel '7' Configuration Register */ 735 /*! @{ */ 736 737 #define SRX_CH_CONFIG_FIL_CNT_MASK (0xFFU) 738 #define SRX_CH_CONFIG_FIL_CNT_SHIFT (0U) 739 #define SRX_CH_CONFIG_FIL_CNT_WIDTH (8U) 740 #define SRX_CH_CONFIG_FIL_CNT(x) (((uint32_t)(((uint32_t)(x)) << SRX_CH_CONFIG_FIL_CNT_SHIFT)) & SRX_CH_CONFIG_FIL_CNT_MASK) 741 742 #define SRX_CH_CONFIG_SUCC_CAL_CHK_MASK (0x100U) 743 #define SRX_CH_CONFIG_SUCC_CAL_CHK_SHIFT (8U) 744 #define SRX_CH_CONFIG_SUCC_CAL_CHK_WIDTH (1U) 745 #define SRX_CH_CONFIG_SUCC_CAL_CHK(x) (((uint32_t)(((uint32_t)(x)) << SRX_CH_CONFIG_SUCC_CAL_CHK_SHIFT)) & SRX_CH_CONFIG_SUCC_CAL_CHK_MASK) 746 747 #define SRX_CH_CONFIG_PAUSE_EN_MASK (0x200U) 748 #define SRX_CH_CONFIG_PAUSE_EN_SHIFT (9U) 749 #define SRX_CH_CONFIG_PAUSE_EN_WIDTH (1U) 750 #define SRX_CH_CONFIG_PAUSE_EN(x) (((uint32_t)(((uint32_t)(x)) << SRX_CH_CONFIG_PAUSE_EN_SHIFT)) & SRX_CH_CONFIG_PAUSE_EN_MASK) 751 752 #define SRX_CH_CONFIG_SCRC_TYPE_MASK (0x400U) 753 #define SRX_CH_CONFIG_SCRC_TYPE_SHIFT (10U) 754 #define SRX_CH_CONFIG_SCRC_TYPE_WIDTH (1U) 755 #define SRX_CH_CONFIG_SCRC_TYPE(x) (((uint32_t)(((uint32_t)(x)) << SRX_CH_CONFIG_SCRC_TYPE_SHIFT)) & SRX_CH_CONFIG_SCRC_TYPE_MASK) 756 757 #define SRX_CH_CONFIG_FCRC_SC_EN_MASK (0x800U) 758 #define SRX_CH_CONFIG_FCRC_SC_EN_SHIFT (11U) 759 #define SRX_CH_CONFIG_FCRC_SC_EN_WIDTH (1U) 760 #define SRX_CH_CONFIG_FCRC_SC_EN(x) (((uint32_t)(((uint32_t)(x)) << SRX_CH_CONFIG_FCRC_SC_EN_SHIFT)) & SRX_CH_CONFIG_FCRC_SC_EN_MASK) 761 762 #define SRX_CH_CONFIG_FCRC_TYPE_MASK (0x1000U) 763 #define SRX_CH_CONFIG_FCRC_TYPE_SHIFT (12U) 764 #define SRX_CH_CONFIG_FCRC_TYPE_WIDTH (1U) 765 #define SRX_CH_CONFIG_FCRC_TYPE(x) (((uint32_t)(((uint32_t)(x)) << SRX_CH_CONFIG_FCRC_TYPE_SHIFT)) & SRX_CH_CONFIG_FCRC_TYPE_MASK) 766 767 #define SRX_CH_CONFIG_PP_CHKSEL_MASK (0x2000U) 768 #define SRX_CH_CONFIG_PP_CHKSEL_SHIFT (13U) 769 #define SRX_CH_CONFIG_PP_CHKSEL_WIDTH (1U) 770 #define SRX_CH_CONFIG_PP_CHKSEL(x) (((uint32_t)(((uint32_t)(x)) << SRX_CH_CONFIG_PP_CHKSEL_SHIFT)) & SRX_CH_CONFIG_PP_CHKSEL_MASK) 771 772 #define SRX_CH_CONFIG_CAL_RNG_MASK (0x4000U) 773 #define SRX_CH_CONFIG_CAL_RNG_SHIFT (14U) 774 #define SRX_CH_CONFIG_CAL_RNG_WIDTH (1U) 775 #define SRX_CH_CONFIG_CAL_RNG(x) (((uint32_t)(((uint32_t)(x)) << SRX_CH_CONFIG_CAL_RNG_SHIFT)) & SRX_CH_CONFIG_CAL_RNG_MASK) 776 777 #define SRX_CH_CONFIG_DCHNG_INT_MASK (0x8000U) 778 #define SRX_CH_CONFIG_DCHNG_INT_SHIFT (15U) 779 #define SRX_CH_CONFIG_DCHNG_INT_WIDTH (1U) 780 #define SRX_CH_CONFIG_DCHNG_INT(x) (((uint32_t)(((uint32_t)(x)) << SRX_CH_CONFIG_DCHNG_INT_SHIFT)) & SRX_CH_CONFIG_DCHNG_INT_MASK) 781 782 #define SRX_CH_CONFIG_IE_NUM_EDGES_ERR_MASK (0x10000U) 783 #define SRX_CH_CONFIG_IE_NUM_EDGES_ERR_SHIFT (16U) 784 #define SRX_CH_CONFIG_IE_NUM_EDGES_ERR_WIDTH (1U) 785 #define SRX_CH_CONFIG_IE_NUM_EDGES_ERR(x) (((uint32_t)(((uint32_t)(x)) << SRX_CH_CONFIG_IE_NUM_EDGES_ERR_SHIFT)) & SRX_CH_CONFIG_IE_NUM_EDGES_ERR_MASK) 786 787 #define SRX_CH_CONFIG_IE_FMSG_CRC_ERR_MASK (0x20000U) 788 #define SRX_CH_CONFIG_IE_FMSG_CRC_ERR_SHIFT (17U) 789 #define SRX_CH_CONFIG_IE_FMSG_CRC_ERR_WIDTH (1U) 790 #define SRX_CH_CONFIG_IE_FMSG_CRC_ERR(x) (((uint32_t)(((uint32_t)(x)) << SRX_CH_CONFIG_IE_FMSG_CRC_ERR_SHIFT)) & SRX_CH_CONFIG_IE_FMSG_CRC_ERR_MASK) 791 792 #define SRX_CH_CONFIG_IE_SMSG_CRC_ERR_MASK (0x40000U) 793 #define SRX_CH_CONFIG_IE_SMSG_CRC_ERR_SHIFT (18U) 794 #define SRX_CH_CONFIG_IE_SMSG_CRC_ERR_WIDTH (1U) 795 #define SRX_CH_CONFIG_IE_SMSG_CRC_ERR(x) (((uint32_t)(((uint32_t)(x)) << SRX_CH_CONFIG_IE_SMSG_CRC_ERR_SHIFT)) & SRX_CH_CONFIG_IE_SMSG_CRC_ERR_MASK) 796 797 #define SRX_CH_CONFIG_IE_NIB_VAL_ERR_MASK (0x80000U) 798 #define SRX_CH_CONFIG_IE_NIB_VAL_ERR_SHIFT (19U) 799 #define SRX_CH_CONFIG_IE_NIB_VAL_ERR_WIDTH (1U) 800 #define SRX_CH_CONFIG_IE_NIB_VAL_ERR(x) (((uint32_t)(((uint32_t)(x)) << SRX_CH_CONFIG_IE_NIB_VAL_ERR_SHIFT)) & SRX_CH_CONFIG_IE_NIB_VAL_ERR_MASK) 801 802 #define SRX_CH_CONFIG_IE_CAL_DIAG_ERR_MASK (0x100000U) 803 #define SRX_CH_CONFIG_IE_CAL_DIAG_ERR_SHIFT (20U) 804 #define SRX_CH_CONFIG_IE_CAL_DIAG_ERR_WIDTH (1U) 805 #define SRX_CH_CONFIG_IE_CAL_DIAG_ERR(x) (((uint32_t)(((uint32_t)(x)) << SRX_CH_CONFIG_IE_CAL_DIAG_ERR_SHIFT)) & SRX_CH_CONFIG_IE_CAL_DIAG_ERR_MASK) 806 807 #define SRX_CH_CONFIG_IE_CAL_LEN_ERR_MASK (0x200000U) 808 #define SRX_CH_CONFIG_IE_CAL_LEN_ERR_SHIFT (21U) 809 #define SRX_CH_CONFIG_IE_CAL_LEN_ERR_WIDTH (1U) 810 #define SRX_CH_CONFIG_IE_CAL_LEN_ERR(x) (((uint32_t)(((uint32_t)(x)) << SRX_CH_CONFIG_IE_CAL_LEN_ERR_SHIFT)) & SRX_CH_CONFIG_IE_CAL_LEN_ERR_MASK) 811 812 #define SRX_CH_CONFIG_IE_PP_DIAG_ERR_MASK (0x400000U) 813 #define SRX_CH_CONFIG_IE_PP_DIAG_ERR_SHIFT (22U) 814 #define SRX_CH_CONFIG_IE_PP_DIAG_ERR_WIDTH (1U) 815 #define SRX_CH_CONFIG_IE_PP_DIAG_ERR(x) (((uint32_t)(((uint32_t)(x)) << SRX_CH_CONFIG_IE_PP_DIAG_ERR_SHIFT)) & SRX_CH_CONFIG_IE_PP_DIAG_ERR_MASK) 816 817 #define SRX_CH_CONFIG_FCRC_CHK_OFF_MASK (0x800000U) 818 #define SRX_CH_CONFIG_FCRC_CHK_OFF_SHIFT (23U) 819 #define SRX_CH_CONFIG_FCRC_CHK_OFF_WIDTH (1U) 820 #define SRX_CH_CONFIG_FCRC_CHK_OFF(x) (((uint32_t)(((uint32_t)(x)) << SRX_CH_CONFIG_FCRC_CHK_OFF_SHIFT)) & SRX_CH_CONFIG_FCRC_CHK_OFF_MASK) 821 822 #define SRX_CH_CONFIG_IE_FMSG_OFLW_MASK (0x1000000U) 823 #define SRX_CH_CONFIG_IE_FMSG_OFLW_SHIFT (24U) 824 #define SRX_CH_CONFIG_IE_FMSG_OFLW_WIDTH (1U) 825 #define SRX_CH_CONFIG_IE_FMSG_OFLW(x) (((uint32_t)(((uint32_t)(x)) << SRX_CH_CONFIG_IE_FMSG_OFLW_SHIFT)) & SRX_CH_CONFIG_IE_FMSG_OFLW_MASK) 826 827 #define SRX_CH_CONFIG_IE_SMSG_OFLW_MASK (0x2000000U) 828 #define SRX_CH_CONFIG_IE_SMSG_OFLW_SHIFT (25U) 829 #define SRX_CH_CONFIG_IE_SMSG_OFLW_WIDTH (1U) 830 #define SRX_CH_CONFIG_IE_SMSG_OFLW(x) (((uint32_t)(((uint32_t)(x)) << SRX_CH_CONFIG_IE_SMSG_OFLW_SHIFT)) & SRX_CH_CONFIG_IE_SMSG_OFLW_MASK) 831 832 #define SRX_CH_CONFIG_IE_CAL_20_25_MASK (0x4000000U) 833 #define SRX_CH_CONFIG_IE_CAL_20_25_SHIFT (26U) 834 #define SRX_CH_CONFIG_IE_CAL_20_25_WIDTH (1U) 835 #define SRX_CH_CONFIG_IE_CAL_20_25(x) (((uint32_t)(((uint32_t)(x)) << SRX_CH_CONFIG_IE_CAL_20_25_SHIFT)) & SRX_CH_CONFIG_IE_CAL_20_25_MASK) 836 837 #define SRX_CH_CONFIG_IE_CAL_RESYNC_MASK (0x8000000U) 838 #define SRX_CH_CONFIG_IE_CAL_RESYNC_SHIFT (27U) 839 #define SRX_CH_CONFIG_IE_CAL_RESYNC_WIDTH (1U) 840 #define SRX_CH_CONFIG_IE_CAL_RESYNC(x) (((uint32_t)(((uint32_t)(x)) << SRX_CH_CONFIG_IE_CAL_RESYNC_SHIFT)) & SRX_CH_CONFIG_IE_CAL_RESYNC_MASK) 841 842 #define SRX_CH_CONFIG_BUS_IDLE_CNT_MASK (0xF0000000U) 843 #define SRX_CH_CONFIG_BUS_IDLE_CNT_SHIFT (28U) 844 #define SRX_CH_CONFIG_BUS_IDLE_CNT_WIDTH (4U) 845 #define SRX_CH_CONFIG_BUS_IDLE_CNT(x) (((uint32_t)(((uint32_t)(x)) << SRX_CH_CONFIG_BUS_IDLE_CNT_SHIFT)) & SRX_CH_CONFIG_BUS_IDLE_CNT_MASK) 846 /*! @} */ 847 848 /*! @name CH_FMSG_DATA - Channel '0' Fast Message Data Read Register..Channel '7' Fast Message Data Read Register */ 849 /*! @{ */ 850 851 #define SRX_CH_FMSG_DATA_DNIB8_MASK (0xFU) 852 #define SRX_CH_FMSG_DATA_DNIB8_SHIFT (0U) 853 #define SRX_CH_FMSG_DATA_DNIB8_WIDTH (4U) 854 #define SRX_CH_FMSG_DATA_DNIB8(x) (((uint32_t)(((uint32_t)(x)) << SRX_CH_FMSG_DATA_DNIB8_SHIFT)) & SRX_CH_FMSG_DATA_DNIB8_MASK) 855 856 #define SRX_CH_FMSG_DATA_DNIB7_MASK (0xF0U) 857 #define SRX_CH_FMSG_DATA_DNIB7_SHIFT (4U) 858 #define SRX_CH_FMSG_DATA_DNIB7_WIDTH (4U) 859 #define SRX_CH_FMSG_DATA_DNIB7(x) (((uint32_t)(((uint32_t)(x)) << SRX_CH_FMSG_DATA_DNIB7_SHIFT)) & SRX_CH_FMSG_DATA_DNIB7_MASK) 860 861 #define SRX_CH_FMSG_DATA_DNIB6_MASK (0xF00U) 862 #define SRX_CH_FMSG_DATA_DNIB6_SHIFT (8U) 863 #define SRX_CH_FMSG_DATA_DNIB6_WIDTH (4U) 864 #define SRX_CH_FMSG_DATA_DNIB6(x) (((uint32_t)(((uint32_t)(x)) << SRX_CH_FMSG_DATA_DNIB6_SHIFT)) & SRX_CH_FMSG_DATA_DNIB6_MASK) 865 866 #define SRX_CH_FMSG_DATA_DNIB5_MASK (0xF000U) 867 #define SRX_CH_FMSG_DATA_DNIB5_SHIFT (12U) 868 #define SRX_CH_FMSG_DATA_DNIB5_WIDTH (4U) 869 #define SRX_CH_FMSG_DATA_DNIB5(x) (((uint32_t)(((uint32_t)(x)) << SRX_CH_FMSG_DATA_DNIB5_SHIFT)) & SRX_CH_FMSG_DATA_DNIB5_MASK) 870 871 #define SRX_CH_FMSG_DATA_DNIB4_MASK (0xF0000U) 872 #define SRX_CH_FMSG_DATA_DNIB4_SHIFT (16U) 873 #define SRX_CH_FMSG_DATA_DNIB4_WIDTH (4U) 874 #define SRX_CH_FMSG_DATA_DNIB4(x) (((uint32_t)(((uint32_t)(x)) << SRX_CH_FMSG_DATA_DNIB4_SHIFT)) & SRX_CH_FMSG_DATA_DNIB4_MASK) 875 876 #define SRX_CH_FMSG_DATA_DNIB3_MASK (0xF00000U) 877 #define SRX_CH_FMSG_DATA_DNIB3_SHIFT (20U) 878 #define SRX_CH_FMSG_DATA_DNIB3_WIDTH (4U) 879 #define SRX_CH_FMSG_DATA_DNIB3(x) (((uint32_t)(((uint32_t)(x)) << SRX_CH_FMSG_DATA_DNIB3_SHIFT)) & SRX_CH_FMSG_DATA_DNIB3_MASK) 880 881 #define SRX_CH_FMSG_DATA_DNIB2_MASK (0xF000000U) 882 #define SRX_CH_FMSG_DATA_DNIB2_SHIFT (24U) 883 #define SRX_CH_FMSG_DATA_DNIB2_WIDTH (4U) 884 #define SRX_CH_FMSG_DATA_DNIB2(x) (((uint32_t)(((uint32_t)(x)) << SRX_CH_FMSG_DATA_DNIB2_SHIFT)) & SRX_CH_FMSG_DATA_DNIB2_MASK) 885 886 #define SRX_CH_FMSG_DATA_DNIB1_MASK (0xF0000000U) 887 #define SRX_CH_FMSG_DATA_DNIB1_SHIFT (28U) 888 #define SRX_CH_FMSG_DATA_DNIB1_WIDTH (4U) 889 #define SRX_CH_FMSG_DATA_DNIB1(x) (((uint32_t)(((uint32_t)(x)) << SRX_CH_FMSG_DATA_DNIB1_SHIFT)) & SRX_CH_FMSG_DATA_DNIB1_MASK) 890 /*! @} */ 891 892 /*! @name CH_FMSG_CRC - Channel '0' Fast Message CRC Read Register..Channel '7' Fast Message CRC Read Register */ 893 /*! @{ */ 894 895 #define SRX_CH_FMSG_CRC_SCNIB_MASK (0xFU) 896 #define SRX_CH_FMSG_CRC_SCNIB_SHIFT (0U) 897 #define SRX_CH_FMSG_CRC_SCNIB_WIDTH (4U) 898 #define SRX_CH_FMSG_CRC_SCNIB(x) (((uint32_t)(((uint32_t)(x)) << SRX_CH_FMSG_CRC_SCNIB_SHIFT)) & SRX_CH_FMSG_CRC_SCNIB_MASK) 899 900 #define SRX_CH_FMSG_CRC_CHNUM_MASK (0xF0U) 901 #define SRX_CH_FMSG_CRC_CHNUM_SHIFT (4U) 902 #define SRX_CH_FMSG_CRC_CHNUM_WIDTH (4U) 903 #define SRX_CH_FMSG_CRC_CHNUM(x) (((uint32_t)(((uint32_t)(x)) << SRX_CH_FMSG_CRC_CHNUM_SHIFT)) & SRX_CH_FMSG_CRC_CHNUM_MASK) 904 905 #define SRX_CH_FMSG_CRC_CRC4b_MASK (0xF0000U) 906 #define SRX_CH_FMSG_CRC_CRC4b_SHIFT (16U) 907 #define SRX_CH_FMSG_CRC_CRC4b_WIDTH (4U) 908 #define SRX_CH_FMSG_CRC_CRC4b(x) (((uint32_t)(((uint32_t)(x)) << SRX_CH_FMSG_CRC_CRC4b_SHIFT)) & SRX_CH_FMSG_CRC_CRC4b_MASK) 909 /*! @} */ 910 911 /*! @name CH_FMSG_TS - Channel '0' Fast Message Time Stamp Read Register..Channel '7' Fast Message Time Stamp Read Register */ 912 /*! @{ */ 913 914 #define SRX_CH_FMSG_TS_TS_MASK (0xFFFFFFFFU) 915 #define SRX_CH_FMSG_TS_TS_SHIFT (0U) 916 #define SRX_CH_FMSG_TS_TS_WIDTH (32U) 917 #define SRX_CH_FMSG_TS_TS(x) (((uint32_t)(((uint32_t)(x)) << SRX_CH_FMSG_TS_TS_SHIFT)) & SRX_CH_FMSG_TS_TS_MASK) 918 /*! @} */ 919 920 /*! @name CH_SMSG_BIT3 - Channel '0' Serial Message Read Register (Bit 3)..Channel '7' Serial Message Read Register (Bit 3) */ 921 /*! @{ */ 922 923 #define SRX_CH_SMSG_BIT3_ID3_0_DATA15_12_MASK (0x1EU) 924 #define SRX_CH_SMSG_BIT3_ID3_0_DATA15_12_SHIFT (1U) 925 #define SRX_CH_SMSG_BIT3_ID3_0_DATA15_12_WIDTH (4U) 926 #define SRX_CH_SMSG_BIT3_ID3_0_DATA15_12(x) (((uint32_t)(((uint32_t)(x)) << SRX_CH_SMSG_BIT3_ID3_0_DATA15_12_SHIFT)) & SRX_CH_SMSG_BIT3_ID3_0_DATA15_12_MASK) 927 928 #define SRX_CH_SMSG_BIT3_ID7_4_ID3_0_MASK (0x3C0U) 929 #define SRX_CH_SMSG_BIT3_ID7_4_ID3_0_SHIFT (6U) 930 #define SRX_CH_SMSG_BIT3_ID7_4_ID3_0_WIDTH (4U) 931 #define SRX_CH_SMSG_BIT3_ID7_4_ID3_0(x) (((uint32_t)(((uint32_t)(x)) << SRX_CH_SMSG_BIT3_ID7_4_ID3_0_SHIFT)) & SRX_CH_SMSG_BIT3_ID7_4_ID3_0_MASK) 932 933 #define SRX_CH_SMSG_BIT3_CFG_MASK (0x400U) 934 #define SRX_CH_SMSG_BIT3_CFG_SHIFT (10U) 935 #define SRX_CH_SMSG_BIT3_CFG_WIDTH (1U) 936 #define SRX_CH_SMSG_BIT3_CFG(x) (((uint32_t)(((uint32_t)(x)) << SRX_CH_SMSG_BIT3_CFG_SHIFT)) & SRX_CH_SMSG_BIT3_CFG_MASK) 937 938 #define SRX_CH_SMSG_BIT3_TYPE_MASK (0x8000000U) 939 #define SRX_CH_SMSG_BIT3_TYPE_SHIFT (27U) 940 #define SRX_CH_SMSG_BIT3_TYPE_WIDTH (1U) 941 #define SRX_CH_SMSG_BIT3_TYPE(x) (((uint32_t)(((uint32_t)(x)) << SRX_CH_SMSG_BIT3_TYPE_SHIFT)) & SRX_CH_SMSG_BIT3_TYPE_MASK) 942 943 #define SRX_CH_SMSG_BIT3_CHNUM_MASK (0xF0000000U) 944 #define SRX_CH_SMSG_BIT3_CHNUM_SHIFT (28U) 945 #define SRX_CH_SMSG_BIT3_CHNUM_WIDTH (4U) 946 #define SRX_CH_SMSG_BIT3_CHNUM(x) (((uint32_t)(((uint32_t)(x)) << SRX_CH_SMSG_BIT3_CHNUM_SHIFT)) & SRX_CH_SMSG_BIT3_CHNUM_MASK) 947 /*! @} */ 948 949 /*! @name CH_SMSG_BIT2 - Channel '0' Serial Message Read Register (Bit 2)..Channel '7' Serial Message Read Register (Bit 2) */ 950 /*! @{ */ 951 952 #define SRX_CH_SMSG_BIT2_DATA_MASK (0xFFFU) 953 #define SRX_CH_SMSG_BIT2_DATA_SHIFT (0U) 954 #define SRX_CH_SMSG_BIT2_DATA_WIDTH (12U) 955 #define SRX_CH_SMSG_BIT2_DATA(x) (((uint32_t)(((uint32_t)(x)) << SRX_CH_SMSG_BIT2_DATA_SHIFT)) & SRX_CH_SMSG_BIT2_DATA_MASK) 956 957 #define SRX_CH_SMSG_BIT2_SMCRC_MASK (0x3F0000U) 958 #define SRX_CH_SMSG_BIT2_SMCRC_SHIFT (16U) 959 #define SRX_CH_SMSG_BIT2_SMCRC_WIDTH (6U) 960 #define SRX_CH_SMSG_BIT2_SMCRC(x) (((uint32_t)(((uint32_t)(x)) << SRX_CH_SMSG_BIT2_SMCRC_SHIFT)) & SRX_CH_SMSG_BIT2_SMCRC_MASK) 961 /*! @} */ 962 963 /*! @name CH_SMSG_TS - Channel '0' Serial Message Time Stamp Read..Channel '7' Serial Message Time Stamp Read */ 964 /*! @{ */ 965 966 #define SRX_CH_SMSG_TS_TS_MASK (0xFFFFFFFFU) 967 #define SRX_CH_SMSG_TS_TS_SHIFT (0U) 968 #define SRX_CH_SMSG_TS_TS_WIDTH (32U) 969 #define SRX_CH_SMSG_TS_TS(x) (((uint32_t)(((uint32_t)(x)) << SRX_CH_SMSG_TS_TS_SHIFT)) & SRX_CH_SMSG_TS_TS_MASK) 970 /*! @} */ 971 972 /*! @name CH_F_DMA_RD - Channel '0' DMA Fast Message Data Read..Channel '7' DMA Fast Message Data Read */ 973 /*! @{ */ 974 975 #define SRX_CH_F_DMA_RD_DNIB8_MASK (0xFU) 976 #define SRX_CH_F_DMA_RD_DNIB8_SHIFT (0U) 977 #define SRX_CH_F_DMA_RD_DNIB8_WIDTH (4U) 978 #define SRX_CH_F_DMA_RD_DNIB8(x) (((uint32_t)(((uint32_t)(x)) << SRX_CH_F_DMA_RD_DNIB8_SHIFT)) & SRX_CH_F_DMA_RD_DNIB8_MASK) 979 980 #define SRX_CH_F_DMA_RD_DNIB7_MASK (0xF0U) 981 #define SRX_CH_F_DMA_RD_DNIB7_SHIFT (4U) 982 #define SRX_CH_F_DMA_RD_DNIB7_WIDTH (4U) 983 #define SRX_CH_F_DMA_RD_DNIB7(x) (((uint32_t)(((uint32_t)(x)) << SRX_CH_F_DMA_RD_DNIB7_SHIFT)) & SRX_CH_F_DMA_RD_DNIB7_MASK) 984 985 #define SRX_CH_F_DMA_RD_DNIB6_MASK (0xF00U) 986 #define SRX_CH_F_DMA_RD_DNIB6_SHIFT (8U) 987 #define SRX_CH_F_DMA_RD_DNIB6_WIDTH (4U) 988 #define SRX_CH_F_DMA_RD_DNIB6(x) (((uint32_t)(((uint32_t)(x)) << SRX_CH_F_DMA_RD_DNIB6_SHIFT)) & SRX_CH_F_DMA_RD_DNIB6_MASK) 989 990 #define SRX_CH_F_DMA_RD_DNIB5_MASK (0xF000U) 991 #define SRX_CH_F_DMA_RD_DNIB5_SHIFT (12U) 992 #define SRX_CH_F_DMA_RD_DNIB5_WIDTH (4U) 993 #define SRX_CH_F_DMA_RD_DNIB5(x) (((uint32_t)(((uint32_t)(x)) << SRX_CH_F_DMA_RD_DNIB5_SHIFT)) & SRX_CH_F_DMA_RD_DNIB5_MASK) 994 995 #define SRX_CH_F_DMA_RD_DNIB4_MASK (0xF0000U) 996 #define SRX_CH_F_DMA_RD_DNIB4_SHIFT (16U) 997 #define SRX_CH_F_DMA_RD_DNIB4_WIDTH (4U) 998 #define SRX_CH_F_DMA_RD_DNIB4(x) (((uint32_t)(((uint32_t)(x)) << SRX_CH_F_DMA_RD_DNIB4_SHIFT)) & SRX_CH_F_DMA_RD_DNIB4_MASK) 999 1000 #define SRX_CH_F_DMA_RD_DNIB3_MASK (0xF00000U) 1001 #define SRX_CH_F_DMA_RD_DNIB3_SHIFT (20U) 1002 #define SRX_CH_F_DMA_RD_DNIB3_WIDTH (4U) 1003 #define SRX_CH_F_DMA_RD_DNIB3(x) (((uint32_t)(((uint32_t)(x)) << SRX_CH_F_DMA_RD_DNIB3_SHIFT)) & SRX_CH_F_DMA_RD_DNIB3_MASK) 1004 1005 #define SRX_CH_F_DMA_RD_DNIB2_MASK (0xF000000U) 1006 #define SRX_CH_F_DMA_RD_DNIB2_SHIFT (24U) 1007 #define SRX_CH_F_DMA_RD_DNIB2_WIDTH (4U) 1008 #define SRX_CH_F_DMA_RD_DNIB2(x) (((uint32_t)(((uint32_t)(x)) << SRX_CH_F_DMA_RD_DNIB2_SHIFT)) & SRX_CH_F_DMA_RD_DNIB2_MASK) 1009 1010 #define SRX_CH_F_DMA_RD_DNIB1_MASK (0xF0000000U) 1011 #define SRX_CH_F_DMA_RD_DNIB1_SHIFT (28U) 1012 #define SRX_CH_F_DMA_RD_DNIB1_WIDTH (4U) 1013 #define SRX_CH_F_DMA_RD_DNIB1(x) (((uint32_t)(((uint32_t)(x)) << SRX_CH_F_DMA_RD_DNIB1_SHIFT)) & SRX_CH_F_DMA_RD_DNIB1_MASK) 1014 /*! @} */ 1015 1016 /*! @name CH_F_DMA_CRC - Channel '0' DMA Fast Message CRC Read..Channel '7' DMA Fast Message CRC Read */ 1017 /*! @{ */ 1018 1019 #define SRX_CH_F_DMA_CRC_SCNIB_MASK (0xFU) 1020 #define SRX_CH_F_DMA_CRC_SCNIB_SHIFT (0U) 1021 #define SRX_CH_F_DMA_CRC_SCNIB_WIDTH (4U) 1022 #define SRX_CH_F_DMA_CRC_SCNIB(x) (((uint32_t)(((uint32_t)(x)) << SRX_CH_F_DMA_CRC_SCNIB_SHIFT)) & SRX_CH_F_DMA_CRC_SCNIB_MASK) 1023 1024 #define SRX_CH_F_DMA_CRC_CHNUM_MASK (0xF0U) 1025 #define SRX_CH_F_DMA_CRC_CHNUM_SHIFT (4U) 1026 #define SRX_CH_F_DMA_CRC_CHNUM_WIDTH (4U) 1027 #define SRX_CH_F_DMA_CRC_CHNUM(x) (((uint32_t)(((uint32_t)(x)) << SRX_CH_F_DMA_CRC_CHNUM_SHIFT)) & SRX_CH_F_DMA_CRC_CHNUM_MASK) 1028 1029 #define SRX_CH_F_DMA_CRC_CRC4b_MASK (0xF0000U) 1030 #define SRX_CH_F_DMA_CRC_CRC4b_SHIFT (16U) 1031 #define SRX_CH_F_DMA_CRC_CRC4b_WIDTH (4U) 1032 #define SRX_CH_F_DMA_CRC_CRC4b(x) (((uint32_t)(((uint32_t)(x)) << SRX_CH_F_DMA_CRC_CRC4b_SHIFT)) & SRX_CH_F_DMA_CRC_CRC4b_MASK) 1033 /*! @} */ 1034 1035 /*! @name CH_F_DMA_TS - Channel '0' DMA Fast Message Time Stamp Read..Channel '7' DMA Fast Message Time Stamp Read */ 1036 /*! @{ */ 1037 1038 #define SRX_CH_F_DMA_TS_TS_MASK (0xFFFFFFFFU) 1039 #define SRX_CH_F_DMA_TS_TS_SHIFT (0U) 1040 #define SRX_CH_F_DMA_TS_TS_WIDTH (32U) 1041 #define SRX_CH_F_DMA_TS_TS(x) (((uint32_t)(((uint32_t)(x)) << SRX_CH_F_DMA_TS_TS_SHIFT)) & SRX_CH_F_DMA_TS_TS_MASK) 1042 /*! @} */ 1043 1044 /*! @name CH_S_DMA_RD - Channel '0' DMA Slow Serial Message Bit3 Read..Channel '7' DMA Slow Serial Message Bit3 Read */ 1045 /*! @{ */ 1046 1047 #define SRX_CH_S_DMA_RD_ID3_0_DATA15_12_MASK (0x1EU) 1048 #define SRX_CH_S_DMA_RD_ID3_0_DATA15_12_SHIFT (1U) 1049 #define SRX_CH_S_DMA_RD_ID3_0_DATA15_12_WIDTH (4U) 1050 #define SRX_CH_S_DMA_RD_ID3_0_DATA15_12(x) (((uint32_t)(((uint32_t)(x)) << SRX_CH_S_DMA_RD_ID3_0_DATA15_12_SHIFT)) & SRX_CH_S_DMA_RD_ID3_0_DATA15_12_MASK) 1051 1052 #define SRX_CH_S_DMA_RD_ID7_4_ID3_0_MASK (0x3C0U) 1053 #define SRX_CH_S_DMA_RD_ID7_4_ID3_0_SHIFT (6U) 1054 #define SRX_CH_S_DMA_RD_ID7_4_ID3_0_WIDTH (4U) 1055 #define SRX_CH_S_DMA_RD_ID7_4_ID3_0(x) (((uint32_t)(((uint32_t)(x)) << SRX_CH_S_DMA_RD_ID7_4_ID3_0_SHIFT)) & SRX_CH_S_DMA_RD_ID7_4_ID3_0_MASK) 1056 1057 #define SRX_CH_S_DMA_RD_CFG_MASK (0x400U) 1058 #define SRX_CH_S_DMA_RD_CFG_SHIFT (10U) 1059 #define SRX_CH_S_DMA_RD_CFG_WIDTH (1U) 1060 #define SRX_CH_S_DMA_RD_CFG(x) (((uint32_t)(((uint32_t)(x)) << SRX_CH_S_DMA_RD_CFG_SHIFT)) & SRX_CH_S_DMA_RD_CFG_MASK) 1061 1062 #define SRX_CH_S_DMA_RD_TYPE_MASK (0x8000000U) 1063 #define SRX_CH_S_DMA_RD_TYPE_SHIFT (27U) 1064 #define SRX_CH_S_DMA_RD_TYPE_WIDTH (1U) 1065 #define SRX_CH_S_DMA_RD_TYPE(x) (((uint32_t)(((uint32_t)(x)) << SRX_CH_S_DMA_RD_TYPE_SHIFT)) & SRX_CH_S_DMA_RD_TYPE_MASK) 1066 1067 #define SRX_CH_S_DMA_RD_CHNUM_MASK (0xF0000000U) 1068 #define SRX_CH_S_DMA_RD_CHNUM_SHIFT (28U) 1069 #define SRX_CH_S_DMA_RD_CHNUM_WIDTH (4U) 1070 #define SRX_CH_S_DMA_RD_CHNUM(x) (((uint32_t)(((uint32_t)(x)) << SRX_CH_S_DMA_RD_CHNUM_SHIFT)) & SRX_CH_S_DMA_RD_CHNUM_MASK) 1071 /*! @} */ 1072 1073 /*! @name CH_S_DMA_CRC - Channel '0' DMA Slow Serial Message Bit2 Read..Channel '7' DMA Slow Serial Message Bit2 Read */ 1074 /*! @{ */ 1075 1076 #define SRX_CH_S_DMA_CRC_DATA_MASK (0xFFFU) 1077 #define SRX_CH_S_DMA_CRC_DATA_SHIFT (0U) 1078 #define SRX_CH_S_DMA_CRC_DATA_WIDTH (12U) 1079 #define SRX_CH_S_DMA_CRC_DATA(x) (((uint32_t)(((uint32_t)(x)) << SRX_CH_S_DMA_CRC_DATA_SHIFT)) & SRX_CH_S_DMA_CRC_DATA_MASK) 1080 1081 #define SRX_CH_S_DMA_CRC_SMCRC_MASK (0x3F0000U) 1082 #define SRX_CH_S_DMA_CRC_SMCRC_SHIFT (16U) 1083 #define SRX_CH_S_DMA_CRC_SMCRC_WIDTH (6U) 1084 #define SRX_CH_S_DMA_CRC_SMCRC(x) (((uint32_t)(((uint32_t)(x)) << SRX_CH_S_DMA_CRC_SMCRC_SHIFT)) & SRX_CH_S_DMA_CRC_SMCRC_MASK) 1085 /*! @} */ 1086 1087 /*! @name CH_S_DMA_TS - Channel '0' DMA Slow Serial Message Time Stamp Read..Channel '7' DMA Slow Serial Message Time Stamp Read */ 1088 /*! @{ */ 1089 1090 #define SRX_CH_S_DMA_TS_TS_MASK (0xFFFFFFFFU) 1091 #define SRX_CH_S_DMA_TS_TS_SHIFT (0U) 1092 #define SRX_CH_S_DMA_TS_TS_WIDTH (32U) 1093 #define SRX_CH_S_DMA_TS_TS(x) (((uint32_t)(((uint32_t)(x)) << SRX_CH_S_DMA_TS_TS_SHIFT)) & SRX_CH_S_DMA_TS_TS_MASK) 1094 /*! @} */ 1095 1096 /*! @name CHNL_TIMESTAMP - Channel '0' Time Stamp..Channel '7' Time Stamp */ 1097 /*! @{ */ 1098 1099 #define SRX_CHNL_TIMESTAMP_CHn_TS_MASK (0xFFFFFFFFU) 1100 #define SRX_CHNL_TIMESTAMP_CHn_TS_SHIFT (0U) 1101 #define SRX_CHNL_TIMESTAMP_CHn_TS_WIDTH (32U) 1102 #define SRX_CHNL_TIMESTAMP_CHn_TS(x) (((uint32_t)(((uint32_t)(x)) << SRX_CHNL_TIMESTAMP_CHn_TS_SHIFT)) & SRX_CHNL_TIMESTAMP_CHn_TS_MASK) 1103 /*! @} */ 1104 1105 /*! @name CHNL_COUNTER - Channel '0' Counter..Channel '7' Counter */ 1106 /*! @{ */ 1107 1108 #define SRX_CHNL_COUNTER_EDGE_CNT_MASK (0xFFU) 1109 #define SRX_CHNL_COUNTER_EDGE_CNT_SHIFT (0U) 1110 #define SRX_CHNL_COUNTER_EDGE_CNT_WIDTH (8U) 1111 #define SRX_CHNL_COUNTER_EDGE_CNT(x) (((uint32_t)(((uint32_t)(x)) << SRX_CHNL_COUNTER_EDGE_CNT_SHIFT)) & SRX_CHNL_COUNTER_EDGE_CNT_MASK) 1112 1113 #define SRX_CHNL_COUNTER_CLR_EDGE_CNT_MASK (0x8000U) 1114 #define SRX_CHNL_COUNTER_CLR_EDGE_CNT_SHIFT (15U) 1115 #define SRX_CHNL_COUNTER_CLR_EDGE_CNT_WIDTH (1U) 1116 #define SRX_CHNL_COUNTER_CLR_EDGE_CNT(x) (((uint32_t)(((uint32_t)(x)) << SRX_CHNL_COUNTER_CLR_EDGE_CNT_SHIFT)) & SRX_CHNL_COUNTER_CLR_EDGE_CNT_MASK) 1117 1118 #define SRX_CHNL_COUNTER_FRAME_CNT_MASK (0xFF0000U) 1119 #define SRX_CHNL_COUNTER_FRAME_CNT_SHIFT (16U) 1120 #define SRX_CHNL_COUNTER_FRAME_CNT_WIDTH (8U) 1121 #define SRX_CHNL_COUNTER_FRAME_CNT(x) (((uint32_t)(((uint32_t)(x)) << SRX_CHNL_COUNTER_FRAME_CNT_SHIFT)) & SRX_CHNL_COUNTER_FRAME_CNT_MASK) 1122 1123 #define SRX_CHNL_COUNTER_CLR_FRAME_CNT_MASK (0x80000000U) 1124 #define SRX_CHNL_COUNTER_CLR_FRAME_CNT_SHIFT (31U) 1125 #define SRX_CHNL_COUNTER_CLR_FRAME_CNT_WIDTH (1U) 1126 #define SRX_CHNL_COUNTER_CLR_FRAME_CNT(x) (((uint32_t)(((uint32_t)(x)) << SRX_CHNL_COUNTER_CLR_FRAME_CNT_SHIFT)) & SRX_CHNL_COUNTER_CLR_FRAME_CNT_MASK) 1127 /*! @} */ 1128 1129 /*! 1130 * @} 1131 */ /* end of group SRX_Register_Masks */ 1132 1133 /*! 1134 * @} 1135 */ /* end of group SRX_Peripheral_Access_Layer */ 1136 1137 #endif /* #if !defined(S32Z2_SRX_H_) */ 1138
