| /hal_nxp-latest/mcux/mcux-sdk/drivers/spdif/ |
| D | fsl_spdif.c | 114 base->SRPC = SPDIF_SRPC_CLKSRC_SEL(config->DPLLClkSource) | SPDIF_SRPC_GAINSEL(config->gain); in SPDIF_Init()
262 …uint64_t gain = s_spdif_gain[((base->SRPC & SPDIF_SRPC_GAINSEL_MASK) >> SPDIF_SRPC_GAINSEL_S… in SPDIF_GetRxSampleRate()
268 while ((base->SRPC & SPDIF_SRPC_LOCK_MASK) == 0U) in SPDIF_GetRxSampleRate()
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| /hal_nxp-latest/imx/devices/MCIMX6X/ |
| D | MCIMX6X_M4.h | 33786 __IO uint32_t SRPC; /**< PhaseConfig Register, offset: 0x8 */ member
33850 #define SPDIF_SRPC_REG(base) ((base)->SRPC)
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1015/ |
| D | MIMXRT1015.h | 30412 __IO uint32_t SRPC; /**< PhaseConfig Register, offset: 0x8 */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1011/ |
| D | MIMXRT1011.h | 27986 __IO uint32_t SRPC; /**< PhaseConfig Register, offset: 0x8 */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1021/ |
| D | MIMXRT1021.h | 35712 __IO uint32_t SRPC; /**< PhaseConfig Register, offset: 0x8 */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1024/ |
| D | MIMXRT1024.h | 35691 __IO uint32_t SRPC; /**< PhaseConfig Register, offset: 0x8 */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1041/ |
| D | MIMXRT1041.h | 38704 __IO uint32_t SRPC; /**< PhaseConfig Register, offset: 0x8 */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1051/ |
| D | MIMXRT1051.h | 37262 __IO uint32_t SRPC; /**< PhaseConfig Register, offset: 0x8 */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1042/ |
| D | MIMXRT1042.h | 42114 __IO uint32_t SRPC; /**< PhaseConfig Register, offset: 0x8 */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1052/ |
| D | MIMXRT1052.h | 41528 __IO uint32_t SRPC; /**< PhaseConfig Register, offset: 0x8 */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1061/ |
| D | MIMXRT1061.h | 39588 __IO uint32_t SRPC; /**< PhaseConfig Register, offset: 0x8 */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MN1/ |
| D | MIMX8MN1_cm7.h | 48275 __IO uint32_t SRPC; /**< PhaseConfig Register, offset: 0x8 */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MN2/ |
| D | MIMX8MN2_cm7.h | 48273 __IO uint32_t SRPC; /**< PhaseConfig Register, offset: 0x8 */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MN6/ |
| D | MIMX8MN6_cm7.h | 48273 __IO uint32_t SRPC; /**< PhaseConfig Register, offset: 0x8 */ member
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| D | MIMX8MN6_ca53.h | 48287 __IO uint32_t SRPC; /**< PhaseConfig Register, offset: 0x8 */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1062/ |
| D | MIMXRT1062.h | 43782 __IO uint32_t SRPC; /**< PhaseConfig Register, offset: 0x8 */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1064/ |
| D | MIMXRT1064.h | 43789 __IO uint32_t SRPC; /**< PhaseConfig Register, offset: 0x8 */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MN3/ |
| D | MIMX8MN3_cm7.h | 48275 __IO uint32_t SRPC; /**< PhaseConfig Register, offset: 0x8 */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MN4/ |
| D | MIMX8MN4_cm7.h | 48273 __IO uint32_t SRPC; /**< PhaseConfig Register, offset: 0x8 */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MQ5/ |
| D | MIMX8MQ5_cm4.h | 50302 __IO uint32_t SRPC; /**< PhaseConfig Register, offset: 0x8 */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MN5/ |
| D | MIMX8MN5_cm7.h | 48275 __IO uint32_t SRPC; /**< PhaseConfig Register, offset: 0x8 */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MQ6/ |
| D | MIMX8MQ6_cm4.h | 52475 __IO uint32_t SRPC; /**< PhaseConfig Register, offset: 0x8 */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MQ7/ |
| D | MIMX8MQ7_cm4.h | 52475 __IO uint32_t SRPC; /**< PhaseConfig Register, offset: 0x8 */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MD7/ |
| D | MIMX8MD7_cm4.h | 52475 __IO uint32_t SRPC; /**< PhaseConfig Register, offset: 0x8 */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MD6/ |
| D | MIMX8MD6_cm4.h | 52475 __IO uint32_t SRPC; /**< PhaseConfig Register, offset: 0x8 */ member
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