Searched refs:SRAMCR5 (Results 1 – 17 of 17) sorted by relevance
| /hal_nxp-latest/mcux/mcux-sdk/drivers/semc/ |
| D | fsl_semc.c | 1078 base->SRAMCR5 = timing; in SEMC_ConfigureSRAMWithChipSelection()
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1175/ |
| D | MIMXRT1175_cm4.h | 64999 __IO uint32_t SRAMCR5; /**< SRAM Control Register 5, offset: 0x124 */ member
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| D | MIMXRT1175_cm7.h | 64097 __IO uint32_t SRAMCR5; /**< SRAM Control Register 5, offset: 0x124 */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1165/ |
| D | MIMXRT1165_cm7.h | 63595 __IO uint32_t SRAMCR5; /**< SRAM Control Register 5, offset: 0x124 */ member
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| D | MIMXRT1165_cm4.h | 64497 __IO uint32_t SRAMCR5; /**< SRAM Control Register 5, offset: 0x124 */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1171/ |
| D | MIMXRT1171.h | 64097 __IO uint32_t SRAMCR5; /**< SRAM Control Register 5, offset: 0x124 */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1166/ |
| D | MIMXRT1166_cm4.h | 69960 __IO uint32_t SRAMCR5; /**< SRAM Control Register 5, offset: 0x124 */ member
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| D | MIMXRT1166_cm7.h | 69058 __IO uint32_t SRAMCR5; /**< SRAM Control Register 5, offset: 0x124 */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1173/ |
| D | MIMXRT1173_cm4.h | 70459 __IO uint32_t SRAMCR5; /**< SRAM Control Register 5, offset: 0x124 */ member
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| D | MIMXRT1173_cm7.h | 69557 __IO uint32_t SRAMCR5; /**< SRAM Control Register 5, offset: 0x124 */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1172/ |
| D | MIMXRT1172.h | 69560 __IO uint32_t SRAMCR5; /**< SRAM Control Register 5, offset: 0x124 */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1176/ |
| D | MIMXRT1176_cm7.h | 80227 __IO uint32_t SRAMCR5; /**< SRAM Control Register 5, offset: 0x124 */ member
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| D | MIMXRT1176_cm4.h | 81129 __IO uint32_t SRAMCR5; /**< SRAM Control Register 5, offset: 0x124 */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1187/ |
| D | MIMXRT1187_cm33.h | 73985 __IO uint32_t SRAMCR5; /**< SRAM Control Register 5, offset: 0x124 */ member
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| D | MIMXRT1187_cm7.h | 71959 __IO uint32_t SRAMCR5; /**< SRAM Control Register 5, offset: 0x124 */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1189/ |
| D | MIMXRT1189_cm33.h | 77833 __IO uint32_t SRAMCR5; /**< SRAM Control Register 5, offset: 0x124 */ member
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| D | MIMXRT1189_cm7.h | 75788 __IO uint32_t SRAMCR5; /**< SRAM Control Register 5, offset: 0x124 */ member
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