| /hal_nxp-latest/mcux/mcux-sdk/drivers/semc/ |
| D | fsl_semc.c | 1040 base->SRAMCR1 = timing; in SEMC_ConfigureSRAMWithChipSelection()
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1021/ |
| D | MIMXRT1021.h | 33255 __IO uint32_t SRAMCR1; /**< SRAM Control Register 1, offset: 0x74 */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1024/ |
| D | MIMXRT1024.h | 33234 __IO uint32_t SRAMCR1; /**< SRAM Control Register 1, offset: 0x74 */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1041/ |
| D | MIMXRT1041.h | 36035 __IO uint32_t SRAMCR1; /**< SRAM Control Register 1, offset: 0x74 */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1051/ |
| D | MIMXRT1051.h | 34818 __IO uint32_t SRAMCR1; /**< SRAM control register 1, offset: 0x74 */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1042/ |
| D | MIMXRT1042.h | 39445 __IO uint32_t SRAMCR1; /**< SRAM Control Register 1, offset: 0x74 */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1052/ |
| D | MIMXRT1052.h | 39084 __IO uint32_t SRAMCR1; /**< SRAM control register 1, offset: 0x74 */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1061/ |
| D | MIMXRT1061.h | 36919 __IO uint32_t SRAMCR1; /**< SRAM Control Register 1, offset: 0x74 */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1062/ |
| D | MIMXRT1062.h | 41113 __IO uint32_t SRAMCR1; /**< SRAM Control Register 1, offset: 0x74 */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1064/ |
| D | MIMXRT1064.h | 41120 __IO uint32_t SRAMCR1; /**< SRAM Control Register 1, offset: 0x74 */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1187/ |
| D | MIMXRT1187_cm33.h | 8813 __IO uint32_t SRAMCR1; /**< SRAM Control Register 1, offset: 0x58 */ member
73949 __IO uint32_t SRAMCR1; /**< SRAM Control Register 1, offset: 0x74 */ member
|
| D | MIMXRT1187_cm7.h | 8496 __IO uint32_t SRAMCR1; /**< SRAM Control Register 1, offset: 0x58 */ member
71923 __IO uint32_t SRAMCR1; /**< SRAM Control Register 1, offset: 0x74 */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1189/ |
| D | MIMXRT1189_cm7.h | 8495 __IO uint32_t SRAMCR1; /**< SRAM Control Register 1, offset: 0x58 */ member
75752 __IO uint32_t SRAMCR1; /**< SRAM Control Register 1, offset: 0x74 */ member
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| D | MIMXRT1189_cm33.h | 8812 __IO uint32_t SRAMCR1; /**< SRAM Control Register 1, offset: 0x58 */ member
77797 __IO uint32_t SRAMCR1; /**< SRAM Control Register 1, offset: 0x74 */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1165/ |
| D | MIMXRT1165_cm4.h | 64461 __IO uint32_t SRAMCR1; /**< SRAM Control Register 1, offset: 0x74 */ member
|
| D | MIMXRT1165_cm7.h | 63559 __IO uint32_t SRAMCR1; /**< SRAM Control Register 1, offset: 0x74 */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1171/ |
| D | MIMXRT1171.h | 64061 __IO uint32_t SRAMCR1; /**< SRAM Control Register 1, offset: 0x74 */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1175/ |
| D | MIMXRT1175_cm4.h | 64963 __IO uint32_t SRAMCR1; /**< SRAM Control Register 1, offset: 0x74 */ member
|
| D | MIMXRT1175_cm7.h | 64061 __IO uint32_t SRAMCR1; /**< SRAM Control Register 1, offset: 0x74 */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1173/ |
| D | MIMXRT1173_cm7.h | 69521 __IO uint32_t SRAMCR1; /**< SRAM Control Register 1, offset: 0x74 */ member
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| D | MIMXRT1173_cm4.h | 70423 __IO uint32_t SRAMCR1; /**< SRAM Control Register 1, offset: 0x74 */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1166/ |
| D | MIMXRT1166_cm7.h | 69022 __IO uint32_t SRAMCR1; /**< SRAM Control Register 1, offset: 0x74 */ member
|
| D | MIMXRT1166_cm4.h | 69924 __IO uint32_t SRAMCR1; /**< SRAM Control Register 1, offset: 0x74 */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1172/ |
| D | MIMXRT1172.h | 69524 __IO uint32_t SRAMCR1; /**< SRAM Control Register 1, offset: 0x74 */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1176/ |
| D | MIMXRT1176_cm7.h | 80191 __IO uint32_t SRAMCR1; /**< SRAM Control Register 1, offset: 0x74 */ member
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