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/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT595S/gcc/
DMIMXRT595Sxxxx_cm33_flash_ns.ld36 /* The SRAM region [0x10000-0x1BFFF] is reserved for ROM code. */
37 /* The SRAM region [0x0-0xFFFF], [0x1C000-0x1FFFF] are reserved for app-specific use cases. */
38 /* The SRAM region [0x20000-0x7FFFF] is reserved for Non-cached shared memory between M33 and DSP. …
39 /* The SRAM region [0x80000-0x27FFFF] is reserved for DSP code and data. */
44 /* Use the same SRAM partition with ram_ns linker to share the same SAU configuration. */
DMIMXRT595Sxxxx_cm33_flash_s.ld36 /* The SRAM region [0x10000-0x1BFFF] is reserved for ROM code. */
37 /* The SRAM region [0x0-0xFFFF], [0x1C000-0x1FFFF] are reserved for app-specific use cases. */
38 /* The SRAM region [0x20000-0x7FFFF] is reserved for Non-cached shared memory between M33 and DSP. …
39 /* The SRAM region [0x80000-0x27FFFF] is reserved for DSP code and data. */
46 /* Use the same SRAM partition with ram_s linker to share the same SAU configuration. */
DMIMXRT595Sxxxx_cm33_ram_ns.ld35 /* The SRAM region [0x10000-0x1BFFF] is reserved for ROM code. */
36 /* The SRAM region [0x0-0xFFFF], [0x1C000-0x1FFFF] are reserved for app-specific use cases. */
37 /* The SRAM region [0x20000-0x7FFFF] is reserved for Non-cached shared memory between M33 and DSP. …
38 /* The SRAM region [0x80000-0x27FFFF] is reserved for DSP code and data. */
DMIMXRT595Sxxxx_cm33_flash.ld36 /* The SRAM region [0x10000-0x1BFFF] is reserved for ROM code. */
37 /* The SRAM region [0x0-0xFFFF], [0x1C000-0x1FFFF] are reserved for app-specific use cases. */
38 /* The SRAM region [0x20000-0x7FFFF] is reserved for Non-cached shared memory between M33 and DSP. …
39 /* The SRAM region [0x80000-0x27FFFF] is reserved for DSP code and data. */
DMIMXRT595Sxxxx_cm33_ram.ld35 /* The SRAM region [0x10000-0x1BFFF] is reserved for ROM code. */
36 /* The SRAM region [0x0-0xFFFF], [0x1C000-0x1FFFF] are reserved for app-specific use cases. */
37 /* The SRAM region [0x20000-0x7FFFF] is reserved for Non-cached shared memory between M33 and DSP. …
38 /* The SRAM region [0x80000-0x27FFFF] is reserved for DSP code and data. */
DMIMXRT595Sxxxx_cm33_ram_s.ld35 /* The SRAM region [0x10000-0x1BFFF] is reserved for ROM code. */
36 /* The SRAM region [0x0-0xFFFF], [0x1C000-0x1FFFF] are reserved for app-specific use cases. */
37 /* The SRAM region [0x20000-0x7FFFF] is reserved for Non-cached shared memory between M33 and DSP. …
38 /* The SRAM region [0x80000-0x27FFFF] is reserved for DSP code and data. */
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT685S/gcc/
DMIMXRT685Sxxxx_cm33_ram_ns.ld36 /* The SRAM region [0x10000-0x1BFFF] is reserved for ROM code. */
37 /* The SRAM region [0x0-0xFFFF], [0x1C000-0x1FFFF] is reserved for app-specific use cases. */
38 /* The SRAM region [0x20000-0x7FFFF] is reserved for Non-cached shared memory between M33 and DSP. …
DMIMXRT685Sxxxx_cm33_ram.ld36 /* The SRAM region [0x10000-0x1BFFF] is reserved for ROM code. */
37 /* The SRAM region [0x0-0xFFFF], [0x1C000-0x1FFFF] is reserved for app-specific use cases. */
38 /* The SRAM region [0x20000-0x7FFFF] is reserved for Non-cached shared memory between M33 and DSP. …
DMIMXRT685Sxxxx_cm33_ram_s.ld36 /* The SRAM region [0x10000-0x1BFFF] is reserved for ROM code. */
37 /* The SRAM region [0x0-0xFFFF], [0x1C000-0x1FFFF] is reserved for app-specific use cases. */
38 /* The SRAM region [0x20000-0x7FFFF] is reserved for Non-cached shared memory between M33 and DSP. …
DMIMXRT685Sxxxx_cm33_flash.ld37 /* The SRAM region [0x10000-0x1BFFF] is reserved for ROM code. */
38 /* The SRAM region [0x0-0xFFFF], [0x1C000-0x1FFFF] is reserved for app-specific use cases. */
39 /* The SRAM region [0x20000-0x7FFFF] is reserved for Non-cached shared memory between M33 and DSP. …
DMIMXRT685Sxxxx_cm33_flash_ns.ld37 /* The SRAM region [0x10000-0x1BFFF] is reserved for ROM code. */
38 /* The SRAM region [0x0-0xFFFF], [0x1C000-0x1FFFF] is reserved for app-specific use cases. */
39 /* The SRAM region [0x20000-0x7FFFF] is reserved for Non-cached shared memory between M33 and DSP. …
DMIMXRT685Sxxxx_cm33_flash_s.ld37 /* The SRAM region [0x10000-0x1BFFF] is reserved for ROM code. */
38 /* The SRAM region [0x0-0xFFFF], [0x1C000-0x1FFFF] is reserved for app-specific use cases. */
39 /* The SRAM region [0x20000-0x7FFFF] is reserved for Non-cached shared memory between M33 and DSP. …
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT633S/gcc/
DMIMXRT633Sxxxx_ram.ld36 /* The SRAM region [0x10000-0x1BFFF] is reserved for ROM code. */
37 /* The SRAM region [0x0-0xFFFF], [0x1C000-0x7FFFF] is reserved for app-specific use cases. */
DMIMXRT633Sxxxx_flash.ld37 /* The SRAM region [0x10000-0x1BFFF] is reserved for ROM code. */
38 /* The SRAM region [0x0-0xFFFF], [0x1C000-0x7FFFF] is reserved for app-specific use cases. */
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT533S/gcc/
DMIMXRT533Sxxxx_ram.ld35 /* The SRAM region [0x10000-0x1BFFF] is reserved for ROM code. */
36 /* The SRAM region [0x0-0xFFFF], [0x1C000-0x7FFFF] are reserved for app-specific use cases. */
DMIMXRT533Sxxxx_flash.ld36 /* The SRAM region [0x10000-0x1BFFF] is reserved for ROM code. */
37 /* The SRAM region [0x0-0xFFFF], [0x1C000-0x7FFFF] are reserved for app-specific use cases. */
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC55S36/gcc/
DLPC55S36_flash.ld32 /* __pkc__ : SRAM A(16K) reserved for; pkc __power_down__ : The first 0x604 bytes reserved to CPU r…
34 POWERQUAD_RAMSIZE = DEFINED(__powerquad__) ? 0x00004000 : 0x00000000; /* SRAM E(16K) reserved for…
DLPC55S36_ram.ld32 /* __pkc__ : SRAM A(16K) reserved for; pkc __power_down__ : The first 0x604 bytes reserved to CPU r…
34 POWERQUAD_RAMSIZE = DEFINED(__powerquad__) ? 0x00004000 : 0x0; /* SRAM E(16K) reserved …
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT555S/gcc/
DMIMXRT555Sxxxx_ram.ld35 /* The SRAM region [0x10000-0x1BFFF] is reserved for ROM code. */
36 /* The SRAM region [0x0-0xFFFF], [0x1C000-0x7FFFF] are reserved for app-specific use cases. */
DMIMXRT555Sxxxx_flash.ld36 /* The SRAM region [0x10000-0x1BFFF] is reserved for ROM code. */
37 /* The SRAM region [0x0-0xFFFF], [0x1C000-0x7FFFF] are reserved for app-specific use cases. */
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC5536/gcc/
DLPC5536_flash.ld33 /* __pkc__ : SRAM A(16K) reserved for; pkc __power_down__ : The first 0x604 bytes reserved to CPU r…
35 POWERQUAD_RAMSIZE = DEFINED(__powerquad__) ? 0x00004000 : 0x00000000; /* SRAM E(16K) reserved for…
DLPC5536_ram.ld33 /* __pkc__ : SRAM A(16K) reserved for; pkc __power_down__ : The first 0x604 bytes reserved to CPU r…
35 POWERQUAD_RAMSIZE = DEFINED(__powerquad__) ? 0x00004000 : 0x0; /* SRAM E(16K) reserved …
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC5534/gcc/
DLPC5534_ram.ld33 /* __pkc__ : SRAM A(16K) reserved for; pkc __power_down__ : The first 0x604 bytes reserved to CPU r…
DLPC5534_flash.ld33 /* __pkc__ : SRAM A(16K) reserved for; pkc __power_down__ : The first 0x604 bytes reserved to CPU r…
/hal_nxp-latest/mcux/mcux-sdk/components/power_manager/
DREADME.md104 …raging the SDK Power Manager. In this application, the code is running in SRAM partition 16 (0x201…
124 In deep sleep, only the defined SRAM partition and the FLEXSPI0 SRAM are retained, i.e., the memory…

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