Searched refs:SPM_DCDCC3_DCDC_MINPWR_DC_HALFCLK_MASK (Results 1 – 3 of 3) sorted by relevance
786 base->DCDCC3 |= SPM_DCDCC3_DCDC_MINPWR_DC_HALFCLK_MASK; in SPM_SplitDcdcClockFreq()790 base->DCDCC3 &= ~SPM_DCDCC3_DCDC_MINPWR_DC_HALFCLK_MASK; in SPM_SplitDcdcClockFreq()
20266 #define SPM_DCDCC3_DCDC_MINPWR_DC_HALFCLK_MASK (0x1000000U) macro20269 …int32_t)(x)) << SPM_DCDCC3_DCDC_MINPWR_DC_HALFCLK_SHIFT)) & SPM_DCDCC3_DCDC_MINPWR_DC_HALFCLK_MASK)
20376 #define SPM_DCDCC3_DCDC_MINPWR_DC_HALFCLK_MASK (0x1000000U) macro20379 …int32_t)(x)) << SPM_DCDCC3_DCDC_MINPWR_DC_HALFCLK_SHIFT)) & SPM_DCDCC3_DCDC_MINPWR_DC_HALFCLK_MASK)
