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Searched refs:SPLLCFG (Results 1 – 25 of 30) sorted by relevance

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/hal_nxp-latest/s32/drivers/s32k1/Mcu/src/
DClock_Ip_Pll.c272 IP_SCG->SPLLCFG &= (~((uint32)SCG_SPLLCFG_SOURCE_MASK)); in Clock_Ip_ResetSpll_TrustedCall()
274 IP_SCG->SPLLCFG &= (~((uint32)SCG_SPLLCFG_PREDIV_MASK)); in Clock_Ip_ResetSpll_TrustedCall()
275 IP_SCG->SPLLCFG &= (~((uint32)SCG_SPLLCFG_MULT_MASK)); in Clock_Ip_ResetSpll_TrustedCall()
286 IP_SCG->SPLLCFG |= SCG_SPLLCFG_SOURCE(0UL); in Clock_Ip_SetSpll_TrustedCall()
290 IP_SCG->SPLLCFG |= SCG_SPLLCFG_SOURCE(1UL); in Clock_Ip_SetSpll_TrustedCall()
295 IP_SCG->SPLLCFG |= SCG_SPLLCFG_PREDIV((uint32)(Config->Predivider) - 1U) | in Clock_Ip_SetSpll_TrustedCall()
DClock_Ip_Frequency.c725 if (SpllChecksum != IP_SCG->SPLLCFG) in get_SPLL_CLK_Frequency()
727 SpllChecksum = IP_SCG->SPLLCFG; in get_SPLL_CLK_Frequency()
1627 if ((IP_SCG->SPLLCFG & SCG_SPLLCFG_SOURCE_MASK) == 0U) in PLL_VCO()
1638 …Prediv = (((Base->SPLLCFG & SCG_SPLLCFG_PREDIV_MASK) >> SCG_SPLLCFG_PREDIV_SHIFT) + 1U) << 1U; … in PLL_VCO()
1639 …Mul = (((Base->SPLLCFG & SCG_SPLLCFG_MULT_MASK) >> SCG_SPLLCFG_MULT_SHIFT) + 16U); … in PLL_VCO()
DClock_Ip_Specific.c620 …SpllConfiguration.Predivider = (uint8)((IP_SCG->SPLLCFG & SCG_SPLLCFG_PREDIV_MASK) >> SCG_SPLLCFG_… in getSpllConfig()
621 …SpllConfiguration.MulFactorDiv = (uint8)((IP_SCG->SPLLCFG & SCG_SPLLCFG_MULT_MASK) >> SCG_SPLLCFG_… in getSpllConfig()
/hal_nxp-latest/mcux/mcux-sdk/devices/MCIMX7U3/
Dsystem_MCIMX7U3_cm4.c189 SCGOUTClock = (0u == (SCG0->SPLLCFG & SCG_SPLLCFG_SOURCE_MASK)) ? CPU_XTAL_SOSC_CLK_HZ : in SystemCoreClockUpdate()
191 SCGOUTClock /= ((SCG0->SPLLCFG & SCG_SPLLCFG_PREDIV_MASK) >> SCG_SPLLCFG_PREDIV_SHIFT) + 1u; in SystemCoreClockUpdate()
192 SCGOUTClock *= spllMulti[((SCG0->SPLLCFG & SCG_SPLLCFG_MULT_MASK) >> SCG_SPLLCFG_MULT_SHIFT)]; in SystemCoreClockUpdate()
194 if (0u != (SCG0->SPLLCFG & SCG_SPLLCFG_PLLS_MASK)) in SystemCoreClockUpdate()
197 switch (SCG0->SPLLCFG & SCG_SPLLCFG_PFDSEL_MASK) in SystemCoreClockUpdate()
/hal_nxp-latest/mcux/mcux-sdk/devices/MCIMX7U5/
Dsystem_MCIMX7U5_cm4.c190 SCGOUTClock = (0u == (SCG0->SPLLCFG & SCG_SPLLCFG_SOURCE_MASK)) ? CPU_XTAL_SOSC_CLK_HZ : in SystemCoreClockUpdate()
192 SCGOUTClock /= ((SCG0->SPLLCFG & SCG_SPLLCFG_PREDIV_MASK) >> SCG_SPLLCFG_PREDIV_SHIFT) + 1u; in SystemCoreClockUpdate()
193 SCGOUTClock *= spllMulti[((SCG0->SPLLCFG & SCG_SPLLCFG_MULT_MASK) >> SCG_SPLLCFG_MULT_SHIFT)]; in SystemCoreClockUpdate()
195 if (0u != (SCG0->SPLLCFG & SCG_SPLLCFG_PLLS_MASK)) in SystemCoreClockUpdate()
198 switch (SCG0->SPLLCFG & SCG_SPLLCFG_PFDSEL_MASK) in SystemCoreClockUpdate()
/hal_nxp-latest/mcux/mcux-sdk/devices/K32L2A31A/
Dsystem_K32L2A31A.c107 if (((SCG->SPLLCFG & SCG_SPLLCFG_SOURCE_MASK) >> SCG_SPLLCFG_SOURCE_SHIFT) != 0U) in SystemCoreClockUpdate()
116 …prediv = (uint16_t)(((SCG->SPLLCFG & SCG_SPLLCFG_PREDIV_MASK) >> SCG_SPLLCFG_PREDIV_SHIFT) + … in SystemCoreClockUpdate()
117 …multi = (uint16_t)(((SCG->SPLLCFG & SCG_SPLLCFG_MULT_MASK) >> SCG_SPLLCFG_MULT_SHIFT) + 16U); in SystemCoreClockUpdate()
/hal_nxp-latest/mcux/mcux-sdk/devices/K32L2A41A/
Dsystem_K32L2A41A.c107 if (((SCG->SPLLCFG & SCG_SPLLCFG_SOURCE_MASK) >> SCG_SPLLCFG_SOURCE_SHIFT) != 0U) in SystemCoreClockUpdate()
116 …prediv = (uint16_t)(((SCG->SPLLCFG & SCG_SPLLCFG_PREDIV_MASK) >> SCG_SPLLCFG_PREDIV_SHIFT) + … in SystemCoreClockUpdate()
117 …multi = (uint16_t)(((SCG->SPLLCFG & SCG_SPLLCFG_MULT_MASK) >> SCG_SPLLCFG_MULT_SHIFT) + 16U); in SystemCoreClockUpdate()
DK32L2A41A.h14390 …__IO uint32_t SPLLCFG; /**< System PLL Configuration Register, offset: 0… member
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE18F16/
Dsystem_MKE18F16.c131 if (((SCG->SPLLCFG & SCG_SPLLCFG_SOURCE_MASK) >> SCG_SPLLCFG_SOURCE_SHIFT) != 0U) { in SystemCoreClockUpdate()
137 … prediv = (uint16_t)(((SCG->SPLLCFG & SCG_SPLLCFG_PREDIV_MASK) >> SCG_SPLLCFG_PREDIV_SHIFT) + 1U); in SystemCoreClockUpdate()
138 multi = (uint16_t)(((SCG->SPLLCFG & SCG_SPLLCFG_MULT_MASK) >> SCG_SPLLCFG_MULT_SHIFT) + 16U); in SystemCoreClockUpdate()
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE16F16/
Dsystem_MKE16F16.c131 if (((SCG->SPLLCFG & SCG_SPLLCFG_SOURCE_MASK) >> SCG_SPLLCFG_SOURCE_SHIFT) != 0U) { in SystemCoreClockUpdate()
137 … prediv = (uint16_t)(((SCG->SPLLCFG & SCG_SPLLCFG_PREDIV_MASK) >> SCG_SPLLCFG_PREDIV_SHIFT) + 1U); in SystemCoreClockUpdate()
138 multi = (uint16_t)(((SCG->SPLLCFG & SCG_SPLLCFG_MULT_MASK) >> SCG_SPLLCFG_MULT_SHIFT) + 16U); in SystemCoreClockUpdate()
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE14F16/
Dsystem_MKE14F16.c131 if (((SCG->SPLLCFG & SCG_SPLLCFG_SOURCE_MASK) >> SCG_SPLLCFG_SOURCE_SHIFT) != 0U) { in SystemCoreClockUpdate()
137 … prediv = (uint16_t)(((SCG->SPLLCFG & SCG_SPLLCFG_PREDIV_MASK) >> SCG_SPLLCFG_PREDIV_SHIFT) + 1U); in SystemCoreClockUpdate()
138 multi = (uint16_t)(((SCG->SPLLCFG & SCG_SPLLCFG_MULT_MASK) >> SCG_SPLLCFG_MULT_SHIFT) + 16U); in SystemCoreClockUpdate()
DMKE14F16.h15337 …__IO uint32_t SPLLCFG; /**< System PLL Configuration Register, offset: 0… member
/hal_nxp-latest/mcux/mcux-sdk/devices/MCIMX7U3/drivers/
Dfsl_clock.c81 #define SCG_SPLLCFG_PREDIV_VAL ((SCG->SPLLCFG & SCG_SPLLCFG_PREDIV_MASK) >> SCG_SPLLCFG_PREDIV_SHIF…
82 #define SCG_SPLLCFG_MULT_VAL ((SCG->SPLLCFG & SCG_SPLLCFG_MULT_MASK) >> SCG_SPLLCFG_MULT_SHIFT)
1429 SCG->SPLLCFG = SCG_SPLLCFG_SOURCE(config->src) | SCG_SPLLCFG_PREDIV(config->prediv) | in CLOCK_InitSysPll()
1484 if ((SCG->SPLLCFG & SCG_SPLLCFG_SOURCE_MASK) != 0UL) /* If use FIRC */ in CLOCK_GetSysPllCommonFreq()
1512 if ((SCG->SPLLCFG & SCG_SPLLCFG_PLLS_MASK) != 0UL) in CLOCK_GetSysPllFreq()
1516 ((SCG->SPLLCFG & SCG_SPLLCFG_PFDSEL_MASK) >> SCG_SPLLCFG_PFDSEL_SHIFT) << 3U); in CLOCK_GetSysPllFreq()
/hal_nxp-latest/mcux/mcux-sdk/devices/MCIMX7U5/drivers/
Dfsl_clock.c81 #define SCG_SPLLCFG_PREDIV_VAL ((SCG->SPLLCFG & SCG_SPLLCFG_PREDIV_MASK) >> SCG_SPLLCFG_PREDIV_SHIF…
82 #define SCG_SPLLCFG_MULT_VAL ((SCG->SPLLCFG & SCG_SPLLCFG_MULT_MASK) >> SCG_SPLLCFG_MULT_SHIFT)
1429 SCG->SPLLCFG = SCG_SPLLCFG_SOURCE(config->src) | SCG_SPLLCFG_PREDIV(config->prediv) | in CLOCK_InitSysPll()
1484 if ((SCG->SPLLCFG & SCG_SPLLCFG_SOURCE_MASK) != 0UL) /* If use FIRC */ in CLOCK_GetSysPllCommonFreq()
1512 if ((SCG->SPLLCFG & SCG_SPLLCFG_PLLS_MASK) != 0UL) in CLOCK_GetSysPllFreq()
1516 ((SCG->SPLLCFG & SCG_SPLLCFG_PFDSEL_MASK) >> SCG_SPLLCFG_PFDSEL_SHIFT) << 3U); in CLOCK_GetSysPllFreq()
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE18F16/drivers/
Dfsl_clock.c64 #define SCG_SPLLCFG_PREDIV_VAL ((SCG->SPLLCFG & SCG_SPLLCFG_PREDIV_MASK) >> SCG_SPLLCFG_PREDIV_SHIF…
65 #define SCG_SPLLCFG_MULT_VAL ((SCG->SPLLCFG & SCG_SPLLCFG_MULT_MASK) >> SCG_SPLLCFG_MULT_SHIFT)
1037 SCG->SPLLCFG = in CLOCK_InitSysPll()
1094 if ((SCG->SPLLCFG & SCG_SPLLCFG_SOURCE_MASK) != 0UL) /* If use FIRC */ in CLOCK_GetSysPllCommonFreq()
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE14F16/drivers/
Dfsl_clock.c64 #define SCG_SPLLCFG_PREDIV_VAL ((SCG->SPLLCFG & SCG_SPLLCFG_PREDIV_MASK) >> SCG_SPLLCFG_PREDIV_SHIF…
65 #define SCG_SPLLCFG_MULT_VAL ((SCG->SPLLCFG & SCG_SPLLCFG_MULT_MASK) >> SCG_SPLLCFG_MULT_SHIFT)
1037 SCG->SPLLCFG = in CLOCK_InitSysPll()
1094 if ((SCG->SPLLCFG & SCG_SPLLCFG_SOURCE_MASK) != 0UL) /* If use FIRC */ in CLOCK_GetSysPllCommonFreq()
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE16F16/drivers/
Dfsl_clock.c64 #define SCG_SPLLCFG_PREDIV_VAL ((SCG->SPLLCFG & SCG_SPLLCFG_PREDIV_MASK) >> SCG_SPLLCFG_PREDIV_SHIF…
65 #define SCG_SPLLCFG_MULT_VAL ((SCG->SPLLCFG & SCG_SPLLCFG_MULT_MASK) >> SCG_SPLLCFG_MULT_SHIFT)
1037 SCG->SPLLCFG = in CLOCK_InitSysPll()
1094 if ((SCG->SPLLCFG & SCG_SPLLCFG_SOURCE_MASK) != 0UL) /* If use FIRC */ in CLOCK_GetSysPllCommonFreq()
/hal_nxp-latest/mcux/mcux-sdk/devices/K32L2A41A/drivers/
Dfsl_clock.c68 #define SCG_SPLLCFG_PREDIV_VAL ((SCG->SPLLCFG & SCG_SPLLCFG_PREDIV_MASK) >> SCG_SPLLCFG_PREDIV_SHIF…
69 #define SCG_SPLLCFG_MULT_VAL ((SCG->SPLLCFG & SCG_SPLLCFG_MULT_MASK) >> SCG_SPLLCFG_MULT_SHIFT)
1077 SCG->SPLLCFG = in CLOCK_InitSysPll()
1134 if ((SCG->SPLLCFG & SCG_SPLLCFG_SOURCE_MASK) != 0UL) /* If use FIRC */ in CLOCK_GetSysPllCommonFreq()
/hal_nxp-latest/mcux/mcux-sdk/devices/K32L2A31A/drivers/
Dfsl_clock.c68 #define SCG_SPLLCFG_PREDIV_VAL ((SCG->SPLLCFG & SCG_SPLLCFG_PREDIV_MASK) >> SCG_SPLLCFG_PREDIV_SHIF…
69 #define SCG_SPLLCFG_MULT_VAL ((SCG->SPLLCFG & SCG_SPLLCFG_MULT_MASK) >> SCG_SPLLCFG_MULT_SHIFT)
1077 SCG->SPLLCFG = in CLOCK_InitSysPll()
1134 if ((SCG->SPLLCFG & SCG_SPLLCFG_SOURCE_MASK) != 0UL) /* If use FIRC */ in CLOCK_GetSysPllCommonFreq()
/hal_nxp-latest/s32/drivers/s32k1/BaseNXP/header/
DS32K142W_SCG.h96 …__IO uint32_t SPLLCFG; /**< System PLL Configuration Register, offset: 0… member
DS32K142_SCG.h96 …__IO uint32_t SPLLCFG; /**< System PLL Configuration Register, offset: 0… member
DS32K146_SCG.h96 …__IO uint32_t SPLLCFG; /**< System PLL Configuration Register, offset: 0… member
DS32K144_SCG.h96 …__IO uint32_t SPLLCFG; /**< System PLL Configuration Register, offset: 0… member
DS32K148_SCG.h96 …__IO uint32_t SPLLCFG; /**< System PLL Configuration Register, offset: 0… member
DS32K144W_SCG.h96 …__IO uint32_t SPLLCFG; /**< System PLL Configuration Register, offset: 0… member

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