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Searched refs:SPI_RSER_TFFF_RE_MASK (Results 1 – 25 of 37) sorted by relevance

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/hal_nxp-latest/mcux/mcux-sdk/drivers/dspi/
Dfsl_dspi.h72 …kDSPI_TxFifoFillRequestInterruptEnable = SPI_RSER_TFFF_RE_MASK, /*!< TFFF interrupt enable, D…
79 … SPI_RSER_TFFF_RE_MASK | SPI_RSER_RFOF_RE_MASK | SPI_RSER_RFDF_RE_MASK)
86 …kDSPI_TxDmaEnable = (SPI_RSER_TFFF_RE_MASK | SPI_RSER_TFFF_DIRS_MASK), /*!< TFFF flag generates DM…
Dfsl_dspi.c849 if (0U != (mask & SPI_RSER_TFFF_RE_MASK)) in DSPI_EnableInterrupts()
/hal_nxp-latest/s32/drivers/s32ze/BaseNXP/header/
DS32Z2_SPI.h489 #define SPI_RSER_TFFF_RE_MASK (0x2000000U) macro
492 … (((uint32_t)(((uint32_t)(x)) << SPI_RSER_TFFF_RE_SHIFT)) & SPI_RSER_TFFF_RE_MASK)
/hal_nxp-latest/s32/mcux/devices/S32Z270/
DS32Z270_device.h2861 #define SPI_RSER_TFFF_RE_MASK DSPI_RSER_TFFF_RE_MASK macro
/hal_nxp-latest/mcux/mcux-sdk/devices/MK02F12810/
DMK02F12810.h9433 #define SPI_RSER_TFFF_RE_MASK (0x2000000U) macro
9439 … (((uint32_t)(((uint32_t)(x)) << SPI_RSER_TFFF_RE_SHIFT)) & SPI_RSER_TFFF_RE_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKV30F12810/
DMKV30F12810.h9466 #define SPI_RSER_TFFF_RE_MASK (0x2000000U) macro
9472 … (((uint32_t)(((uint32_t)(x)) << SPI_RSER_TFFF_RE_SHIFT)) & SPI_RSER_TFFF_RE_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKV10Z7/
DMKV10Z7.h9369 #define SPI_RSER_TFFF_RE_MASK (0x2000000U) macro
9375 … (((uint32_t)(((uint32_t)(x)) << SPI_RSER_TFFF_RE_SHIFT)) & SPI_RSER_TFFF_RE_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKV31F12810/
DMKV31F12810.h10252 #define SPI_RSER_TFFF_RE_MASK (0x2000000U) macro
10258 … (((uint32_t)(((uint32_t)(x)) << SPI_RSER_TFFF_RE_SHIFT)) & SPI_RSER_TFFF_RE_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKV10Z1287/
DMKV10Z1287.h10405 #define SPI_RSER_TFFF_RE_MASK (0x2000000U) macro
10411 … (((uint32_t)(((uint32_t)(x)) << SPI_RSER_TFFF_RE_SHIFT)) & SPI_RSER_TFFF_RE_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKV11Z7/
DMKV11Z7.h11193 #define SPI_RSER_TFFF_RE_MASK (0x2000000U) macro
11199 … (((uint32_t)(((uint32_t)(x)) << SPI_RSER_TFFF_RE_SHIFT)) & SPI_RSER_TFFF_RE_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKV31F25612/
DMKV31F25612.h11323 #define SPI_RSER_TFFF_RE_MASK (0x2000000U) macro
11329 … (((uint32_t)(((uint32_t)(x)) << SPI_RSER_TFFF_RE_SHIFT)) & SPI_RSER_TFFF_RE_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKV31F51212/
DMKV31F51212.h11711 #define SPI_RSER_TFFF_RE_MASK (0x2000000U) macro
11717 … (((uint32_t)(((uint32_t)(x)) << SPI_RSER_TFFF_RE_SHIFT)) & SPI_RSER_TFFF_RE_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MK22F12810/
DMK22F12810.h11518 #define SPI_RSER_TFFF_RE_MASK (0x2000000U) macro
11524 … (((uint32_t)(((uint32_t)(x)) << SPI_RSER_TFFF_RE_SHIFT)) & SPI_RSER_TFFF_RE_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKW22D5/
DMKW22D5.h7050 #define SPI_RSER_TFFF_RE_MASK (0x2000000U) macro
7052 … (((uint32_t)(((uint32_t)(x)) << SPI_RSER_TFFF_RE_SHIFT)) & SPI_RSER_TFFF_RE_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKW24D5/
DMKW24D5.h7050 #define SPI_RSER_TFFF_RE_MASK (0x2000000U) macro
7052 … (((uint32_t)(((uint32_t)(x)) << SPI_RSER_TFFF_RE_SHIFT)) & SPI_RSER_TFFF_RE_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MK22F25612/
DMK22F25612.h12638 #define SPI_RSER_TFFF_RE_MASK (0x2000000U) macro
12644 … (((uint32_t)(((uint32_t)(x)) << SPI_RSER_TFFF_RE_SHIFT)) & SPI_RSER_TFFF_RE_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MK22F51212/
DMK22F51212.h13036 #define SPI_RSER_TFFF_RE_MASK (0x2000000U) macro
13042 … (((uint32_t)(((uint32_t)(x)) << SPI_RSER_TFFF_RE_SHIFT)) & SPI_RSER_TFFF_RE_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MK22F12/
DMK22F12.h17305 #define SPI_RSER_TFFF_RE_MASK (0x2000000U) macro
17311 … (((uint32_t)(((uint32_t)(x)) << SPI_RSER_TFFF_RE_SHIFT)) & SPI_RSER_TFFF_RE_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MK24F12/
DMK24F12.h20997 #define SPI_RSER_TFFF_RE_MASK (0x2000000U) macro
21003 … (((uint32_t)(((uint32_t)(x)) << SPI_RSER_TFFF_RE_SHIFT)) & SPI_RSER_TFFF_RE_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKW31Z4/
DMKW31Z4.h6872 #define SPI_RSER_TFFF_RE_MASK (0x2000000U) macro
6874 … (((uint32_t)(((uint32_t)(x)) << SPI_RSER_TFFF_RE_SHIFT)) & SPI_RSER_TFFF_RE_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKW30Z4/
DMKW30Z4.h7614 #define SPI_RSER_TFFF_RE_MASK 0x2000000u macro
7617 … (((uint32_t)(((uint32_t)(x))<<SPI_RSER_TFFF_RE_SHIFT))&SPI_RSER_TFFF_RE_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKW21Z4/
DMKW21Z4.h6801 #define SPI_RSER_TFFF_RE_MASK (0x2000000U) macro
6803 … (((uint32_t)(((uint32_t)(x)) << SPI_RSER_TFFF_RE_SHIFT)) & SPI_RSER_TFFF_RE_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKW20Z4/
DMKW20Z4.h7614 #define SPI_RSER_TFFF_RE_MASK 0x2000000u macro
7617 … (((uint32_t)(((uint32_t)(x))<<SPI_RSER_TFFF_RE_SHIFT))&SPI_RSER_TFFF_RE_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MK64F12/
DMK64F12.h22854 #define SPI_RSER_TFFF_RE_MASK (0x2000000U) macro
22860 … (((uint32_t)(((uint32_t)(x)) << SPI_RSER_TFFF_RE_SHIFT)) & SPI_RSER_TFFF_RE_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MK63F12/
DMK63F12.h22808 #define SPI_RSER_TFFF_RE_MASK (0x2000000U) macro
22814 … (((uint32_t)(((uint32_t)(x)) << SPI_RSER_TFFF_RE_SHIFT)) & SPI_RSER_TFFF_RE_MASK)

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