1 /* 2 * Copyright 2024 NXP 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef _S32Z270_DEVICE_H_ 8 #define _S32Z270_DEVICE_H_ 9 10 /* ---------------------------------------------------------------------------- 11 -- CAN Peripheral Access Layer 12 ---------------------------------------------------------------------------- */ 13 14 /*! 15 * @addtogroup CAN_Peripheral_Access_Layer CAN Peripheral Access Layer 16 * @{ 17 */ 18 19 /** CAN - Register Layout Typedef */ 20 typedef struct { 21 __IO uint32_t MCR; /**< Module Configuration Register, offset: 0x0 */ 22 __IO uint32_t CTRL1; /**< Control 1 Register, offset: 0x4 */ 23 __IO uint32_t TIMER; /**< Free Running Timer, offset: 0x8 */ 24 uint8_t RESERVED_0[4]; 25 __IO uint32_t RXMGMASK; /**< Rx Mailboxes Global Mask Register, offset: 0x10 */ 26 __IO uint32_t RX14MASK; /**< Rx 14 Mask Register, offset: 0x14 */ 27 __IO uint32_t RX15MASK; /**< Rx 15 Mask Register, offset: 0x18 */ 28 __IO uint32_t ECR; /**< Error Counter, offset: 0x1C */ 29 __IO uint32_t ESR1; /**< Error and Status 1 Register, offset: 0x20 */ 30 __IO uint32_t IMASK2; /**< Interrupt Masks 2 Register, offset: 0x24 */ 31 __IO uint32_t IMASK1; /**< Interrupt Masks 1 Register, offset: 0x28 */ 32 __IO uint32_t IFLAG2; /**< Interrupt Flags 2 Register, offset: 0x2C */ 33 __IO uint32_t IFLAG1; /**< Interrupt Flags 1 Register, offset: 0x30 */ 34 __IO uint32_t CTRL2; /**< Control 2 Register, offset: 0x34 */ 35 __I uint32_t ESR2; /**< Error and Status 2 Register, offset: 0x38 */ 36 uint8_t RESERVED_1[8]; 37 __I uint32_t CRCR; /**< CRC Register, offset: 0x44 */ 38 __IO uint32_t RXFGMASK; /**< Legacy Rx FIFO Global Mask Register..Rx FIFO Global Mask Register, offset: 0x48 */ 39 __I uint32_t RXFIR; /**< Legacy Rx FIFO Information Register..Rx FIFO Information Register, offset: 0x4C */ 40 __IO uint32_t CBT; /**< CAN Bit Timing Register, offset: 0x50 */ 41 uint8_t RESERVED_2[20]; 42 __IO uint32_t IMASK4; /**< Interrupt Masks 4, offset: 0x68 */ 43 __IO uint32_t IMASK3; /**< Interrupt Masks 3, offset: 0x6C */ 44 __IO uint32_t IFLAG4; /**< Interrupt Flags 4, offset: 0x70 */ 45 __IO uint32_t IFLAG3; /**< Interrupt Flags 3, offset: 0x74 */ 46 uint8_t RESERVED_3[8]; 47 struct 48 { /* offset: 0x80, array step: 0x10 */ 49 __IO uint32_t CS; /**< Message Buffer 0 CS Register..Message Buffer 127 CS Register, array offset: 0x80, array step: 0x10 */ 50 __IO uint32_t ID; /**< Message Buffer 0 ID Register..Message Buffer 127 ID Register, array offset: 0x84, array step: 0x10 */ 51 __IO uint32_t WORD0; /**< Message Buffer 0 WORD0 Register..Message Buffer 127 WORD0 Register, array offset: 0x88, array step: 0x10 */ 52 __IO uint32_t WORD1; /**< Message Buffer 0 WORD1 Register..Message Buffer 127 WORD1 Register, array offset: 0x8C, array step: 0x10 */ 53 } MB[128]; 54 __IO uint32_t RXIMR[128]; /**< Rx Individual Mask Registers, array offset: 0x880, array step: 0x4 */ 55 uint8_t RESERVED_4[96]; 56 __IO uint32_t MECR; /**< Memory Error Control Register, offset: 0xAE0 */ 57 __IO uint32_t ERRIAR; /**< Error Injection Address Register, offset: 0xAE4 */ 58 __IO uint32_t ERRIDPR; /**< Error Injection Data Pattern Register, offset: 0xAE8 */ 59 __IO uint32_t ERRIPPR; /**< Error Injection Parity Pattern Register, offset: 0xAEC */ 60 __I uint32_t RERRAR; /**< Error Report Address Register, offset: 0xAF0 */ 61 __I uint32_t RERRDR; /**< Error Report Data Register, offset: 0xAF4 */ 62 __I uint32_t RERRSYNR; /**< Error Report Syndrome Register, offset: 0xAF8 */ 63 __IO uint32_t ERRSR; /**< Error Status Register, offset: 0xAFC */ 64 uint8_t RESERVED_5[240]; 65 __IO uint32_t EPRS; /**< Enhanced CAN Bit Timing Prescalers, offset: 0xBF0 */ 66 __IO uint32_t ENCBT; /**< Enhanced Nominal CAN Bit Timing, offset: 0xBF4 */ 67 __IO uint32_t EDCBT; /**< Enhanced Data Phase CAN bit Timing, offset: 0xBF8 */ 68 __IO uint32_t ETDC; /**< Enhanced Transceiver Delay Compensation, offset: 0xBFC */ 69 __IO uint32_t FDCTRL; /**< CAN FD Control Register, offset: 0xC00 */ 70 __IO uint32_t FDCBT; /**< CAN FD Bit Timing Register, offset: 0xC04 */ 71 __I uint32_t FDCRC; /**< CAN FD CRC Register, offset: 0xC08 */ 72 __IO uint32_t ERFCR; /**< Enhanced Rx FIFO Control Register, offset: 0xC0C */ 73 __IO uint32_t ERFIER; /**< Enhanced Rx FIFO Interrupt Enable Register, offset: 0xC10 */ 74 __IO uint32_t ERFSR; /**< Enhanced Rx FIFO Status Register, offset: 0xC14 */ 75 uint8_t RESERVED_6[24]; 76 __IO uint32_t HR_TIME_STAMP[128]; /**< High Resolution Time Stamp, array offset: 0xC30, array step: 0x4 */ 77 uint8_t RESERVED_7[8656]; 78 __IO uint32_t ERFFEL[128]; /**< Enhanced Rx FIFO Filter Element, array offset: 0x3000, array step: 0x4 */ 79 } CAN_Type; 80 81 /* ---------------------------------------------------------------------------- 82 -- CAN Register Masks 83 ---------------------------------------------------------------------------- */ 84 85 /*! 86 * @addtogroup CAN_Register_Masks CAN Register Masks 87 * @{ 88 */ 89 90 /*! @name MCR - Module Configuration Register */ 91 /*! @{ */ 92 93 #define CAN_MCR_MAXMB_MASK FLEXCAN_MCR_MAXMB_MASK 94 #define CAN_MCR_MAXMB_SHIFT FLEXCAN_MCR_MAXMB_SHIFT 95 96 #define CAN_MCR_MAXMB(x) FLEXCAN_MCR_MAXMB(x) 97 98 #define CAN_MCR_IDAM_MASK FLEXCAN_MCR_IDAM_MASK 99 #define CAN_MCR_IDAM_SHIFT FLEXCAN_MCR_IDAM_SHIFT 100 101 #define CAN_MCR_IDAM(x) FLEXCAN_MCR_IDAM(x) 102 103 #define CAN_MCR_FDEN_MASK FLEXCAN_MCR_FDEN_MASK 104 #define CAN_MCR_FDEN_SHIFT FLEXCAN_MCR_FDEN_SHIFT 105 106 #define CAN_MCR_FDEN(x) FLEXCAN_MCR_FDEN(x) 107 108 #define CAN_MCR_AEN_MASK FLEXCAN_MCR_AEN_MASK 109 #define CAN_MCR_AEN_SHIFT FLEXCAN_MCR_AEN_SHIFT 110 111 #define CAN_MCR_AEN(x) FLEXCAN_MCR_AEN(x) 112 113 #define CAN_MCR_LPRIOEN_MASK FLEXCAN_MCR_LPRIOEN_MASK 114 #define CAN_MCR_LPRIOEN_SHIFT FLEXCAN_MCR_LPRIOEN_SHIFT 115 116 #define CAN_MCR_LPRIOEN(x) FLEXCAN_MCR_LPRIOEN(x) 117 118 #define CAN_MCR_DMA_MASK FLEXCAN_MCR_DMA_MASK 119 #define CAN_MCR_DMA_SHIFT FLEXCAN_MCR_DMA_SHIFT 120 121 #define CAN_MCR_DMA(x) FLEXCAN_MCR_DMA(x) 122 123 #define CAN_MCR_IRMQ_MASK FLEXCAN_MCR_IRMQ_MASK 124 #define CAN_MCR_IRMQ_SHIFT FLEXCAN_MCR_IRMQ_SHIFT 125 126 #define CAN_MCR_IRMQ(x) FLEXCAN_MCR_IRMQ(x) 127 128 #define CAN_MCR_SRXDIS_MASK FLEXCAN_MCR_SRXDIS_MASK 129 #define CAN_MCR_SRXDIS_SHIFT FLEXCAN_MCR_SRXDIS_SHIFT 130 131 #define CAN_MCR_SRXDIS(x) FLEXCAN_MCR_SRXDIS(x) 132 133 #define CAN_MCR_LPMACK_MASK FLEXCAN_MCR_LPMACK_MASK 134 #define CAN_MCR_LPMACK_SHIFT FLEXCAN_MCR_LPMACK_SHIFT 135 136 #define CAN_MCR_LPMACK(x) FLEXCAN_MCR_LPMACK(x) 137 138 #define CAN_MCR_WRNEN_MASK FLEXCAN_MCR_WRNEN_MASK 139 #define CAN_MCR_WRNEN_SHIFT FLEXCAN_MCR_WRNEN_SHIFT 140 141 #define CAN_MCR_WRNEN(x) FLEXCAN_MCR_WRNEN(x) 142 143 #define CAN_MCR_FRZACK_MASK FLEXCAN_MCR_FRZACK_MASK 144 #define CAN_MCR_FRZACK_SHIFT FLEXCAN_MCR_FRZACK_SHIFT 145 146 #define CAN_MCR_FRZACK(x) FLEXCAN_MCR_FRZACK(x) 147 148 #define CAN_MCR_SOFTRST_MASK FLEXCAN_MCR_SOFTRST_MASK 149 #define CAN_MCR_SOFTRST_SHIFT FLEXCAN_MCR_SOFTRST_SHIFT 150 151 #define CAN_MCR_SOFTRST(x) FLEXCAN_MCR_SOFTRST(x) 152 153 #define CAN_MCR_NOTRDY_MASK FLEXCAN_MCR_NOTRDY_MASK 154 #define CAN_MCR_NOTRDY_SHIFT FLEXCAN_MCR_NOTRDY_SHIFT 155 156 #define CAN_MCR_NOTRDY(x) FLEXCAN_MCR_NOTRDY(x) 157 158 #define CAN_MCR_HALT_MASK FLEXCAN_MCR_HALT_MASK 159 #define CAN_MCR_HALT_SHIFT FLEXCAN_MCR_HALT_SHIFT 160 161 #define CAN_MCR_HALT(x) FLEXCAN_MCR_HALT(x) 162 163 #define CAN_MCR_RFEN_MASK FLEXCAN_MCR_RFEN_MASK 164 #define CAN_MCR_RFEN_SHIFT FLEXCAN_MCR_RFEN_SHIFT 165 166 #define CAN_MCR_RFEN(x) FLEXCAN_MCR_RFEN(x) 167 168 #define CAN_MCR_FRZ_MASK FLEXCAN_MCR_FRZ_MASK 169 #define CAN_MCR_FRZ_SHIFT FLEXCAN_MCR_FRZ_SHIFT 170 171 #define CAN_MCR_FRZ(x) FLEXCAN_MCR_FRZ(x) 172 173 #define CAN_MCR_MDIS_MASK FLEXCAN_MCR_MDIS_MASK 174 #define CAN_MCR_MDIS_SHIFT FLEXCAN_MCR_MDIS_SHIFT 175 176 #define CAN_MCR_MDIS(x) FLEXCAN_MCR_MDIS(x) 177 /*! @} */ 178 179 /*! @name CTRL1 - Control 1 Register */ 180 /*! @{ */ 181 182 #define CAN_CTRL1_PROPSEG_MASK FLEXCAN_CTRL1_PROPSEG_MASK 183 #define CAN_CTRL1_PROPSEG_SHIFT FLEXCAN_CTRL1_PROPSEG_SHIFT 184 185 #define CAN_CTRL1_PROPSEG(x) FLEXCAN_CTRL1_PROPSEG(x) 186 187 #define CAN_CTRL1_LOM_MASK FLEXCAN_CTRL1_LOM_MASK 188 #define CAN_CTRL1_LOM_SHIFT FLEXCAN_CTRL1_LOM_SHIFT 189 190 #define CAN_CTRL1_LOM(x) FLEXCAN_CTRL1_LOM(x) 191 192 #define CAN_CTRL1_LBUF_MASK FLEXCAN_CTRL1_LBUF_MASK 193 #define CAN_CTRL1_LBUF_SHIFT FLEXCAN_CTRL1_LBUF_SHIFT 194 195 #define CAN_CTRL1_LBUF(x) FLEXCAN_CTRL1_LBUF(x) 196 197 #define CAN_CTRL1_TSYN_MASK FLEXCAN_CTRL1_TSYN_MASK 198 #define CAN_CTRL1_TSYN_SHIFT FLEXCAN_CTRL1_TSYN_SHIFT 199 200 #define CAN_CTRL1_TSYN(x) FLEXCAN_CTRL1_TSYN(x) 201 202 #define CAN_CTRL1_BOFFREC_MASK FLEXCAN_CTRL1_BOFFREC_MASK 203 #define CAN_CTRL1_BOFFREC_SHIFT FLEXCAN_CTRL1_BOFFREC_SHIFT 204 205 #define CAN_CTRL1_BOFFREC(x) FLEXCAN_CTRL1_BOFFREC(x) 206 207 #define CAN_CTRL1_SMP_MASK FLEXCAN_CTRL1_SMP_MASK 208 #define CAN_CTRL1_SMP_SHIFT FLEXCAN_CTRL1_SMP_SHIFT 209 210 #define CAN_CTRL1_SMP(x) FLEXCAN_CTRL1_SMP(x) 211 212 #define CAN_CTRL1_RWRNMSK_MASK FLEXCAN_CTRL1_RWRNMSK_MASK 213 #define CAN_CTRL1_RWRNMSK_SHIFT FLEXCAN_CTRL1_RWRNMSK_SHIFT 214 215 #define CAN_CTRL1_RWRNMSK(x) FLEXCAN_CTRL1_RWRNMSK(x) 216 217 #define CAN_CTRL1_TWRNMSK_MASK FLEXCAN_CTRL1_TWRNMSK_MASK 218 #define CAN_CTRL1_TWRNMSK_SHIFT FLEXCAN_CTRL1_TWRNMSK_SHIFT 219 220 #define CAN_CTRL1_TWRNMSK(x) FLEXCAN_CTRL1_TWRNMSK(x) 221 222 #define CAN_CTRL1_LPB_MASK FLEXCAN_CTRL1_LPB_MASK 223 #define CAN_CTRL1_LPB_SHIFT FLEXCAN_CTRL1_LPB_SHIFT 224 225 #define CAN_CTRL1_LPB(x) FLEXCAN_CTRL1_LPB(x) 226 227 #define CAN_CTRL1_ERRMSK_MASK FLEXCAN_CTRL1_ERRMSK_MASK 228 #define CAN_CTRL1_ERRMSK_SHIFT FLEXCAN_CTRL1_ERRMSK_SHIFT 229 230 #define CAN_CTRL1_ERRMSK(x) FLEXCAN_CTRL1_ERRMSK(x) 231 232 #define CAN_CTRL1_BOFFMSK_MASK FLEXCAN_CTRL1_BOFFMSK_MASK 233 #define CAN_CTRL1_BOFFMSK_SHIFT FLEXCAN_CTRL1_BOFFMSK_SHIFT 234 235 #define CAN_CTRL1_BOFFMSK(x) FLEXCAN_CTRL1_BOFFMSK(x) 236 237 #define CAN_CTRL1_PSEG2_MASK FLEXCAN_CTRL1_PSEG2_MASK 238 #define CAN_CTRL1_PSEG2_SHIFT FLEXCAN_CTRL1_PSEG2_SHIFT 239 240 #define CAN_CTRL1_PSEG2(x) FLEXCAN_CTRL1_PSEG2(x) 241 242 #define CAN_CTRL1_PSEG1_MASK FLEXCAN_CTRL1_PSEG1_MASK 243 #define CAN_CTRL1_PSEG1_SHIFT FLEXCAN_CTRL1_PSEG1_SHIFT 244 245 #define CAN_CTRL1_PSEG1(x) FLEXCAN_CTRL1_PSEG1(x) 246 247 #define CAN_CTRL1_RJW_MASK FLEXCAN_CTRL1_RJW_MASK 248 #define CAN_CTRL1_RJW_SHIFT FLEXCAN_CTRL1_RJW_SHIFT 249 250 #define CAN_CTRL1_RJW(x) FLEXCAN_CTRL1_RJW(x) 251 252 #define CAN_CTRL1_PRESDIV_MASK FLEXCAN_CTRL1_PRESDIV_MASK 253 #define CAN_CTRL1_PRESDIV_SHIFT FLEXCAN_CTRL1_PRESDIV_SHIFT 254 255 #define CAN_CTRL1_PRESDIV(x) FLEXCAN_CTRL1_PRESDIV(x) 256 /*! @} */ 257 258 /*! @name TIMER - Free Running Timer */ 259 /*! @{ */ 260 261 #define CAN_TIMER_TIMER_MASK FLEXCAN_TIMER_TIMER_MASK 262 #define CAN_TIMER_TIMER_SHIFT FLEXCAN_TIMER_TIMER_SHIFT 263 264 #define CAN_TIMER_TIMER(x) FLEXCAN_TIMER_TIMER(x) 265 /*! @} */ 266 267 /*! @name RXMGMASK - Rx Mailboxes Global Mask Register */ 268 /*! @{ */ 269 270 #define CAN_RXMGMASK_MG_MASK FLEXCAN_RXMGMASK_MG_MASK 271 #define CAN_RXMGMASK_MG_SHIFT FLEXCAN_RXMGMASK_MG_SHIFT 272 273 #define CAN_RXMGMASK_MG(x) FLEXCAN_RXMGMASK_MG(x) 274 /*! @} */ 275 276 /*! @name RX14MASK - Rx 14 Mask Register */ 277 /*! @{ */ 278 279 #define CAN_RX14MASK_RX14M_MASK FLEXCAN_RX14MASK_RX14M_MASK 280 #define CAN_RX14MASK_RX14M_SHIFT FLEXCAN_RX14MASK_RX14M_SHIFT 281 282 #define CAN_RX14MASK_RX14M(x) FLEXCAN_RX14MASK_RX14M(x) 283 /*! @} */ 284 285 /*! @name RX15MASK - Rx 15 Mask Register */ 286 /*! @{ */ 287 288 #define CAN_RX15MASK_RX15M_MASK FLEXCAN_RX15MASK_RX15M_MASK 289 #define CAN_RX15MASK_RX15M_SHIFT FLEXCAN_RX15MASK_RX15M_SHIFT 290 291 #define CAN_RX15MASK_RX15M(x) FLEXCAN_RX15MASK_RX15M(x) 292 /*! @} */ 293 294 /*! @name ECR - Error Counter */ 295 /*! @{ */ 296 297 #define CAN_ECR_TXERRCNT_MASK FLEXCAN_ECR_TXERRCNT_MASK 298 #define CAN_ECR_TXERRCNT_SHIFT FLEXCAN_ECR_TXERRCNT_SHIFT 299 300 #define CAN_ECR_TXERRCNT(x) FLEXCAN_ECR_TXERRCNT(x) 301 302 #define CAN_ECR_RXERRCNT_MASK FLEXCAN_ECR_RXERRCNT_MASK 303 #define CAN_ECR_RXERRCNT_SHIFT FLEXCAN_ECR_RXERRCNT_SHIFT 304 305 #define CAN_ECR_RXERRCNT(x) FLEXCAN_ECR_RXERRCNT(x) 306 307 #define CAN_ECR_TXERRCNT_FAST_MASK FLEXCAN_ECR_TXERRCNT_FAST_MASK 308 #define CAN_ECR_TXERRCNT_FAST_SHIFT FLEXCAN_ECR_TXERRCNT_FAST_SHIFT 309 310 #define CAN_ECR_TXERRCNT_FAST(x) FLEXCAN_ECR_TXERRCNT_FAST(x) 311 312 #define CAN_ECR_RXERRCNT_FAST_MASK FLEXCAN_ECR_RXERRCNT_FAST_MASK 313 #define CAN_ECR_RXERRCNT_FAST_SHIFT FLEXCAN_ECR_RXERRCNT_FAST_SHIFT 314 315 #define CAN_ECR_RXERRCNT_FAST(x) FLEXCAN_ECR_RXERRCNT_FAST(x) 316 /*! @} */ 317 318 /*! @name ESR1 - Error and Status 1 Register */ 319 /*! @{ */ 320 321 #define CAN_ESR1_ERRINT_MASK FLEXCAN_ESR1_ERRINT_MASK 322 #define CAN_ESR1_ERRINT_SHIFT FLEXCAN_ESR1_ERRINT_SHIFT 323 324 #define CAN_ESR1_ERRINT(x) FLEXCAN_ESR1_ERRINT(x) 325 326 #define CAN_ESR1_BOFFINT_MASK FLEXCAN_ESR1_BOFFINT_MASK 327 #define CAN_ESR1_BOFFINT_SHIFT FLEXCAN_ESR1_BOFFINT_SHIFT 328 329 #define CAN_ESR1_BOFFINT(x) FLEXCAN_ESR1_BOFFINT(x) 330 331 #define CAN_ESR1_RX_MASK FLEXCAN_ESR1_RX_MASK 332 #define CAN_ESR1_RX_SHIFT FLEXCAN_ESR1_RX_SHIFT 333 334 #define CAN_ESR1_RX(x) FLEXCAN_ESR1_RX(x) 335 336 #define CAN_ESR1_FLTCONF_MASK FLEXCAN_ESR1_FLTCONF_MASK 337 #define CAN_ESR1_FLTCONF_SHIFT FLEXCAN_ESR1_FLTCONF_SHIFT 338 339 #define CAN_ESR1_FLTCONF(x) FLEXCAN_ESR1_FLTCONF(x) 340 341 #define CAN_ESR1_TX_MASK FLEXCAN_ESR1_TX_MASK 342 #define CAN_ESR1_TX_SHIFT FLEXCAN_ESR1_TX_SHIFT 343 344 #define CAN_ESR1_TX(x) FLEXCAN_ESR1_TX(x) 345 346 #define CAN_ESR1_IDLE_MASK FLEXCAN_ESR1_IDLE_MASK 347 #define CAN_ESR1_IDLE_SHIFT FLEXCAN_ESR1_IDLE_SHIFT 348 349 #define CAN_ESR1_IDLE(x) FLEXCAN_ESR1_IDLE(x) 350 351 #define CAN_ESR1_RXWRN_MASK FLEXCAN_ESR1_RXWRN_MASK 352 #define CAN_ESR1_RXWRN_SHIFT FLEXCAN_ESR1_RXWRN_SHIFT 353 354 #define CAN_ESR1_RXWRN(x) FLEXCAN_ESR1_RXWRN(x) 355 356 #define CAN_ESR1_TXWRN_MASK FLEXCAN_ESR1_TXWRN_MASK 357 #define CAN_ESR1_TXWRN_SHIFT FLEXCAN_ESR1_TXWRN_SHIFT 358 359 #define CAN_ESR1_TXWRN(x) FLEXCAN_ESR1_TXWRN(x) 360 361 #define CAN_ESR1_STFERR_MASK FLEXCAN_ESR1_STFERR_MASK 362 #define CAN_ESR1_STFERR_SHIFT FLEXCAN_ESR1_STFERR_SHIFT 363 364 #define CAN_ESR1_STFERR(x) FLEXCAN_ESR1_STFERR(x) 365 366 #define CAN_ESR1_FRMERR_MASK FLEXCAN_ESR1_FRMERR_MASK 367 #define CAN_ESR1_FRMERR_SHIFT FLEXCAN_ESR1_FRMERR_SHIFT 368 369 #define CAN_ESR1_FRMERR(x) FLEXCAN_ESR1_FRMERR(x) 370 371 #define CAN_ESR1_CRCERR_MASK FLEXCAN_ESR1_CRCERR_MASK 372 #define CAN_ESR1_CRCERR_SHIFT FLEXCAN_ESR1_CRCERR_SHIFT 373 374 #define CAN_ESR1_CRCERR(x) FLEXCAN_ESR1_CRCERR(x) 375 376 #define CAN_ESR1_ACKERR_MASK FLEXCAN_ESR1_ACKERR_MASK 377 #define CAN_ESR1_ACKERR_SHIFT FLEXCAN_ESR1_ACKERR_SHIFT 378 379 #define CAN_ESR1_ACKERR(x) FLEXCAN_ESR1_ACKERR(x) 380 381 #define CAN_ESR1_BIT0ERR_MASK FLEXCAN_ESR1_BIT0ERR_MASK 382 #define CAN_ESR1_BIT0ERR_SHIFT FLEXCAN_ESR1_BIT0ERR_SHIFT 383 384 #define CAN_ESR1_BIT0ERR(x) FLEXCAN_ESR1_BIT0ERR(x) 385 386 #define CAN_ESR1_BIT1ERR_MASK FLEXCAN_ESR1_BIT1ERR_MASK 387 #define CAN_ESR1_BIT1ERR_SHIFT FLEXCAN_ESR1_BIT1ERR_SHIFT 388 389 #define CAN_ESR1_BIT1ERR(x) FLEXCAN_ESR1_BIT1ERR(x) 390 391 #define CAN_ESR1_RWRNINT_MASK FLEXCAN_ESR1_RWRNINT_MASK 392 #define CAN_ESR1_RWRNINT_SHIFT FLEXCAN_ESR1_RWRNINT_SHIFT 393 394 #define CAN_ESR1_RWRNINT(x) FLEXCAN_ESR1_RWRNINT(x) 395 396 #define CAN_ESR1_TWRNINT_MASK FLEXCAN_ESR1_TWRNINT_MASK 397 #define CAN_ESR1_TWRNINT_SHIFT FLEXCAN_ESR1_TWRNINT_SHIFT 398 399 #define CAN_ESR1_TWRNINT(x) FLEXCAN_ESR1_TWRNINT(x) 400 401 #define CAN_ESR1_SYNCH_MASK FLEXCAN_ESR1_SYNCH_MASK 402 #define CAN_ESR1_SYNCH_SHIFT FLEXCAN_ESR1_SYNCH_SHIFT 403 404 #define CAN_ESR1_SYNCH(x) FLEXCAN_ESR1_SYNCH(x) 405 406 #define CAN_ESR1_BOFFDONEINT_MASK FLEXCAN_ESR1_BOFFDONEINT_MASK 407 #define CAN_ESR1_BOFFDONEINT_SHIFT FLEXCAN_ESR1_BOFFDONEINT_SHIFT 408 409 #define CAN_ESR1_BOFFDONEINT(x) FLEXCAN_ESR1_BOFFDONEINT(x) 410 411 #define CAN_ESR1_ERRINT_FAST_MASK FLEXCAN_ESR1_ERRINT_FAST_MASK 412 #define CAN_ESR1_ERRINT_FAST_SHIFT FLEXCAN_ESR1_ERRINT_FAST_SHIFT 413 414 #define CAN_ESR1_ERRINT_FAST(x) FLEXCAN_ESR1_ERRINT_FAST(x) 415 416 #define CAN_ESR1_ERROVR_MASK FLEXCAN_ESR1_ERROVR_MASK 417 #define CAN_ESR1_ERROVR_SHIFT FLEXCAN_ESR1_ERROVR_SHIFT 418 419 #define CAN_ESR1_ERROVR(x) FLEXCAN_ESR1_ERROVR(x) 420 421 #define CAN_ESR1_STFERR_FAST_MASK FLEXCAN_ESR1_STFERR_FAST_MASK 422 #define CAN_ESR1_STFERR_FAST_SHIFT FLEXCAN_ESR1_STFERR_FAST_SHIFT 423 424 #define CAN_ESR1_STFERR_FAST(x) FLEXCAN_ESR1_STFERR_FAST(x) 425 426 #define CAN_ESR1_FRMERR_FAST_MASK FLEXCAN_ESR1_FRMERR_FAST_MASK 427 #define CAN_ESR1_FRMERR_FAST_SHIFT FLEXCAN_ESR1_FRMERR_FAST_SHIFT 428 429 #define CAN_ESR1_FRMERR_FAST(x) FLEXCAN_ESR1_FRMERR_FAST(x) 430 431 #define CAN_ESR1_CRCERR_FAST_MASK FLEXCAN_ESR1_CRCERR_FAST_MASK 432 #define CAN_ESR1_CRCERR_FAST_SHIFT FLEXCAN_ESR1_CRCERR_FAST_SHIFT 433 434 #define CAN_ESR1_CRCERR_FAST(x) FLEXCAN_ESR1_CRCERR_FAST(x) 435 436 #define CAN_ESR1_BIT0ERR_FAST_MASK FLEXCAN_ESR1_BIT0ERR_FAST_MASK 437 #define CAN_ESR1_BIT0ERR_FAST_SHIFT FLEXCAN_ESR1_BIT0ERR_FAST_SHIFT 438 439 #define CAN_ESR1_BIT0ERR_FAST(x) FLEXCAN_ESR1_BIT0ERR_FAST(x) 440 441 #define CAN_ESR1_BIT1ERR_FAST_MASK FLEXCAN_ESR1_BIT1ERR_FAST_MASK 442 #define CAN_ESR1_BIT1ERR_FAST_SHIFT FLEXCAN_ESR1_BIT1ERR_FAST_SHIFT 443 444 #define CAN_ESR1_BIT1ERR_FAST(x) FLEXCAN_ESR1_BIT1ERR_FAST(x) 445 /*! @} */ 446 447 /*! @name IMASK2 - Interrupt Masks 2 Register */ 448 /*! @{ */ 449 450 #define CAN_IMASK2_BUF63TO32M_MASK FLEXCAN_IMASK2_BUF63TO32M_MASK 451 #define CAN_IMASK2_BUF63TO32M_SHIFT FLEXCAN_IMASK2_BUF63TO32M_SHIFT 452 453 #define CAN_IMASK2_BUF63TO32M(x) FLEXCAN_IMASK2_BUF63TO32M(x) 454 /*! @} */ 455 456 /*! @name IMASK1 - Interrupt Masks 1 Register */ 457 /*! @{ */ 458 459 #define CAN_IMASK1_BUF31TO0M_MASK FLEXCAN_IMASK1_BUF31TO0M_MASK 460 #define CAN_IMASK1_BUF31TO0M_SHIFT FLEXCAN_IMASK1_BUF31TO0M_SHIFT 461 462 #define CAN_IMASK1_BUF31TO0M(x) FLEXCAN_IMASK1_BUF31TO0M(x) 463 /*! @} */ 464 465 /*! @name IFLAG2 - Interrupt Flags 2 Register */ 466 /*! @{ */ 467 468 #define CAN_IFLAG2_BUF63TO32I_MASK FLEXCAN_IFLAG2_BUF63TO32I_MASK 469 #define CAN_IFLAG2_BUF63TO32I_SHIFT FLEXCAN_IFLAG2_BUF63TO32I_SHIFT 470 471 #define CAN_IFLAG2_BUF63TO32I(x) FLEXCAN_IFLAG2_BUF63TO32I(x) 472 /*! @} */ 473 474 /*! @name IFLAG1 - Interrupt Flags 1 Register */ 475 /*! @{ */ 476 477 #define CAN_IFLAG1_BUF0I_MASK FLEXCAN_IFLAG1_BUF0I_MASK 478 #define CAN_IFLAG1_BUF0I_SHIFT FLEXCAN_IFLAG1_BUF0I_SHIFT 479 480 #define CAN_IFLAG1_BUF0I(x) FLEXCAN_IFLAG1_BUF0I(x) 481 482 #define CAN_IFLAG1_BUF4TO1I_MASK FLEXCAN_IFLAG1_BUF4TO1I_MASK 483 #define CAN_IFLAG1_BUF4TO1I_SHIFT FLEXCAN_IFLAG1_BUF4TO1I_SHIFT 484 485 #define CAN_IFLAG1_BUF4TO1I(x) FLEXCAN_IFLAG1_BUF4TO1I(x) 486 487 #define CAN_IFLAG1_BUF5I_MASK FLEXCAN_IFLAG1_BUF4TO1I_MASK 488 #define CAN_IFLAG1_BUF5I_SHIFT FLEXCAN_IFLAG1_BUF4TO1I_SHIFT 489 490 #define CAN_IFLAG1_BUF5I(x) FLEXCAN_IFLAG1_BUF5I(x) 491 492 #define CAN_IFLAG1_BUF6I_MASK FLEXCAN_IFLAG1_BUF5I_MASK 493 #define CAN_IFLAG1_BUF6I_SHIFT FLEXCAN_IFLAG1_BUF5I_SHIFT 494 495 #define CAN_IFLAG1_BUF6I(x) FLEXCAN_IFLAG1_BUF6I(x) 496 497 #define CAN_IFLAG1_BUF7I_MASK FLEXCAN_IFLAG1_BUF6I_MASK 498 #define CAN_IFLAG1_BUF7I_SHIFT FLEXCAN_IFLAG1_BUF6I_SHIFT 499 500 #define CAN_IFLAG1_BUF7I(x) FLEXCAN_IFLAG1_BUF7I(x) 501 502 #define CAN_IFLAG1_BUF31TO8I_MASK FLEXCAN_IFLAG1_BUF31TO8I_MASK 503 #define CAN_IFLAG1_BUF31TO8I_SHIFT FLEXCAN_IFLAG1_BUF31TO8I_SHIFT 504 505 #define CAN_IFLAG1_BUF31TO8I(x) FLEXCAN_IFLAG1_BUF31TO8I(x) 506 /*! @} */ 507 508 /*! @name CTRL2 - Control 2 Register */ 509 /*! @{ */ 510 511 #define CAN_CTRL2_TSTAMPCAP_MASK FLEXCAN_CTRL2_TSTAMPCAP_MASK 512 #define CAN_CTRL2_TSTAMPCAP_SHIFT FLEXCAN_CTRL2_TSTAMPCAP_SHIFT 513 514 #define CAN_CTRL2_TSTAMPCAP(x) FLEXCAN_CTRL2_TSTAMPCAP(x) 515 516 #define CAN_CTRL2_MBTSBASE_MASK FLEXCAN_CTRL2_MBTSBASE_MASK 517 #define CAN_CTRL2_MBTSBASE_SHIFT FLEXCAN_CTRL2_MBTSBASE_SHIFT 518 519 #define CAN_CTRL2_MBTSBASE(x) FLEXCAN_CTRL2_MBTSBASE(x) 520 521 #define CAN_CTRL2_EDFLTDIS_MASK FLEXCAN_CTRL2_EDFLTDIS_MASK 522 #define CAN_CTRL2_EDFLTDIS_SHIFT FLEXCAN_CTRL2_EDFLTDIS_SHIFT 523 524 #define CAN_CTRL2_EDFLTDIS(x) FLEXCAN_CTRL2_EDFLTDIS(x) 525 526 #define CAN_CTRL2_ISOCANFDEN_MASK FLEXCAN_CTRL2_ISOCANFDEN_MASK 527 #define CAN_CTRL2_ISOCANFDEN_SHIFT FLEXCAN_CTRL2_ISOCANFDEN_SHIFT 528 529 #define CAN_CTRL2_ISOCANFDEN(x) FLEXCAN_CTRL2_ISOCANFDEN(x) 530 531 #define CAN_CTRL2_BTE_MASK FLEXCAN_CTRL2_BTE_MASK 532 #define CAN_CTRL2_BTE_SHIFT FLEXCAN_CTRL2_BTE_SHIFT 533 534 #define CAN_CTRL2_BTE(x) FLEXCAN_CTRL2_BTE(x) 535 536 #define CAN_CTRL2_PREXCEN_MASK FLEXCAN_CTRL2_PREXCEN_MASK 537 #define CAN_CTRL2_PREXCEN_SHIFT FLEXCAN_CTRL2_PREXCEN_SHIFT 538 539 #define CAN_CTRL2_PREXCEN(x) FLEXCAN_CTRL2_PREXCEN(x) 540 541 #define CAN_CTRL2_TIMER_SRC_MASK FLEXCAN_CTRL2_TIMER_SRC_MASK 542 #define CAN_CTRL2_TIMER_SRC_SHIFT FLEXCAN_CTRL2_TIMER_SRC_SHIFT 543 544 #define CAN_CTRL2_TIMER_SRC(x) FLEXCAN_CTRL2_TIMER_SRC(x) 545 546 #define CAN_CTRL2_EACEN_MASK FLEXCAN_CTRL2_EACEN_MASK 547 #define CAN_CTRL2_EACEN_SHIFT FLEXCAN_CTRL2_EACEN_SHIFT 548 549 #define CAN_CTRL2_EACEN(x) FLEXCAN_CTRL2_EACEN(x) 550 551 #define CAN_CTRL2_RRS_MASK FLEXCAN_CTRL2_RRS_MASK 552 #define CAN_CTRL2_RRS_SHIFT FLEXCAN_CTRL2_RRS_SHIFT 553 554 #define CAN_CTRL2_RRS(x) FLEXCAN_CTRL2_RRS(x) 555 556 #define CAN_CTRL2_MRP_MASK FLEXCAN_CTRL2_MRP_MASK 557 #define CAN_CTRL2_MRP_SHIFT FLEXCAN_CTRL2_MRP_SHIFT 558 559 #define CAN_CTRL2_MRP(x) FLEXCAN_CTRL2_MRP(x) 560 561 #define CAN_CTRL2_TASD_MASK FLEXCAN_CTRL2_TASD_MASK 562 #define CAN_CTRL2_TASD_SHIFT FLEXCAN_CTRL2_TASD_SHIFT 563 564 #define CAN_CTRL2_TASD(x) FLEXCAN_CTRL2_TASD(x) 565 566 #define CAN_CTRL2_RFFN_MASK FLEXCAN_CTRL2_RFFN_MASK 567 #define CAN_CTRL2_RFFN_SHIFT FLEXCAN_CTRL2_RFFN_SHIFT 568 569 #define CAN_CTRL2_RFFN(x) FLEXCAN_CTRL2_RFFN(x) 570 571 #define CAN_CTRL2_WRMFRZ_MASK FLEXCAN_CTRL2_WRMFRZ_MASK 572 #define CAN_CTRL2_WRMFRZ_SHIFT FLEXCAN_CTRL2_WRMFRZ_SHIFT 573 574 #define CAN_CTRL2_WRMFRZ(x) FLEXCAN_CTRL2_WRMFRZ(x) 575 576 #define CAN_CTRL2_ECRWRE_MASK FLEXCAN_CTRL2_ECRWRE_MASK 577 #define CAN_CTRL2_ECRWRE_SHIFT FLEXCAN_CTRL2_ECRWRE_SHIFT 578 579 #define CAN_CTRL2_ECRWRE(x) FLEXCAN_CTRL2_ECRWRE(x) 580 581 #define CAN_CTRL2_BOFFDONEMSK_MASK FLEXCAN_CTRL2_BOFFDONEMSK_MASK 582 #define CAN_CTRL2_BOFFDONEMSK_SHIFT FLEXCAN_CTRL2_BOFFDONEMSK_SHIFT 583 584 #define CAN_CTRL2_BOFFDONEMSK(x) FLEXCAN_CTRL2_BOFFDONEMSK(x) 585 586 #define CAN_CTRL2_ERRMSK_FAST_MASK FLEXCAN_CTRL2_ERRMSK_FAST_MASK 587 #define CAN_CTRL2_ERRMSK_FAST_SHIFT FLEXCAN_CTRL2_ERRMSK_FAST_SHIFT 588 589 #define CAN_CTRL2_ERRMSK_FAST(x) FLEXCAN_CTRL2_ERRMSK_FAST(x) 590 /*! @} */ 591 592 /*! @name ESR2 - Error and Status 2 Register */ 593 /*! @{ */ 594 595 #define CAN_ESR2_IMB_MASK FLEXCAN_ESR2_IMB_MASK 596 #define CAN_ESR2_IMB_SHIFT FLEXCAN_ESR2_IMB_SHIFT 597 598 #define CAN_ESR2_IMB(x) FLEXCAN_ESR2_IMB(x) 599 600 #define CAN_ESR2_VPS_MASK FLEXCAN_ESR2_VPS_MASK 601 #define CAN_ESR2_VPS_SHIFT FLEXCAN_ESR2_VPS_SHIFT 602 603 #define CAN_ESR2_VPS(x) FLEXCAN_ESR2_VPS(x) 604 605 #define CAN_ESR2_LPTM_MASK FLEXCAN_ESR2_LPTM_MASK 606 #define CAN_ESR2_LPTM_SHIFT FLEXCAN_ESR2_LPTM_SHIFT 607 /*! LPTM - Lowest Priority Tx Mailbox 608 */ 609 #define CAN_ESR2_LPTM(x) FLEXCAN_ESR2_LPTM(x) 610 /*! @} */ 611 612 /*! @name CRCR - CRC Register */ 613 /*! @{ */ 614 615 #define CAN_CRCR_TXCRC_MASK FLEXCAN_CRCR_TXCRC_MASK 616 #define CAN_CRCR_TXCRC_SHIFT FLEXCAN_CRCR_TXCRC_SHIFT 617 618 #define CAN_CRCR_TXCRC(x) FLEXCAN_CRCR_TXCRC(x) 619 620 #define CAN_CRCR_MBCRC_MASK FLEXCAN_CRCR_MBCRC_MASK 621 #define CAN_CRCR_MBCRC_SHIFT FLEXCAN_CRCR_MBCRC_SHIFT 622 623 #define CAN_CRCR_MBCRC(x) FLEXCAN_CRCR_MBCRC(x) 624 /*! @} */ 625 626 /*! @name RXFGMASK - Legacy Rx FIFO Global Mask Register */ 627 /*! @{ */ 628 629 #define CAN_RXFGMASK_FGM_MASK FLEXCAN_RXFGMASK_FGM_MASK 630 #define CAN_RXFGMASK_FGM_SHIFT FLEXCAN_RXFGMASK_FGM_SHIFT 631 632 #define CAN_RXFGMASK_FGM(x) FLEXCAN_RXFGMASK_FGM(x) 633 /*! @} */ 634 635 /*! @name RXFIR - Legacy Rx FIFO Information Register */ 636 /*! @{ */ 637 638 #define CAN_RXFIR_IDHIT_MASK FLEXCAN_RXFIR_IDHIT_MASK 639 #define CAN_RXFIR_IDHIT_SHIFT FLEXCAN_RXFIR_IDHIT_SHIFT 640 641 #define CAN_RXFIR_IDHIT(x) FLEXCAN_RXFIR_IDHIT(x) 642 /*! @} */ 643 644 /*! @name CBT - CAN Bit Timing Register */ 645 /*! @{ */ 646 647 #define CAN_CBT_EPSEG2_MASK FLEXCAN_CBT_EPSEG2_MASK 648 #define CAN_CBT_EPSEG2_SHIFT FLEXCAN_CBT_EPSEG2_SHIFT 649 650 #define CAN_CBT_EPSEG2(x) FLEXCAN_CBT_EPSEG2(x) 651 652 #define CAN_CBT_EPSEG1_MASK FLEXCAN_CBT_EPSEG1_MASK 653 #define CAN_CBT_EPSEG1_SHIFT FLEXCAN_CBT_EPSEG1_SHIFT 654 655 #define CAN_CBT_EPSEG1(x) FLEXCAN_CBT_EPSEG1(x) 656 657 #define CAN_CBT_EPROPSEG_MASK FLEXCAN_CBT_EPROPSEG_MASK 658 #define CAN_CBT_EPROPSEG_SHIFT FLEXCAN_CBT_EPROPSEG_SHIFT 659 660 #define CAN_CBT_EPROPSEG(x) FLEXCAN_CBT_EPROPSEG(x) 661 662 #define CAN_CBT_ERJW_MASK FLEXCAN_CBT_ERJW_MASK 663 #define CAN_CBT_ERJW_SHIFT FLEXCAN_CBT_ERJW_SHIFT 664 665 #define CAN_CBT_ERJW(x) FLEXCAN_CBT_ERJW(x) 666 667 #define CAN_CBT_EPRESDIV_MASK FLEXCAN_CBT_EPRESDIV_MASK 668 #define CAN_CBT_EPRESDIV_SHIFT FLEXCAN_CBT_EPRESDIV_SHIFT 669 670 #define CAN_CBT_EPRESDIV(x) FLEXCAN_CBT_EPRESDIV(x) 671 672 #define CAN_CBT_BTF_MASK FLEXCAN_CBT_BTF_MASK 673 #define CAN_CBT_BTF_SHIFT FLEXCAN_CBT_BTF_SHIFT 674 675 #define CAN_CBT_BTF(x) FLEXCAN_CBT_BTF(x) 676 /*! @} */ 677 678 /*! @name IMASK3 - Interrupt Masks 3 Register */ 679 /*! @{ */ 680 681 #define CAN_IMASK3_BUF95TO64M_MASK FLEXCAN_IMASK3_BUF95TO64M_MASK 682 #define CAN_IMASK3_BUF95TO64M_SHIFT FLEXCAN_IMASK3_BUF95TO64M_SHIFT 683 684 #define CAN_IMASK3_BUF95TO64M(x) FLEXCAN_IMASK3_BUF95TO64M(x) 685 /*! @} */ 686 687 /*! @name IFLAG3 - Interrupt Flags 3 Register */ 688 /*! @{ */ 689 690 #define CAN_IFLAG3_BUF95TO64_MASK FLEXCAN_IFLAG3_BUF95TO64_MASK 691 #define CAN_IFLAG3_BUF95TO64_SHIFT FLEXCAN_IFLAG3_BUF95TO64_SHIFT 692 693 /*! @name IMASK4 - Interrupt Masks 4 Register */ 694 /*! @{ */ 695 696 #define CAN_IMASK4_BUF127TO96M_MASK FLEXCAN_IMASK4_BUF127TO96M_MASK 697 #define CAN_IMASK4_BUF127TO96M_SHIFT FLEXCAN_IMASK4_BUF127TO96M_SHIFT 698 699 #define CAN_IMASK4_BUF127TO96M(x) FLEXCAN_IMASK4_BUF127TO96M(x) 700 /*! @} */ 701 702 /*! @name IFLAG4 - Interrupt Flags 4 Register */ 703 /*! @{ */ 704 705 #define CAN_IFLAG4_BUF127TO96_MASK FLEXCAN_IFLAG4_BUF127TO96_MASK 706 #define CAN_IFLAG4_BUF127TO96_SHIFT FLEXCAN_IFLAG4_BUF127TO96_SHIFT 707 708 #define CAN_IFLAG4_BUF127TO96M(x) FLEXCAN_IFLAG4_BUF127TO96M(x) 709 /*! @} */ 710 711 /* The count of CAN_CS */ 712 #define CAN_CS_COUNT_MB8B (96U) 713 714 /* The count of CAN_ID */ 715 #define CAN_ID_COUNT_MB8B (96U) 716 717 /* The count of CAN_WORD */ 718 #define CAN_WORD_COUNT_MB8B (96U) 719 720 /* The count of CAN_WORD */ 721 #define CAN_WORD_COUNT_MB8B2 (2U) 722 723 /* The count of CAN_CS */ 724 #define CAN_CS_COUNT_MB16B (63U) 725 726 /* The count of CAN_ID */ 727 #define CAN_ID_COUNT_MB16B (63U) 728 729 /* The count of CAN_WORD */ 730 #define CAN_WORD_COUNT_MB16B (63U) 731 732 /* The count of CAN_WORD */ 733 #define CAN_WORD_COUNT_MB16B2 (4U) 734 735 /* The count of CAN_CS */ 736 #define CAN_CS_COUNT_MB32B (36U) 737 738 /* The count of CAN_ID */ 739 #define CAN_ID_COUNT_MB32B (36U) 740 741 /* The count of CAN_WORD */ 742 #define CAN_WORD_COUNT_MB32B (36U) 743 744 /* The count of CAN_WORD */ 745 #define CAN_WORD_COUNT_MB32B2 (8U) 746 747 /*! @name CS - Message Buffer 0 CS Register..Message Buffer 20 CS Register */ 748 /*! @{ */ 749 750 #define CAN_CS_TIME_STAMP_MASK (0xFFFFU) 751 #define CAN_CS_TIME_STAMP_SHIFT (0U) 752 /*! TIME_STAMP - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running 753 * Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field 754 * appears on the CAN bus. 755 */ 756 #define CAN_CS_TIME_STAMP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_TIME_STAMP_SHIFT)) & CAN_CS_TIME_STAMP_MASK) 757 758 #define CAN_CS_DLC_MASK (0xF0000U) 759 #define CAN_CS_DLC_SHIFT (16U) 760 /*! DLC - Length of the data to be stored/transmitted. 761 */ 762 #define CAN_CS_DLC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_DLC_SHIFT)) & CAN_CS_DLC_MASK) 763 764 #define CAN_CS_RTR_MASK (0x100000U) 765 #define CAN_CS_RTR_SHIFT (20U) 766 /*! RTR - Remote Transmission Request. One/zero for remote/data frame. 767 */ 768 #define CAN_CS_RTR(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_RTR_SHIFT)) & CAN_CS_RTR_MASK) 769 770 #define CAN_CS_IDE_MASK (0x200000U) 771 #define CAN_CS_IDE_SHIFT (21U) 772 /*! IDE - ID Extended. One/zero for extended/standard format frame. 773 */ 774 #define CAN_CS_IDE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_IDE_SHIFT)) & CAN_CS_IDE_MASK) 775 776 #define CAN_CS_SRR_MASK (0x400000U) 777 #define CAN_CS_SRR_SHIFT (22U) 778 /*! SRR - Substitute Remote Request. Contains a fixed recessive bit. 779 */ 780 #define CAN_CS_SRR(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_SRR_SHIFT)) & CAN_CS_SRR_MASK) 781 782 #define CAN_CS_CODE_MASK (0xF000000U) 783 #define CAN_CS_CODE_SHIFT (24U) 784 785 #define CAN_CS_CODE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_CODE_SHIFT)) & CAN_CS_CODE_MASK) 786 787 #define CAN_CS_ESI_MASK (0x20000000U) 788 #define CAN_CS_ESI_SHIFT (29U) 789 /*! ESI - Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 790 */ 791 #define CAN_CS_ESI(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_ESI_SHIFT)) & CAN_CS_ESI_MASK) 792 793 #define CAN_CS_BRS_MASK (0x40000000U) 794 #define CAN_CS_BRS_SHIFT (30U) 795 /*! BRS - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 796 */ 797 #define CAN_CS_BRS(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_BRS_SHIFT)) & CAN_CS_BRS_MASK) 798 799 #define CAN_CS_EDL_MASK (0x80000000U) 800 #define CAN_CS_EDL_SHIFT (31U) 801 /*! EDL - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. 802 * The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 803 */ 804 #define CAN_CS_EDL(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_EDL_SHIFT)) & CAN_CS_EDL_MASK) 805 /*! @} */ 806 807 /* The count of CAN_CS */ 808 #define CAN_CS_COUNT_MB64B (21U) 809 810 /*! @name ID - Message Buffer 0 ID Register..Message Buffer 20 ID Register */ 811 /*! @{ */ 812 813 #define CAN_ID_EXT_MASK (0x3FFFFU) 814 #define CAN_ID_EXT_SHIFT (0U) 815 /*! EXT - Contains extended (LOW word) identifier of message buffer. 816 */ 817 #define CAN_ID_EXT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_EXT_SHIFT)) & CAN_ID_EXT_MASK) 818 819 #define CAN_ID_STD_MASK (0x1FFC0000U) 820 #define CAN_ID_STD_SHIFT (18U) 821 /*! STD - Contains standard/extended (HIGH word) identifier of message buffer. 822 */ 823 #define CAN_ID_STD(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_STD_SHIFT)) & CAN_ID_STD_MASK) 824 825 #define CAN_ID_PRIO_MASK (0xE0000000U) 826 #define CAN_ID_PRIO_SHIFT (29U) 827 /*! PRIO - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only 828 * makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular 829 * ID to define the transmission priority. 830 */ 831 #define CAN_ID_PRIO(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_PRIO_SHIFT)) & CAN_ID_PRIO_MASK) 832 /*! @} */ 833 834 /* The count of CAN_ID */ 835 #define CAN_ID_COUNT_MB64B (21U) 836 837 /*! @name WORD - Message Buffer 0 WORD_64B Register..Message Buffer 20 WORD_64B Register */ 838 /*! @{ */ 839 840 #define CAN_WORD_DATA_BYTE_3_MASK (0xFFU) 841 #define CAN_WORD_DATA_BYTE_3_SHIFT (0U) 842 /*! DATA_BYTE_3 - Data byte 0 of Rx/Tx frame. 843 */ 844 #define CAN_WORD_DATA_BYTE_3(x) \ 845 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_3_SHIFT)) & CAN_WORD_DATA_BYTE_3_MASK) 846 847 #define CAN_WORD_DATA_BYTE_7_MASK (0xFFU) 848 #define CAN_WORD_DATA_BYTE_7_SHIFT (0U) 849 /*! DATA_BYTE_7 - Data byte 0 of Rx/Tx frame. 850 */ 851 #define CAN_WORD_DATA_BYTE_7(x) \ 852 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_7_SHIFT)) & CAN_WORD_DATA_BYTE_7_MASK) 853 854 #define CAN_WORD_DATA_BYTE_11_MASK (0xFFU) 855 #define CAN_WORD_DATA_BYTE_11_SHIFT (0U) 856 /*! DATA_BYTE_11 - Data byte 0 of Rx/Tx frame. 857 */ 858 #define CAN_WORD_DATA_BYTE_11(x) \ 859 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_11_SHIFT)) & CAN_WORD_DATA_BYTE_11_MASK) 860 861 #define CAN_WORD_DATA_BYTE_15_MASK (0xFFU) 862 #define CAN_WORD_DATA_BYTE_15_SHIFT (0U) 863 /*! DATA_BYTE_15 - Data byte 0 of Rx/Tx frame. 864 */ 865 #define CAN_WORD_DATA_BYTE_15(x) \ 866 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_15_SHIFT)) & CAN_WORD_DATA_BYTE_15_MASK) 867 868 #define CAN_WORD_DATA_BYTE_19_MASK (0xFFU) 869 #define CAN_WORD_DATA_BYTE_19_SHIFT (0U) 870 /*! DATA_BYTE_19 - Data byte 0 of Rx/Tx frame. 871 */ 872 #define CAN_WORD_DATA_BYTE_19(x) \ 873 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_19_SHIFT)) & CAN_WORD_DATA_BYTE_19_MASK) 874 875 #define CAN_WORD_DATA_BYTE_23_MASK (0xFFU) 876 #define CAN_WORD_DATA_BYTE_23_SHIFT (0U) 877 /*! DATA_BYTE_23 - Data byte 0 of Rx/Tx frame. 878 */ 879 #define CAN_WORD_DATA_BYTE_23(x) \ 880 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_23_SHIFT)) & CAN_WORD_DATA_BYTE_23_MASK) 881 882 #define CAN_WORD_DATA_BYTE_27_MASK (0xFFU) 883 #define CAN_WORD_DATA_BYTE_27_SHIFT (0U) 884 /*! DATA_BYTE_27 - Data byte 0 of Rx/Tx frame. 885 */ 886 #define CAN_WORD_DATA_BYTE_27(x) \ 887 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_27_SHIFT)) & CAN_WORD_DATA_BYTE_27_MASK) 888 889 #define CAN_WORD_DATA_BYTE_31_MASK (0xFFU) 890 #define CAN_WORD_DATA_BYTE_31_SHIFT (0U) 891 /*! DATA_BYTE_31 - Data byte 0 of Rx/Tx frame. 892 */ 893 #define CAN_WORD_DATA_BYTE_31(x) \ 894 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_31_SHIFT)) & CAN_WORD_DATA_BYTE_31_MASK) 895 896 #define CAN_WORD_DATA_BYTE_35_MASK (0xFFU) 897 #define CAN_WORD_DATA_BYTE_35_SHIFT (0U) 898 /*! DATA_BYTE_35 - Data byte 0 of Rx/Tx frame. 899 */ 900 #define CAN_WORD_DATA_BYTE_35(x) \ 901 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_35_SHIFT)) & CAN_WORD_DATA_BYTE_35_MASK) 902 903 #define CAN_WORD_DATA_BYTE_39_MASK (0xFFU) 904 #define CAN_WORD_DATA_BYTE_39_SHIFT (0U) 905 /*! DATA_BYTE_39 - Data byte 0 of Rx/Tx frame. 906 */ 907 #define CAN_WORD_DATA_BYTE_39(x) \ 908 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_39_SHIFT)) & CAN_WORD_DATA_BYTE_39_MASK) 909 910 #define CAN_WORD_DATA_BYTE_43_MASK (0xFFU) 911 #define CAN_WORD_DATA_BYTE_43_SHIFT (0U) 912 /*! DATA_BYTE_43 - Data byte 0 of Rx/Tx frame. 913 */ 914 #define CAN_WORD_DATA_BYTE_43(x) \ 915 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_43_SHIFT)) & CAN_WORD_DATA_BYTE_43_MASK) 916 917 #define CAN_WORD_DATA_BYTE_47_MASK (0xFFU) 918 #define CAN_WORD_DATA_BYTE_47_SHIFT (0U) 919 /*! DATA_BYTE_47 - Data byte 0 of Rx/Tx frame. 920 */ 921 #define CAN_WORD_DATA_BYTE_47(x) \ 922 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_47_SHIFT)) & CAN_WORD_DATA_BYTE_47_MASK) 923 924 #define CAN_WORD_DATA_BYTE_51_MASK (0xFFU) 925 #define CAN_WORD_DATA_BYTE_51_SHIFT (0U) 926 /*! DATA_BYTE_51 - Data byte 0 of Rx/Tx frame. 927 */ 928 #define CAN_WORD_DATA_BYTE_51(x) \ 929 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_51_SHIFT)) & CAN_WORD_DATA_BYTE_51_MASK) 930 931 #define CAN_WORD_DATA_BYTE_55_MASK (0xFFU) 932 #define CAN_WORD_DATA_BYTE_55_SHIFT (0U) 933 /*! DATA_BYTE_55 - Data byte 0 of Rx/Tx frame. 934 */ 935 #define CAN_WORD_DATA_BYTE_55(x) \ 936 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_55_SHIFT)) & CAN_WORD_DATA_BYTE_55_MASK) 937 938 #define CAN_WORD_DATA_BYTE_59_MASK (0xFFU) 939 #define CAN_WORD_DATA_BYTE_59_SHIFT (0U) 940 /*! DATA_BYTE_59 - Data byte 0 of Rx/Tx frame. 941 */ 942 #define CAN_WORD_DATA_BYTE_59(x) \ 943 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_59_SHIFT)) & CAN_WORD_DATA_BYTE_59_MASK) 944 945 #define CAN_WORD_DATA_BYTE_63_MASK (0xFFU) 946 #define CAN_WORD_DATA_BYTE_63_SHIFT (0U) 947 /*! DATA_BYTE_63 - Data byte 0 of Rx/Tx frame. 948 */ 949 #define CAN_WORD_DATA_BYTE_63(x) \ 950 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_63_SHIFT)) & CAN_WORD_DATA_BYTE_63_MASK) 951 952 #define CAN_WORD_DATA_BYTE_2_MASK (0xFF00U) 953 #define CAN_WORD_DATA_BYTE_2_SHIFT (8U) 954 /*! DATA_BYTE_2 - Data byte 1 of Rx/Tx frame. 955 */ 956 #define CAN_WORD_DATA_BYTE_2(x) \ 957 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_2_SHIFT)) & CAN_WORD_DATA_BYTE_2_MASK) 958 959 #define CAN_WORD_DATA_BYTE_6_MASK (0xFF00U) 960 #define CAN_WORD_DATA_BYTE_6_SHIFT (8U) 961 /*! DATA_BYTE_6 - Data byte 1 of Rx/Tx frame. 962 */ 963 #define CAN_WORD_DATA_BYTE_6(x) \ 964 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_6_SHIFT)) & CAN_WORD_DATA_BYTE_6_MASK) 965 966 #define CAN_WORD_DATA_BYTE_10_MASK (0xFF00U) 967 #define CAN_WORD_DATA_BYTE_10_SHIFT (8U) 968 /*! DATA_BYTE_10 - Data byte 1 of Rx/Tx frame. 969 */ 970 #define CAN_WORD_DATA_BYTE_10(x) \ 971 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_10_SHIFT)) & CAN_WORD_DATA_BYTE_10_MASK) 972 973 #define CAN_WORD_DATA_BYTE_14_MASK (0xFF00U) 974 #define CAN_WORD_DATA_BYTE_14_SHIFT (8U) 975 /*! DATA_BYTE_14 - Data byte 1 of Rx/Tx frame. 976 */ 977 #define CAN_WORD_DATA_BYTE_14(x) \ 978 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_14_SHIFT)) & CAN_WORD_DATA_BYTE_14_MASK) 979 980 #define CAN_WORD_DATA_BYTE_18_MASK (0xFF00U) 981 #define CAN_WORD_DATA_BYTE_18_SHIFT (8U) 982 /*! DATA_BYTE_18 - Data byte 1 of Rx/Tx frame. 983 */ 984 #define CAN_WORD_DATA_BYTE_18(x) \ 985 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_18_SHIFT)) & CAN_WORD_DATA_BYTE_18_MASK) 986 987 #define CAN_WORD_DATA_BYTE_22_MASK (0xFF00U) 988 #define CAN_WORD_DATA_BYTE_22_SHIFT (8U) 989 /*! DATA_BYTE_22 - Data byte 1 of Rx/Tx frame. 990 */ 991 #define CAN_WORD_DATA_BYTE_22(x) \ 992 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_22_SHIFT)) & CAN_WORD_DATA_BYTE_22_MASK) 993 994 #define CAN_WORD_DATA_BYTE_26_MASK (0xFF00U) 995 #define CAN_WORD_DATA_BYTE_26_SHIFT (8U) 996 /*! DATA_BYTE_26 - Data byte 1 of Rx/Tx frame. 997 */ 998 #define CAN_WORD_DATA_BYTE_26(x) \ 999 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_26_SHIFT)) & CAN_WORD_DATA_BYTE_26_MASK) 1000 1001 #define CAN_WORD_DATA_BYTE_30_MASK (0xFF00U) 1002 #define CAN_WORD_DATA_BYTE_30_SHIFT (8U) 1003 /*! DATA_BYTE_30 - Data byte 1 of Rx/Tx frame. 1004 */ 1005 #define CAN_WORD_DATA_BYTE_30(x) \ 1006 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_30_SHIFT)) & CAN_WORD_DATA_BYTE_30_MASK) 1007 1008 #define CAN_WORD_DATA_BYTE_34_MASK (0xFF00U) 1009 #define CAN_WORD_DATA_BYTE_34_SHIFT (8U) 1010 /*! DATA_BYTE_34 - Data byte 1 of Rx/Tx frame. 1011 */ 1012 #define CAN_WORD_DATA_BYTE_34(x) \ 1013 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_34_SHIFT)) & CAN_WORD_DATA_BYTE_34_MASK) 1014 1015 #define CAN_WORD_DATA_BYTE_38_MASK (0xFF00U) 1016 #define CAN_WORD_DATA_BYTE_38_SHIFT (8U) 1017 /*! DATA_BYTE_38 - Data byte 1 of Rx/Tx frame. 1018 */ 1019 #define CAN_WORD_DATA_BYTE_38(x) \ 1020 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_38_SHIFT)) & CAN_WORD_DATA_BYTE_38_MASK) 1021 1022 #define CAN_WORD_DATA_BYTE_42_MASK (0xFF00U) 1023 #define CAN_WORD_DATA_BYTE_42_SHIFT (8U) 1024 /*! DATA_BYTE_42 - Data byte 1 of Rx/Tx frame. 1025 */ 1026 #define CAN_WORD_DATA_BYTE_42(x) \ 1027 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_42_SHIFT)) & CAN_WORD_DATA_BYTE_42_MASK) 1028 1029 #define CAN_WORD_DATA_BYTE_46_MASK (0xFF00U) 1030 #define CAN_WORD_DATA_BYTE_46_SHIFT (8U) 1031 /*! DATA_BYTE_46 - Data byte 1 of Rx/Tx frame. 1032 */ 1033 #define CAN_WORD_DATA_BYTE_46(x) \ 1034 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_46_SHIFT)) & CAN_WORD_DATA_BYTE_46_MASK) 1035 1036 #define CAN_WORD_DATA_BYTE_50_MASK (0xFF00U) 1037 #define CAN_WORD_DATA_BYTE_50_SHIFT (8U) 1038 /*! DATA_BYTE_50 - Data byte 1 of Rx/Tx frame. 1039 */ 1040 #define CAN_WORD_DATA_BYTE_50(x) \ 1041 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_50_SHIFT)) & CAN_WORD_DATA_BYTE_50_MASK) 1042 1043 #define CAN_WORD_DATA_BYTE_54_MASK (0xFF00U) 1044 #define CAN_WORD_DATA_BYTE_54_SHIFT (8U) 1045 /*! DATA_BYTE_54 - Data byte 1 of Rx/Tx frame. 1046 */ 1047 #define CAN_WORD_DATA_BYTE_54(x) \ 1048 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_54_SHIFT)) & CAN_WORD_DATA_BYTE_54_MASK) 1049 1050 #define CAN_WORD_DATA_BYTE_58_MASK (0xFF00U) 1051 #define CAN_WORD_DATA_BYTE_58_SHIFT (8U) 1052 /*! DATA_BYTE_58 - Data byte 1 of Rx/Tx frame. 1053 */ 1054 #define CAN_WORD_DATA_BYTE_58(x) \ 1055 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_58_SHIFT)) & CAN_WORD_DATA_BYTE_58_MASK) 1056 1057 #define CAN_WORD_DATA_BYTE_62_MASK (0xFF00U) 1058 #define CAN_WORD_DATA_BYTE_62_SHIFT (8U) 1059 /*! DATA_BYTE_62 - Data byte 1 of Rx/Tx frame. 1060 */ 1061 #define CAN_WORD_DATA_BYTE_62(x) \ 1062 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_62_SHIFT)) & CAN_WORD_DATA_BYTE_62_MASK) 1063 1064 #define CAN_WORD_DATA_BYTE_1_MASK (0xFF0000U) 1065 #define CAN_WORD_DATA_BYTE_1_SHIFT (16U) 1066 /*! DATA_BYTE_1 - Data byte 2 of Rx/Tx frame. 1067 */ 1068 #define CAN_WORD_DATA_BYTE_1(x) \ 1069 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_1_SHIFT)) & CAN_WORD_DATA_BYTE_1_MASK) 1070 1071 #define CAN_WORD_DATA_BYTE_5_MASK (0xFF0000U) 1072 #define CAN_WORD_DATA_BYTE_5_SHIFT (16U) 1073 /*! DATA_BYTE_5 - Data byte 2 of Rx/Tx frame. 1074 */ 1075 #define CAN_WORD_DATA_BYTE_5(x) \ 1076 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_5_SHIFT)) & CAN_WORD_DATA_BYTE_5_MASK) 1077 1078 #define CAN_WORD_DATA_BYTE_9_MASK (0xFF0000U) 1079 #define CAN_WORD_DATA_BYTE_9_SHIFT (16U) 1080 /*! DATA_BYTE_9 - Data byte 2 of Rx/Tx frame. 1081 */ 1082 #define CAN_WORD_DATA_BYTE_9(x) \ 1083 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_9_SHIFT)) & CAN_WORD_DATA_BYTE_9_MASK) 1084 1085 #define CAN_WORD_DATA_BYTE_13_MASK (0xFF0000U) 1086 #define CAN_WORD_DATA_BYTE_13_SHIFT (16U) 1087 /*! DATA_BYTE_13 - Data byte 2 of Rx/Tx frame. 1088 */ 1089 #define CAN_WORD_DATA_BYTE_13(x) \ 1090 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_13_SHIFT)) & CAN_WORD_DATA_BYTE_13_MASK) 1091 1092 #define CAN_WORD_DATA_BYTE_17_MASK (0xFF0000U) 1093 #define CAN_WORD_DATA_BYTE_17_SHIFT (16U) 1094 /*! DATA_BYTE_17 - Data byte 2 of Rx/Tx frame. 1095 */ 1096 #define CAN_WORD_DATA_BYTE_17(x) \ 1097 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_17_SHIFT)) & CAN_WORD_DATA_BYTE_17_MASK) 1098 1099 #define CAN_WORD_DATA_BYTE_21_MASK (0xFF0000U) 1100 #define CAN_WORD_DATA_BYTE_21_SHIFT (16U) 1101 /*! DATA_BYTE_21 - Data byte 2 of Rx/Tx frame. 1102 */ 1103 #define CAN_WORD_DATA_BYTE_21(x) \ 1104 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_21_SHIFT)) & CAN_WORD_DATA_BYTE_21_MASK) 1105 1106 #define CAN_WORD_DATA_BYTE_25_MASK (0xFF0000U) 1107 #define CAN_WORD_DATA_BYTE_25_SHIFT (16U) 1108 /*! DATA_BYTE_25 - Data byte 2 of Rx/Tx frame. 1109 */ 1110 #define CAN_WORD_DATA_BYTE_25(x) \ 1111 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_25_SHIFT)) & CAN_WORD_DATA_BYTE_25_MASK) 1112 1113 #define CAN_WORD_DATA_BYTE_29_MASK (0xFF0000U) 1114 #define CAN_WORD_DATA_BYTE_29_SHIFT (16U) 1115 /*! DATA_BYTE_29 - Data byte 2 of Rx/Tx frame. 1116 */ 1117 #define CAN_WORD_DATA_BYTE_29(x) \ 1118 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_29_SHIFT)) & CAN_WORD_DATA_BYTE_29_MASK) 1119 1120 #define CAN_WORD_DATA_BYTE_33_MASK (0xFF0000U) 1121 #define CAN_WORD_DATA_BYTE_33_SHIFT (16U) 1122 /*! DATA_BYTE_33 - Data byte 2 of Rx/Tx frame. 1123 */ 1124 #define CAN_WORD_DATA_BYTE_33(x) \ 1125 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_33_SHIFT)) & CAN_WORD_DATA_BYTE_33_MASK) 1126 1127 #define CAN_WORD_DATA_BYTE_37_MASK (0xFF0000U) 1128 #define CAN_WORD_DATA_BYTE_37_SHIFT (16U) 1129 /*! DATA_BYTE_37 - Data byte 2 of Rx/Tx frame. 1130 */ 1131 #define CAN_WORD_DATA_BYTE_37(x) \ 1132 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_37_SHIFT)) & CAN_WORD_DATA_BYTE_37_MASK) 1133 1134 #define CAN_WORD_DATA_BYTE_41_MASK (0xFF0000U) 1135 #define CAN_WORD_DATA_BYTE_41_SHIFT (16U) 1136 /*! DATA_BYTE_41 - Data byte 2 of Rx/Tx frame. 1137 */ 1138 #define CAN_WORD_DATA_BYTE_41(x) \ 1139 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_41_SHIFT)) & CAN_WORD_DATA_BYTE_41_MASK) 1140 1141 #define CAN_WORD_DATA_BYTE_45_MASK (0xFF0000U) 1142 #define CAN_WORD_DATA_BYTE_45_SHIFT (16U) 1143 /*! DATA_BYTE_45 - Data byte 2 of Rx/Tx frame. 1144 */ 1145 #define CAN_WORD_DATA_BYTE_45(x) \ 1146 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_45_SHIFT)) & CAN_WORD_DATA_BYTE_45_MASK) 1147 1148 #define CAN_WORD_DATA_BYTE_49_MASK (0xFF0000U) 1149 #define CAN_WORD_DATA_BYTE_49_SHIFT (16U) 1150 /*! DATA_BYTE_49 - Data byte 2 of Rx/Tx frame. 1151 */ 1152 #define CAN_WORD_DATA_BYTE_49(x) \ 1153 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_49_SHIFT)) & CAN_WORD_DATA_BYTE_49_MASK) 1154 1155 #define CAN_WORD_DATA_BYTE_53_MASK (0xFF0000U) 1156 #define CAN_WORD_DATA_BYTE_53_SHIFT (16U) 1157 /*! DATA_BYTE_53 - Data byte 2 of Rx/Tx frame. 1158 */ 1159 #define CAN_WORD_DATA_BYTE_53(x) \ 1160 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_53_SHIFT)) & CAN_WORD_DATA_BYTE_53_MASK) 1161 1162 #define CAN_WORD_DATA_BYTE_57_MASK (0xFF0000U) 1163 #define CAN_WORD_DATA_BYTE_57_SHIFT (16U) 1164 /*! DATA_BYTE_57 - Data byte 2 of Rx/Tx frame. 1165 */ 1166 #define CAN_WORD_DATA_BYTE_57(x) \ 1167 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_57_SHIFT)) & CAN_WORD_DATA_BYTE_57_MASK) 1168 1169 #define CAN_WORD_DATA_BYTE_61_MASK (0xFF0000U) 1170 #define CAN_WORD_DATA_BYTE_61_SHIFT (16U) 1171 /*! DATA_BYTE_61 - Data byte 2 of Rx/Tx frame. 1172 */ 1173 #define CAN_WORD_DATA_BYTE_61(x) \ 1174 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_61_SHIFT)) & CAN_WORD_DATA_BYTE_61_MASK) 1175 1176 #define CAN_WORD_DATA_BYTE_0_MASK (0xFF000000U) 1177 #define CAN_WORD_DATA_BYTE_0_SHIFT (24U) 1178 /*! DATA_BYTE_0 - Data byte 3 of Rx/Tx frame. 1179 */ 1180 #define CAN_WORD_DATA_BYTE_0(x) \ 1181 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_0_SHIFT)) & CAN_WORD_DATA_BYTE_0_MASK) 1182 1183 #define CAN_WORD_DATA_BYTE_4_MASK (0xFF000000U) 1184 #define CAN_WORD_DATA_BYTE_4_SHIFT (24U) 1185 /*! DATA_BYTE_4 - Data byte 3 of Rx/Tx frame. 1186 */ 1187 #define CAN_WORD_DATA_BYTE_4(x) \ 1188 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_4_SHIFT)) & CAN_WORD_DATA_BYTE_4_MASK) 1189 1190 #define CAN_WORD_DATA_BYTE_8_MASK (0xFF000000U) 1191 #define CAN_WORD_DATA_BYTE_8_SHIFT (24U) 1192 /*! DATA_BYTE_8 - Data byte 3 of Rx/Tx frame. 1193 */ 1194 #define CAN_WORD_DATA_BYTE_8(x) \ 1195 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_8_SHIFT)) & CAN_WORD_DATA_BYTE_8_MASK) 1196 1197 #define CAN_WORD_DATA_BYTE_12_MASK (0xFF000000U) 1198 #define CAN_WORD_DATA_BYTE_12_SHIFT (24U) 1199 /*! DATA_BYTE_12 - Data byte 3 of Rx/Tx frame. 1200 */ 1201 #define CAN_WORD_DATA_BYTE_12(x) \ 1202 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_12_SHIFT)) & CAN_WORD_DATA_BYTE_12_MASK) 1203 1204 #define CAN_WORD_DATA_BYTE_16_MASK (0xFF000000U) 1205 #define CAN_WORD_DATA_BYTE_16_SHIFT (24U) 1206 /*! DATA_BYTE_16 - Data byte 3 of Rx/Tx frame. 1207 */ 1208 #define CAN_WORD_DATA_BYTE_16(x) \ 1209 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_16_SHIFT)) & CAN_WORD_DATA_BYTE_16_MASK) 1210 1211 #define CAN_WORD_DATA_BYTE_20_MASK (0xFF000000U) 1212 #define CAN_WORD_DATA_BYTE_20_SHIFT (24U) 1213 /*! DATA_BYTE_20 - Data byte 3 of Rx/Tx frame. 1214 */ 1215 #define CAN_WORD_DATA_BYTE_20(x) \ 1216 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_20_SHIFT)) & CAN_WORD_DATA_BYTE_20_MASK) 1217 1218 #define CAN_WORD_DATA_BYTE_24_MASK (0xFF000000U) 1219 #define CAN_WORD_DATA_BYTE_24_SHIFT (24U) 1220 /*! DATA_BYTE_24 - Data byte 3 of Rx/Tx frame. 1221 */ 1222 #define CAN_WORD_DATA_BYTE_24(x) \ 1223 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_24_SHIFT)) & CAN_WORD_DATA_BYTE_24_MASK) 1224 1225 #define CAN_WORD_DATA_BYTE_28_MASK (0xFF000000U) 1226 #define CAN_WORD_DATA_BYTE_28_SHIFT (24U) 1227 /*! DATA_BYTE_28 - Data byte 3 of Rx/Tx frame. 1228 */ 1229 #define CAN_WORD_DATA_BYTE_28(x) \ 1230 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_28_SHIFT)) & CAN_WORD_DATA_BYTE_28_MASK) 1231 1232 #define CAN_WORD_DATA_BYTE_32_MASK (0xFF000000U) 1233 #define CAN_WORD_DATA_BYTE_32_SHIFT (24U) 1234 /*! DATA_BYTE_32 - Data byte 3 of Rx/Tx frame. 1235 */ 1236 #define CAN_WORD_DATA_BYTE_32(x) \ 1237 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_32_SHIFT)) & CAN_WORD_DATA_BYTE_32_MASK) 1238 1239 #define CAN_WORD_DATA_BYTE_36_MASK (0xFF000000U) 1240 #define CAN_WORD_DATA_BYTE_36_SHIFT (24U) 1241 /*! DATA_BYTE_36 - Data byte 3 of Rx/Tx frame. 1242 */ 1243 #define CAN_WORD_DATA_BYTE_36(x) \ 1244 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_36_SHIFT)) & CAN_WORD_DATA_BYTE_36_MASK) 1245 1246 #define CAN_WORD_DATA_BYTE_40_MASK (0xFF000000U) 1247 #define CAN_WORD_DATA_BYTE_40_SHIFT (24U) 1248 /*! DATA_BYTE_40 - Data byte 3 of Rx/Tx frame. 1249 */ 1250 #define CAN_WORD_DATA_BYTE_40(x) \ 1251 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_40_SHIFT)) & CAN_WORD_DATA_BYTE_40_MASK) 1252 1253 #define CAN_WORD_DATA_BYTE_44_MASK (0xFF000000U) 1254 #define CAN_WORD_DATA_BYTE_44_SHIFT (24U) 1255 /*! DATA_BYTE_44 - Data byte 3 of Rx/Tx frame. 1256 */ 1257 #define CAN_WORD_DATA_BYTE_44(x) \ 1258 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_44_SHIFT)) & CAN_WORD_DATA_BYTE_44_MASK) 1259 1260 #define CAN_WORD_DATA_BYTE_48_MASK (0xFF000000U) 1261 #define CAN_WORD_DATA_BYTE_48_SHIFT (24U) 1262 /*! DATA_BYTE_48 - Data byte 3 of Rx/Tx frame. 1263 */ 1264 #define CAN_WORD_DATA_BYTE_48(x) \ 1265 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_48_SHIFT)) & CAN_WORD_DATA_BYTE_48_MASK) 1266 1267 #define CAN_WORD_DATA_BYTE_52_MASK (0xFF000000U) 1268 #define CAN_WORD_DATA_BYTE_52_SHIFT (24U) 1269 /*! DATA_BYTE_52 - Data byte 3 of Rx/Tx frame. 1270 */ 1271 #define CAN_WORD_DATA_BYTE_52(x) \ 1272 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_52_SHIFT)) & CAN_WORD_DATA_BYTE_52_MASK) 1273 1274 #define CAN_WORD_DATA_BYTE_56_MASK (0xFF000000U) 1275 #define CAN_WORD_DATA_BYTE_56_SHIFT (24U) 1276 /*! DATA_BYTE_56 - Data byte 3 of Rx/Tx frame. 1277 */ 1278 #define CAN_WORD_DATA_BYTE_56(x) \ 1279 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_56_SHIFT)) & CAN_WORD_DATA_BYTE_56_MASK) 1280 1281 #define CAN_WORD_DATA_BYTE_60_MASK (0xFF000000U) 1282 #define CAN_WORD_DATA_BYTE_60_SHIFT (24U) 1283 /*! DATA_BYTE_60 - Data byte 3 of Rx/Tx frame. 1284 */ 1285 #define CAN_WORD_DATA_BYTE_60(x) \ 1286 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_60_SHIFT)) & CAN_WORD_DATA_BYTE_60_MASK) 1287 /*! @} */ 1288 1289 /* The count of CAN_WORD */ 1290 #define CAN_WORD_COUNT_MB64B (21U) 1291 1292 /* The count of CAN_WORD */ 1293 #define CAN_WORD_COUNT_MB64B2 (16U) 1294 1295 /* The count of CAN_CS */ 1296 #define CAN_CS_COUNT (96U) 1297 1298 /* The count of CAN_ID */ 1299 #define CAN_ID_COUNT (96U) 1300 1301 /*! @name WORD0 - Message Buffer 0 WORD0 Register..Message Buffer 95 WORD0 Register */ 1302 /*! @{ */ 1303 1304 #define CAN_WORD0_DATA_BYTE_3_MASK (0xFFU) 1305 #define CAN_WORD0_DATA_BYTE_3_SHIFT (0U) 1306 /*! DATA_BYTE_3 - Data byte 0 of Rx/Tx frame. 1307 */ 1308 #define CAN_WORD0_DATA_BYTE_3(x) \ 1309 (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_3_SHIFT)) & CAN_WORD0_DATA_BYTE_3_MASK) 1310 1311 #define CAN_WORD0_DATA_BYTE_2_MASK (0xFF00U) 1312 #define CAN_WORD0_DATA_BYTE_2_SHIFT (8U) 1313 /*! DATA_BYTE_2 - Data byte 1 of Rx/Tx frame. 1314 */ 1315 #define CAN_WORD0_DATA_BYTE_2(x) \ 1316 (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_2_SHIFT)) & CAN_WORD0_DATA_BYTE_2_MASK) 1317 1318 #define CAN_WORD0_DATA_BYTE_1_MASK (0xFF0000U) 1319 #define CAN_WORD0_DATA_BYTE_1_SHIFT (16U) 1320 /*! DATA_BYTE_1 - Data byte 2 of Rx/Tx frame. 1321 */ 1322 #define CAN_WORD0_DATA_BYTE_1(x) \ 1323 (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_1_SHIFT)) & CAN_WORD0_DATA_BYTE_1_MASK) 1324 1325 #define CAN_WORD0_DATA_BYTE_0_MASK (0xFF000000U) 1326 #define CAN_WORD0_DATA_BYTE_0_SHIFT (24U) 1327 /*! DATA_BYTE_0 - Data byte 3 of Rx/Tx frame. 1328 */ 1329 #define CAN_WORD0_DATA_BYTE_0(x) \ 1330 (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_0_SHIFT)) & CAN_WORD0_DATA_BYTE_0_MASK) 1331 /*! @} */ 1332 1333 /* The count of CAN_WORD0 */ 1334 #define CAN_WORD0_COUNT (96U) 1335 1336 /*! @name WORD1 - Message Buffer 0 WORD1 Register..Message Buffer 95 WORD1 Register */ 1337 /*! @{ */ 1338 1339 #define CAN_WORD1_DATA_BYTE_7_MASK (0xFFU) 1340 #define CAN_WORD1_DATA_BYTE_7_SHIFT (0U) 1341 /*! DATA_BYTE_7 - Data byte 0 of Rx/Tx frame. 1342 */ 1343 #define CAN_WORD1_DATA_BYTE_7(x) \ 1344 (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_7_SHIFT)) & CAN_WORD1_DATA_BYTE_7_MASK) 1345 1346 #define CAN_WORD1_DATA_BYTE_6_MASK (0xFF00U) 1347 #define CAN_WORD1_DATA_BYTE_6_SHIFT (8U) 1348 /*! DATA_BYTE_6 - Data byte 1 of Rx/Tx frame. 1349 */ 1350 #define CAN_WORD1_DATA_BYTE_6(x) \ 1351 (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_6_SHIFT)) & CAN_WORD1_DATA_BYTE_6_MASK) 1352 1353 #define CAN_WORD1_DATA_BYTE_5_MASK (0xFF0000U) 1354 #define CAN_WORD1_DATA_BYTE_5_SHIFT (16U) 1355 /*! DATA_BYTE_5 - Data byte 2 of Rx/Tx frame. 1356 */ 1357 #define CAN_WORD1_DATA_BYTE_5(x) \ 1358 (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_5_SHIFT)) & CAN_WORD1_DATA_BYTE_5_MASK) 1359 1360 #define CAN_WORD1_DATA_BYTE_4_MASK (0xFF000000U) 1361 #define CAN_WORD1_DATA_BYTE_4_SHIFT (24U) 1362 /*! DATA_BYTE_4 - Data byte 3 of Rx/Tx frame. 1363 */ 1364 #define CAN_WORD1_DATA_BYTE_4(x) \ 1365 (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_4_SHIFT)) & CAN_WORD1_DATA_BYTE_4_MASK) 1366 /*! @} */ 1367 1368 /* The count of CAN_WORD1 */ 1369 #define CAN_WORD1_COUNT (96U) 1370 1371 /*! @name RXIMR - Rx Individual Mask Registers */ 1372 /*! @{ */ 1373 1374 #define CAN_RXIMR_MI_MASK FLEXCAN_RXIMR_MI_MASK 1375 #define CAN_RXIMR_MI_SHIFT FLEXCAN_RXIMR_MI_SHIFT 1376 1377 #define CAN_RXIMR_MI(x) FLEXCAN_RXIMR_MI(x) 1378 1379 /* The count of CAN_RXIMR */ 1380 #define CAN_RXIMR_COUNT (128U) 1381 1382 /*! @name MECR - Memory Error Control Register */ 1383 /*! @{ */ 1384 1385 #define CAN_MECR_NCEFAFRZ_MASK FLEXCAN_MECR_NCEFAFRZ_MASK 1386 #define CAN_MECR_NCEFAFRZ_SHIFT FLEXCAN_MECR_NCEFAFRZ_SHIFT 1387 1388 #define CAN_MECR_NCEFAFRZ(x) FLEXCAN_MECR_NCEFAFRZ(x) 1389 1390 #define CAN_MECR_ECCDIS_MASK FLEXCAN_MECR_ECCDIS_MASK 1391 #define CAN_MECR_ECCDIS_SHIFT FLEXCAN_MECR_ECCDIS_SHIFT 1392 1393 #define CAN_MECR_ECCDIS(x) FLEXCAN_MECR_ECCDIS(x) 1394 1395 #define CAN_MECR_RERRDIS_MASK FLEXCAN_MECR_RERRDIS_MASK 1396 #define CAN_MECR_RERRDIS_SHIFT FLEXCAN_MECR_RERRDIS_SHIFT 1397 1398 #define CAN_MECR_RERRDIS(x) FLEXCAN_MECR_RERRDIS(x) 1399 1400 #define CAN_MECR_EXTERRIE_MASK FLEXCAN_MECR_EXTERRIE_MASK 1401 #define CAN_MECR_EXTERRIE_SHIFT FLEXCAN_MECR_EXTERRIE_SHIFT 1402 1403 #define CAN_MECR_EXTERRIE(x) FLEXCAN_MECR_EXTERRIE(x) 1404 1405 #define CAN_MECR_FAERRIE_MASK FLEXCAN_MECR_FAERRIE_MASK 1406 #define CAN_MECR_FAERRIE_SHIFT FLEXCAN_MECR_FAERRIE_SHIFT 1407 1408 #define CAN_MECR_FAERRIE(x) FLEXCAN_MECR_FAERRIE(x) 1409 1410 #define CAN_MECR_HAERRIE_MASK FLEXCAN_MECR_HAERRIE_MASK 1411 #define CAN_MECR_HAERRIE_SHIFT FLEXCAN_MECR_HAERRIE_SHIFT 1412 1413 #define CAN_MECR_HAERRIE(x) FLEXCAN_MECR_HAERRIE(x) 1414 1415 #define CAN_MECR_ECRWRDIS_MASK FLEXCAN_MECR_ECRWRDIS_MASK 1416 #define CAN_MECR_ECRWRDIS_SHIFT FLEXCAN_MECR_ECRWRDIS_SHIFT 1417 1418 #define CAN_MECR_ECRWRDIS(x) FLEXCAN_MECR_ECRWRDIS(x) 1419 /*! @} */ 1420 1421 /*! @name ERRIAR - Error Injection Address Register */ 1422 /*! @{ */ 1423 1424 #define CAN_ERRIAR_INJADDR_L_MASK FLEXCAN_ERRIAR_INJADDR_L_MASK 1425 #define CAN_ERRIAR_INJADDR_L_SHIFT FLEXCAN_ERRIAR_INJADDR_L_SHIFT 1426 1427 #define CAN_ERRIAR_INJADDR_L(x) FLEXCAN_ERRIAR_INJADDR_L(x) 1428 1429 #define CAN_ERRIAR_INJADDR_H_MASK FLEXCAN_ERRIAR_INJADDR_H_MASK 1430 #define CAN_ERRIAR_INJADDR_H_SHIFT FLEXCAN_ERRIAR_INJADDR_H_SHIFT 1431 1432 #define CAN_ERRIAR_INJADDR_H(x) FLEXCAN_ERRIAR_INJADDR_H(x) 1433 /*! @} */ 1434 1435 /*! @name ERRIDPR - Error Injection Data Pattern Register */ 1436 /*! @{ */ 1437 1438 #define CAN_ERRIDPR_DFLIP_MASK FLEXCAN_ERRIDPR_DFLIP_MASK 1439 #define CAN_ERRIDPR_DFLIP_SHIFT FLEXCAN_ERRIDPR_DFLIP_SHIFT 1440 1441 #define CAN_ERRIDPR_DFLIP(x) FLEXCAN_ERRIDPR_DFLIP(x) 1442 /*! @} */ 1443 1444 /*! @name ERRIPPR - Error Injection Parity Pattern Register */ 1445 /*! @{ */ 1446 1447 #define CAN_ERRIPPR_PFLIP0_MASK FLEXCAN_ERRIPPR_PFLIP0_MASK 1448 #define CAN_ERRIPPR_PFLIP0_SHIFT FLEXCAN_ERRIPPR_PFLIP0_SHIFT 1449 1450 #define CAN_ERRIPPR_PFLIP0(x) FLEXCAN_ERRIPPR_PFLIP0(x) 1451 1452 #define CAN_ERRIPPR_PFLIP1_MASK FLEXCAN_ERRIPPR_PFLIP1_MASK 1453 #define CAN_ERRIPPR_PFLIP1_SHIFT FLEXCAN_ERRIPPR_PFLIP1_SHIFT 1454 1455 #define CAN_ERRIPPR_PFLIP1(x) FLEXCAN_ERRIPPR_PFLIP1(x) 1456 1457 #define CAN_ERRIPPR_PFLIP2_MASK FLEXCAN_ERRIPPR_PFLIP2_MASK 1458 #define CAN_ERRIPPR_PFLIP2_SHIFT FLEXCAN_ERRIPPR_PFLIP2_SHIFT 1459 1460 #define CAN_ERRIPPR_PFLIP2(x) FLEXCAN_ERRIPPR_PFLIP2(x) 1461 1462 #define CAN_ERRIPPR_PFLIP3_MASK FLEXCAN_ERRIPPR_PFLIP3_MASK 1463 #define CAN_ERRIPPR_PFLIP3_SHIFT FLEXCAN_ERRIPPR_PFLIP3_SHIFT 1464 1465 #define CAN_ERRIPPR_PFLIP3(x) FLEXCAN_ERRIPPR_PFLIP3(x) 1466 /*! @} */ 1467 1468 /*! @name RERRAR - Error Report Address Register */ 1469 /*! @{ */ 1470 1471 #define CAN_RERRAR_ERRADDR_MASK FLEXCAN_RERRAR_ERRADDR_MASK 1472 #define CAN_RERRAR_ERRADDR_SHIFT FLEXCAN_RERRAR_ERRADDR_SHIFT 1473 1474 #define CAN_RERRAR_ERRADDR(x) FLEXCAN_RERRAR_ERRADDR(x) 1475 1476 #define CAN_RERRAR_SAID_MASK FLEXCAN_RERRAR_SAID_MASK 1477 #define CAN_RERRAR_SAID_SHIFT FLEXCAN_RERRAR_SAID_SHIFT 1478 1479 #define CAN_RERRAR_SAID(x) FLEXCAN_RERRAR_SAID(x) 1480 1481 #define CAN_RERRAR_NCE_MASK FLEXCAN_RERRAR_NCE_MASK 1482 #define CAN_RERRAR_NCE_SHIFT FLEXCAN_RERRAR_NCE_SHIFT 1483 1484 #define CAN_RERRAR_NCE(x) FLEXCAN_RERRAR_NCE(x) 1485 /*! @} */ 1486 1487 /*! @name RERRDR - Error Report Data Register */ 1488 /*! @{ */ 1489 1490 #define CAN_RERRDR_RDATA_MASK FLEXCAN_RERRDR_RDATA_MASK 1491 #define CAN_RERRDR_RDATA_SHIFT FLEXCAN_RERRDR_RDATA_SHIFT 1492 1493 #define CAN_RERRDR_RDATA(x) FLEXCAN_RERRDR_RDATA(x) 1494 /*! @} */ 1495 1496 /*! @name RERRSYNR - Error Report Syndrome Register */ 1497 /*! @{ */ 1498 1499 #define CAN_RERRSYNR_SYND0_MASK FLEXCAN_RERRSYNR_SYND0_MASK 1500 #define CAN_RERRSYNR_SYND0_SHIFT FLEXCAN_RERRSYNR_SYND0_SHIFT 1501 1502 #define CAN_RERRSYNR_SYND0(x) FLEXCAN_RERRSYNR_SYND0(x) 1503 1504 #define CAN_RERRSYNR_BE0_MASK FLEXCAN_RERRSYNR_BE0_MASK 1505 #define CAN_RERRSYNR_BE0_SHIFT FLEXCAN_RERRSYNR_BE0_SHIFT 1506 1507 #define CAN_RERRSYNR_BE0(x) FLEXCAN_RERRSYNR_BE0(x) 1508 1509 #define CAN_RERRSYNR_SYND1_MASK FLEXCAN_RERRSYNR_SYND1_MASK 1510 #define CAN_RERRSYNR_SYND1_SHIFT FLEXCAN_RERRSYNR_SYND1_SHIFT 1511 1512 #define CAN_RERRSYNR_SYND1(x) FLEXCAN_RERRSYNR_SYND1(x) 1513 1514 #define CAN_RERRSYNR_BE1_MASK FLEXCAN_RERRSYNR_BE1_MASK 1515 #define CAN_RERRSYNR_BE1_SHIFT FLEXCAN_RERRSYNR_BE1_SHIFT 1516 1517 #define CAN_RERRSYNR_BE1(x) FLEXCAN_RERRSYNR_BE1(x) 1518 1519 #define CAN_RERRSYNR_SYND2_MASK FLEXCAN_RERRSYNR_SYND2_MASK 1520 #define CAN_RERRSYNR_SYND2_SHIFT FLEXCAN_RERRSYNR_SYND2_SHIFT 1521 1522 #define CAN_RERRSYNR_SYND2(x) FLEXCAN_RERRSYNR_SYND2(x) 1523 1524 #define CAN_RERRSYNR_BE2_MASK FLEXCAN_RERRSYNR_BE2_MASK 1525 #define CAN_RERRSYNR_BE2_SHIFT FLEXCAN_RERRSYNR_BE2_SHIFT 1526 1527 #define CAN_RERRSYNR_BE2(x) FLEXCAN_RERRSYNR_BE2(x) 1528 1529 #define CAN_RERRSYNR_SYND3_MASK FLEXCAN_RERRSYNR_SYND3_MASK 1530 #define CAN_RERRSYNR_SYND3_SHIFT FLEXCAN_RERRSYNR_SYND3_SHIFT 1531 1532 #define CAN_RERRSYNR_SYND3(x) FLEXCAN_RERRSYNR_SYND3(x) 1533 1534 #define CAN_RERRSYNR_BE3_MASK FLEXCAN_RERRSYNR_BE3_MASK 1535 #define CAN_RERRSYNR_BE3_SHIFT FLEXCAN_RERRSYNR_BE3_SHIFT 1536 1537 #define CAN_RERRSYNR_BE3(x) FLEXCAN_RERRSYNR_BE3(x) 1538 /*! @} */ 1539 1540 /*! @name ERRSR - Error Status Register */ 1541 /*! @{ */ 1542 1543 #define CAN_ERRSR_CEIOF_MASK FLEXCAN_ERRSR_CEIOF_MASK 1544 #define CAN_ERRSR_CEIOF_SHIFT FLEXCAN_ERRSR_CEIOF_SHIFT 1545 1546 #define CAN_ERRSR_CEIOF(x) FLEXCAN_ERRSR_CEIOF(x) 1547 1548 #define CAN_ERRSR_FANCEIOF_MASK FLEXCAN_ERRSR_FANCEIOF_MASK 1549 #define CAN_ERRSR_FANCEIOF_SHIFT FLEXCAN_ERRSR_FANCEIOF_SHIFT 1550 1551 #define CAN_ERRSR_FANCEIOF(x) FLEXCAN_ERRSR_FANCEIOF(x) 1552 1553 #define CAN_ERRSR_HANCEIOF_MASK FLEXCAN_ERRSR_HANCEIOF_MASK 1554 #define CAN_ERRSR_HANCEIOF_SHIFT FLEXCAN_ERRSR_HANCEIOF_SHIFT 1555 1556 #define CAN_ERRSR_HANCEIOF(x) FLEXCAN_ERRSR_HANCEIOF(x) 1557 1558 #define CAN_ERRSR_CEIF_MASK FLEXCAN_ERRSR_CEIF_MASK 1559 #define CAN_ERRSR_CEIF_SHIFT FLEXCAN_ERRSR_CEIF_SHIFT 1560 1561 #define CAN_ERRSR_CEIF(x) FLEXCAN_ERRSR_CEIF(x) 1562 1563 #define CAN_ERRSR_FANCEIF_MASK FLEXCAN_ERRSR_FANCEIF_MASK 1564 #define CAN_ERRSR_FANCEIF_SHIFT FLEXCAN_ERRSR_FANCEIF_SHIFT 1565 1566 #define CAN_ERRSR_FANCEIF(x) FLEXCAN_ERRSR_FANCEIF(x) 1567 1568 #define CAN_ERRSR_HANCEIF_MASK FLEXCAN_ERRSR_HANCEIF_MASK 1569 #define CAN_ERRSR_HANCEIF_SHIFT FLEXCAN_ERRSR_HANCEIF_SHIFT 1570 1571 #define CAN_ERRSR_HANCEIF(x) FLEXCAN_ERRSR_HANCEIF(x) 1572 /*! @} */ 1573 1574 /*! @name EPRS - Enhanced CAN Bit Timing Prescalers */ 1575 /*! @{ */ 1576 1577 #define CAN_EPRS_ENPRESDIV_MASK FLEXCAN_EPRS_ENPRESDIV_MASK 1578 #define CAN_EPRS_ENPRESDIV_SHIFT FLEXCAN_EPRS_ENPRESDIV_SHIFT 1579 1580 #define CAN_EPRS_ENPRESDIV(x) FLEXCAN_EPRS_ENPRESDIV(x) 1581 1582 #define CAN_EPRS_EDPRESDIV_MASK FLEXCAN_EPRS_EDPRESDIV_MASK 1583 #define CAN_EPRS_EDPRESDIV_SHIFT FLEXCAN_EPRS_EDPRESDIV_SHIFT 1584 1585 #define CAN_EPRS_EDPRESDIV(x) FLEXCAN_EPRS_EDPRESDIV(x) 1586 /*! @} */ 1587 1588 /*! @name ENCBT - Enhanced Nominal CAN Bit Timing */ 1589 /*! @{ */ 1590 1591 #define CAN_ENCBT_NTSEG1_MASK FLEXCAN_ENCBT_NTSEG1_MASK 1592 #define CAN_ENCBT_NTSEG1_SHIFT FLEXCAN_ENCBT_NTSEG1_SHIFT 1593 1594 #define CAN_ENCBT_NTSEG1(x) FLEXCAN_ENCBT_NTSEG1(x) 1595 1596 #define CAN_ENCBT_NTSEG2_MASK FLEXCAN_ENCBT_NTSEG2_MASK 1597 #define CAN_ENCBT_NTSEG2_SHIFT FLEXCAN_ENCBT_NTSEG2_SHIFT 1598 1599 #define CAN_ENCBT_NTSEG2(x) FLEXCAN_ENCBT_NTSEG2(x) 1600 1601 #define CAN_ENCBT_NRJW_MASK FLEXCAN_ENCBT_NRJW_MASK 1602 #define CAN_ENCBT_NRJW_SHIFT FLEXCAN_ENCBT_NRJW_SHIFT 1603 1604 #define CAN_ENCBT_NRJW(x) FLEXCAN_ENCBT_NRJW(x) 1605 /*! @} */ 1606 1607 /*! @name EDCBT - Enhanced Data Phase CAN bit Timing */ 1608 /*! @{ */ 1609 1610 #define CAN_EDCBT_DTSEG1_MASK FLEXCAN_EDCBT_DTSEG1_MASK 1611 #define CAN_EDCBT_DTSEG1_SHIFT FLEXCAN_EDCBT_DTSEG1_SHIFT 1612 1613 #define CAN_EDCBT_DTSEG1(x) FLEXCAN_EDCBT_DTSEG1(x) 1614 1615 #define CAN_EDCBT_DTSEG2_MASK FLEXCAN_EDCBT_DTSEG2_MASK 1616 #define CAN_EDCBT_DTSEG2_SHIFT FLEXCAN_EDCBT_DTSEG2_SHIFT 1617 1618 #define CAN_EDCBT_DTSEG2(x) FLEXCAN_EDCBT_DTSEG2(x) 1619 1620 #define CAN_EDCBT_DRJW_MASK FLEXCAN_EDCBT_DRJW_MASK 1621 #define CAN_EDCBT_DRJW_SHIFT FLEXCAN_EDCBT_DRJW_SHIFT 1622 1623 #define CAN_EDCBT_DRJW(x) FLEXCAN_EDCBT_DRJW(x) 1624 /*! @} */ 1625 1626 /*! @name ETDC - Enhanced Transceiver Delay Compensation */ 1627 /*! @{ */ 1628 1629 #define CAN_ETDC_ETDCVAL_MASK FLEXCAN_ETDC_ETDCVAL_MASK 1630 #define CAN_ETDC_ETDCVAL_SHIFT FLEXCAN_ETDC_ETDCVAL_SHIFT 1631 1632 #define CAN_ETDC_ETDCVAL(x) FLEXCAN_ETDC_ETDCVAL(x) 1633 1634 #define CAN_ETDC_ETDCFAIL_MASK FLEXCAN_ETDC_ETDCFAIL_MASK 1635 #define CAN_ETDC_ETDCFAIL_SHIFT FLEXCAN_ETDC_ETDCFAIL_SHIFT 1636 1637 #define CAN_ETDC_ETDCFAIL(x) FLEXCAN_ETDC_ETDCFAIL(x) 1638 1639 #define CAN_ETDC_ETDCOFF_MASK FLEXCAN_ETDC_ETDCOFF_MASK 1640 #define CAN_ETDC_ETDCOFF_SHIFT FLEXCAN_ETDC_ETDCOFF_SHIFT 1641 1642 #define CAN_ETDC_ETDCOFF(x) FLEXCAN_ETDC_ETDCOFF(x) 1643 1644 #define CAN_ETDC_TDMDIS_MASK FLEXCAN_ETDC_TDMDIS_MASK 1645 #define CAN_ETDC_TDMDIS_SHIFT FLEXCAN_ETDC_TDMDIS_SHIFT 1646 1647 #define CAN_ETDC_TDMDIS(x) FLEXCAN_ETDC_TDMDIS(x) 1648 1649 #define CAN_ETDC_ETDCEN_MASK FLEXCAN_ETDC_ETDCEN_MASK 1650 #define CAN_ETDC_ETDCEN_SHIFT FLEXCAN_ETDC_ETDCEN_SHIFT 1651 1652 #define CAN_ETDC_ETDCEN(x) FLEXCAN_ETDC_ETDCEN(x) 1653 /*! @} */ 1654 1655 /*! @name FDCTRL - CAN FD Control Register */ 1656 /*! @{ */ 1657 1658 #define CAN_FDCTRL_TDCVAL_MASK FLEXCAN_FDCTRL_TDCVAL_MASK 1659 #define CAN_FDCTRL_TDCVAL_SHIFT FLEXCAN_FDCTRL_TDCVAL_SHIFT 1660 1661 #define CAN_FDCTRL_TDCVAL(x) FLEXCAN_FDCTRL_TDCVAL(x) 1662 1663 #define CAN_FDCTRL_TDCOFF_MASK FLEXCAN_FDCTRL_TDCOFF_MASK 1664 #define CAN_FDCTRL_TDCOFF_SHIFT FLEXCAN_FDCTRL_TDCOFF_SHIFT 1665 1666 #define CAN_FDCTRL_TDCOFF(x) FLEXCAN_FDCTRL_TDCOFF(x) 1667 1668 #define CAN_FDCTRL_TDCFAIL_MASK FLEXCAN_FDCTRL_TDCFAIL_MASK 1669 #define CAN_FDCTRL_TDCFAIL_SHIFT FLEXCAN_FDCTRL_TDCFAIL_SHIFT 1670 1671 #define CAN_FDCTRL_TDCFAIL(x) FLEXCAN_FDCTRL_TDCFAIL(x) 1672 1673 #define CAN_FDCTRL_TDCEN_MASK FLEXCAN_FDCTRL_TDCEN_MASK 1674 #define CAN_FDCTRL_TDCEN_SHIFT FLEXCAN_FDCTRL_TDCEN_SHIFT 1675 1676 #define CAN_FDCTRL_TDCEN(x) FLEXCAN_FDCTRL_TDCEN(x) 1677 1678 #define CAN_FDCTRL_MBDSR0_MASK FLEXCAN_FDCTRL_MBDSR0_MASK 1679 #define CAN_FDCTRL_MBDSR0_SHIFT FLEXCAN_FDCTRL_MBDSR0_SHIFT 1680 1681 #define CAN_FDCTRL_MBDSR0(x) FLEXCAN_FDCTRL_MBDSR0(x) 1682 1683 #define CAN_FDCTRL_MBDSR1_MASK FLEXCAN_FDCTRL_MBDSR1_MASK 1684 #define CAN_FDCTRL_MBDSR1_SHIFT FLEXCAN_FDCTRL_MBDSR1_SHIFT 1685 1686 #define CAN_FDCTRL_MBDSR1(x) FLEXCAN_FDCTRL_MBDSR1(x) 1687 1688 #define CAN_FDCTRL_MBDSR2_MASK FLEXCAN_FDCTRL_MBDSR2_MASK 1689 #define CAN_FDCTRL_MBDSR2_SHIFT FLEXCAN_FDCTRL_MBDSR2_SHIFT 1690 1691 #define CAN_FDCTRL_MBDSR2(x) FLEXCAN_FDCTRL_MBDSR2(x) 1692 1693 #define CAN_FDCTRL_MBDSR3_MASK FLEXCAN_FDCTRL_MBDSR3_MASK 1694 #define CAN_FDCTRL_MBDSR3_SHIFT FLEXCAN_FDCTRL_MBDSR3_SHIFT 1695 1696 #define CAN_FDCTRL_MBDSR3(x) FLEXCAN_FDCTRL_MBDSR3(x) 1697 1698 #define CAN_FDCTRL_FDRATE_MASK FLEXCAN_FDCTRL_FDRATE_MASK 1699 #define CAN_FDCTRL_FDRATE_SHIFT FLEXCAN_FDCTRL_FDRATE_SHIFT 1700 1701 #define CAN_FDCTRL_FDRATE(x) FLEXCAN_FDCTRL_FDRATE(x) 1702 /*! @} */ 1703 1704 /*! @name FDCBT - CAN FD Bit Timing Register */ 1705 /*! @{ */ 1706 1707 #define CAN_FDCBT_FPSEG2_MASK FLEXCAN_FDCBT_FPSEG2_MASK 1708 #define CAN_FDCBT_FPSEG2_SHIFT FLEXCAN_FDCBT_FPSEG2_SHIFT 1709 1710 #define CAN_FDCBT_FPSEG2(x) FLEXCAN_FDCBT_FPSEG2(x) 1711 1712 #define CAN_FDCBT_FPSEG1_MASK FLEXCAN_FDCBT_FPSEG1_MASK 1713 #define CAN_FDCBT_FPSEG1_SHIFT FLEXCAN_FDCBT_FPSEG1_SHIFT 1714 1715 #define CAN_FDCBT_FPSEG1(x) FLEXCAN_FDCBT_FPSEG1(x) 1716 1717 #define CAN_FDCBT_FPROPSEG_MASK FLEXCAN_FDCBT_FPROPSEG_MASK 1718 #define CAN_FDCBT_FPROPSEG_SHIFT FLEXCAN_FDCBT_FPROPSEG_SHIFT 1719 1720 #define CAN_FDCBT_FPROPSEG(x) FLEXCAN_FDCBT_FPROPSEG(x) 1721 1722 #define CAN_FDCBT_FRJW_MASK FLEXCAN_FDCBT_FRJW_MASK 1723 #define CAN_FDCBT_FRJW_SHIFT FLEXCAN_FDCBT_FRJW_SHIFT 1724 1725 #define CAN_FDCBT_FRJW(x) FLEXCAN_FDCBT_FRJW(x) 1726 1727 #define CAN_FDCBT_FPRESDIV_MASK FLEXCAN_FDCBT_FPRESDIV_MASK 1728 #define CAN_FDCBT_FPRESDIV_SHIFT FLEXCAN_FDCBT_FPRESDIV_SHIFT 1729 1730 #define CAN_FDCBT_FPRESDIV(x) FLEXCAN_FDCBT_FPRESDIV(x) 1731 /*! @} */ 1732 1733 /*! @name FDCRC - CAN FD CRC Register */ 1734 /*! @{ */ 1735 1736 #define CAN_FDCRC_FD_TXCRC_MASK FLEXCAN_FDCRC_FD_TXCRC_MASK 1737 #define CAN_FDCRC_FD_TXCRC_SHIFT FLEXCAN_FDCRC_FD_TXCRC_SHIFT 1738 1739 #define CAN_FDCRC_FD_TXCRC(x) FLEXCAN_FDCRC_FD_TXCRC(x) 1740 1741 #define CAN_FDCRC_FD_MBCRC_MASK FLEXCAN_FDCRC_FD_MBCRC_MASK 1742 #define CAN_FDCRC_FD_MBCRC_SHIFT FLEXCAN_FDCRC_FD_MBCRC_SHIFT 1743 1744 #define CAN_FDCRC_FD_MBCRC(x) FLEXCAN_FDCRC_FD_MBCRC(x) 1745 /*! @} */ 1746 1747 /*! @name ERFCR - Enhanced Rx FIFO Control Register */ 1748 /*! @{ */ 1749 1750 #define CAN_ERFCR_ERFWM_MASK FLEXCAN_ERFCR_ERFWM_MASK 1751 #define CAN_ERFCR_ERFWM_SHIFT FLEXCAN_ERFCR_ERFWM_SHIFT 1752 1753 #define CAN_ERFCR_ERFWM(x) FLEXCAN_ERFCR_ERFWM(x) 1754 1755 #define CAN_ERFCR_NFE_MASK FLEXCAN_ERFCR_NFE_MASK 1756 #define CAN_ERFCR_NFE_SHIFT FLEXCAN_ERFCR_NFE_SHIFT 1757 1758 #define CAN_ERFCR_NFE(x) FLEXCAN_ERFCR_NFE(x) 1759 1760 #define CAN_ERFCR_NEXIF_MASK FLEXCAN_ERFCR_NEXIF_MASK 1761 #define CAN_ERFCR_NEXIF_SHIFT FLEXCAN_ERFCR_NEXIF_SHIFT 1762 1763 #define CAN_ERFCR_NEXIF(x) FLEXCAN_ERFCR_NEXIF(x) 1764 1765 #define CAN_ERFCR_DMALW_MASK FLEXCAN_ERFCR_DMALW_MASK 1766 #define CAN_ERFCR_DMALW_SHIFT FLEXCAN_ERFCR_DMALW_SHIFT 1767 1768 #define CAN_ERFCR_DMALW(x) FLEXCAN_ERFCR_DMALW(x) 1769 1770 #define CAN_ERFCR_ERFEN_MASK FLEXCAN_ERFCR_ERFEN_MASK 1771 #define CAN_ERFCR_ERFEN_SHIFT FLEXCAN_ERFCR_ERFEN_SHIFT 1772 1773 #define CAN_ERFCR_ERFEN(x) FLEXCAN_ERFCR_ERFEN(x) 1774 /*! @} */ 1775 1776 /*! @name ERFIER - Enhanced Rx FIFO Interrupt Enable Register */ 1777 /*! @{ */ 1778 1779 #define CAN_ERFIER_ERFDAIE_MASK FLEXCAN_ERFIER_ERFDAIE_MASK 1780 #define CAN_ERFIER_ERFDAIE_SHIFT FLEXCAN_ERFIER_ERFDAIE_SHIFT 1781 1782 #define CAN_ERFIER_ERFDAIE(x) FLEXCAN_ERFIER_ERFDAIE(x) 1783 1784 #define CAN_ERFIER_ERFWMIIE_MASK FLEXCAN_ERFIER_ERFWMIIE_MASK 1785 #define CAN_ERFIER_ERFWMIIE_SHIFT FLEXCAN_ERFIER_ERFWMIIE_SHIFT 1786 1787 #define CAN_ERFIER_ERFWMIIE(x) FLEXCAN_ERFIER_ERFWMIIE(x) 1788 1789 #define CAN_ERFIER_ERFOVFIE_MASK FLEXCAN_ERFIER_ERFOVFIE_MASK 1790 #define CAN_ERFIER_ERFOVFIE_SHIFT FLEXCAN_ERFIER_ERFOVFIE_SHIFT 1791 1792 #define CAN_ERFIER_ERFOVFIE(x) FLEXCAN_ERFIER_ERFOVFIE(x) 1793 1794 #define CAN_ERFIER_ERFUFWIE_MASK FLEXCAN_ERFIER_ERFUFWIE_MASK 1795 #define CAN_ERFIER_ERFUFWIE_SHIFT FLEXCAN_ERFIER_ERFUFWIE_SHIFT 1796 1797 #define CAN_ERFIER_ERFUFWIE(x) FLEXCAN_ERFIER_ERFUFWIE(x) 1798 /*! @} */ 1799 1800 /*! @name ERFSR - Enhanced Rx FIFO Status Register */ 1801 /*! @{ */ 1802 1803 #define CAN_ERFSR_ERFEL_MASK FLEXCAN_ERFSR_ERFEL_MASK 1804 #define CAN_ERFSR_ERFEL_SHIFT FLEXCAN_ERFSR_ERFEL_SHIFT 1805 1806 #define CAN_ERFSR_ERFEL(x) FLEXCAN_ERFSR_ERFEL(x) 1807 1808 #define CAN_ERFSR_ERFF_MASK FLEXCAN_ERFSR_ERFF_MASK 1809 #define CAN_ERFSR_ERFF_SHIFT FLEXCAN_ERFSR_ERFF_SHIFT 1810 1811 #define CAN_ERFSR_ERFF(x) FLEXCAN_ERFSR_ERFF(x) 1812 1813 #define CAN_ERFSR_ERFE_MASK FLEXCAN_ERFSR_ERFE_MASK 1814 #define CAN_ERFSR_ERFE_SHIFT FLEXCAN_ERFSR_ERFE_SHIFT 1815 1816 #define CAN_ERFSR_ERFE(x) FLEXCAN_ERFSR_ERFE(x) 1817 1818 #define CAN_ERFSR_ERFCLR_MASK FLEXCAN_ERFSR_ERFCLR_MASK 1819 #define CAN_ERFSR_ERFCLR_SHIFT FLEXCAN_ERFSR_ERFCLR_SHIFT 1820 1821 #define CAN_ERFSR_ERFCLR(x) FLEXCAN_ERFSR_ERFCLR(x) 1822 1823 #define CAN_ERFSR_ERFDA_MASK FLEXCAN_ERFSR_ERFDA_MASK 1824 #define CAN_ERFSR_ERFDA_SHIFT FLEXCAN_ERFSR_ERFDA_SHIFT 1825 1826 #define CAN_ERFSR_ERFDA(x) FLEXCAN_ERFSR_ERFDA(x) 1827 1828 #define CAN_ERFSR_ERFWMI_MASK FLEXCAN_ERFSR_ERFWMI_MASK 1829 #define CAN_ERFSR_ERFWMI_SHIFT FLEXCAN_ERFSR_ERFWMI_SHIFT 1830 1831 #define CAN_ERFSR_ERFWMI(x) FLEXCAN_ERFSR_ERFWMI(x) 1832 1833 #define CAN_ERFSR_ERFOVF_MASK FLEXCAN_ERFSR_ERFOVF_MASK 1834 #define CAN_ERFSR_ERFOVF_SHIFT FLEXCAN_ERFSR_ERFOVF_SHIFT 1835 1836 #define CAN_ERFSR_ERFOVF(x) FLEXCAN_ERFSR_ERFOVF(x) 1837 1838 #define CAN_ERFSR_ERFUFW_MASK FLEXCAN_ERFSR_ERFUFW_MASK 1839 #define CAN_ERFSR_ERFUFW_SHIFT FLEXCAN_ERFSR_ERFUFW_SHIFT 1840 1841 #define CAN_ERFSR_ERFUFW(x) FLEXCAN_ERFSR_ERFUFW(x) 1842 /*! @} */ 1843 1844 /*! @name HR_TIME_STAMP - High Resolution Time Stamp */ 1845 /*! @{ */ 1846 1847 #define CAN_HR_TIME_STAMP_TS_MASK FLEXCAN_HR_TIME_STAMP_TS_MASK 1848 #define CAN_HR_TIME_STAMP_TS_SHIFT FLEXCAN_HR_TIME_STAMP_TS_SHIFT 1849 1850 #define CAN_HR_TIME_STAMP_TS(x) FLEXCAN_HR_TIME_STAMP_TS(x) 1851 /*! @} */ 1852 1853 /* The count of CAN_HR_TIME_STAMP */ 1854 #define CAN_HR_TIME_STAMP_COUNT (128U) 1855 1856 /*! @name ERFFEL - Enhanced Rx FIFO Filter Element */ 1857 /*! @{ */ 1858 1859 #define CAN_ERFFEL_FEL_MASK FLEXCAN_ERFFEL_FEL_MASK 1860 #define CAN_ERFFEL_FEL_SHIFT FLEXCAN_ERFFEL_FEL_SHIFT 1861 1862 #define CAN_ERFFEL_FEL(x) FLEX_CAN_ERFFEL_FEL(x) 1863 /*! @} */ 1864 1865 /* The count of CAN_ERFFEL */ 1866 #define CAN_ERFFEL_COUNT (128U) 1867 1868 /* ---------------------------------------------------------------------------- 1869 -- DMA Peripheral Access Layer 1870 ---------------------------------------------------------------------------- */ 1871 1872 /*! 1873 * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer 1874 * @{ 1875 */ 1876 1877 /** DMA - Register Layout Typedef */ 1878 typedef struct { 1879 __IO uint32_t MP_CSR; /**< Management Page Control, offset: 0x0 */ 1880 __I uint32_t MP_ES; /**< Management Page Error Status, offset: 0x4 */ 1881 __I uint32_t MP_INT; /**< Management Page Interrupt Request Status, offset: 0x8 */ 1882 __I uint32_t MP_HRS; /**< Management Page Hardware Request Status, offset: 0xC */ 1883 uint8_t RESERVED_0[240]; 1884 __IO uint32_t CH_GRPRI[32]; /**< Channel Arbitration Group, array offset: 0x100, array step: 0x4 */ 1885 uint8_t RESERVED_1[196224]; 1886 struct { /* offset: 0x10000, array step: 0x10000 */ 1887 __IO uint32_t CH_CSR; /**< Channel Control and Status, array offset: 0x0, array step: 0x10000, irregular array, not all indices are valid */ 1888 __IO uint32_t CH_ES; /**< Channel Error Status, array offset: 0x4, array step: 0x10000, irregular array, not all indices are valid */ 1889 __IO uint32_t CH_INT; /**< Channel Interrupt Status, array offset: 0x8, array step: 0x10000, irregular array, not all indices are valid */ 1890 __IO uint32_t CH_SBR; /**< Channel System Bus, array offset: 0xC, array step: 0x10000, irregular array, not all indices are valid */ 1891 __IO uint32_t CH_PRI; /**< Channel Priority, array offset: 0x10, array step: 0x10000, irregular array, not all indices are valid */ 1892 uint8_t RESERVED_0[12]; 1893 __IO uint32_t TCD_SADDR; /**< TCD Source Address, array offset: 0x20, array step: 0x10000, irregular array, not all indices are valid */ 1894 __IO uint16_t TCD_SOFF; /**< TCD Signed Source Address Offset, array offset: 0x24, array step: 0x10000, irregular array, not all indices are valid */ 1895 __IO uint16_t TCD_ATTR; /**< TCD Transfer Attributes, array offset: 0x26, array step: 0x10000, irregular array, not all indices are valid */ 1896 union { /* offset: 0x1028, array step: 0x1000 */ 1897 __IO uint32_t TCD_NBYTES_MLOFFNO; /**< TCD Transfer Size Without Minor Loop Offsets, array offset: 0x1028, array step: 0x1000, irregular array, not all indices are valid */ 1898 __IO uint32_t TCD_NBYTES_MLOFFYES; /**< TCD Transfer Size with Minor Loop Offsets, array offset: 0x1028, array step: 0x1000, irregular array, not all indices are valid */ 1899 }; 1900 __IO uint32_t TCD_SLAST_SDA; /**< TCD Last Source Address Adjustment / Store DADDR Address, array offset: 0x2C, array step: 0x10000, irregular array, not all indices are valid */ 1901 __IO uint32_t TCD_DADDR; /**< TCD Destination Address, array offset: 0x30, array step: 0x10000, irregular array, not all indices are valid */ 1902 __IO uint16_t TCD_DOFF; /**< TCD Signed Destination Address Offset, array offset: 0x34, array step: 0x10000, irregular array, not all indices are valid */ 1903 union { /* offset: 0x1036, array step: 0x1000 */ 1904 __IO uint16_t TCD_CITER_ELINKNO; /**< TCD Current Major Loop Count (Minor Loop Channel Linking Disabled), array offset: 0x1036, array step: 0x1000, irregular array, not all indices are valid */ 1905 __IO uint16_t TCD_CITER_ELINKYES; /**< TCD Current Major Loop Count (Minor Loop Channel Linking Enabled), array offset: 0x1036, array step: 0x1000, irregular array, not all indices are valid */ 1906 }; 1907 __IO uint32_t TCD_DLAST_SGA; /**< TCD Last Destination Address Adjustment / Scatter Gather Address, array offset: 0x38, array step: 0x10000, irregular array, not all indices are valid */ 1908 __IO uint16_t TCD_CSR; /**< TCD Control and Status, array offset: 0x3C, array step: 0x10000, irregular array, not all indices are valid */ 1909 union { /* offset: 0x103E, array step: 0x1000 */ 1910 __IO uint16_t TCD_BITER_ELINKNO; /**< TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled), array offset: 0x103E, array step: 0x1000, irregular array, not all indices are valid */ 1911 __IO uint16_t TCD_BITER_ELINKYES; /**< TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled), array offset: 0x103E, array step: 0x1000, irregular array, not all indices are valid */ 1912 }; 1913 uint8_t RESERVED_1[65472]; 1914 } CH[32]; 1915 } DMA_Type; 1916 1917 /* ---------------------------------------------------------------------------- 1918 -- EDMA3_MP Register Masks 1919 ---------------------------------------------------------------------------- */ 1920 1921 /*! 1922 * @addtogroup EDMA3_MP_Register_Masks EDMA3_MP Register Masks 1923 * @{ 1924 */ 1925 1926 /*! @name CSR - Management Page Control */ 1927 /*! @{ */ 1928 1929 #define DMA_MP_CSR_EDBG_MASK EDMA3_MP_CSR_EDBG_MASK 1930 #define DMA_MP_CSR_EDBG_SHIFT EDMA3_MP_CSR_EDBG_SHIFT 1931 #define DMA_MP_CSR_EDBG_WIDTH EDMA3_MP_CSR_EDBG_WIDTH 1932 #define DMA_MP_CSR_EDBG(x) EDMA3_MP_CSR_EDBG(x) 1933 1934 #define DMA_MP_CSR_ERCA_MASK EDMA3_MP_CSR_ERCA_MASK 1935 #define DMA_MP_CSR_ERCA_SHIFT EDMA3_MP_CSR_ERCA_SHIFT 1936 #define DMA_MP_CSR_ERCA_WIDTH EDMA3_MP_CSR_ERCA_WIDTH 1937 #define DMA_MP_CSR_ERCA(x) EDMA3_MP_CSR_ERCA(x) 1938 1939 #define DMA_MP_CSR_HAE_MASK EDMA3_MP_CSR_HAE_MASK 1940 #define DMA_MP_CSR_HAE_SHIFT EDMA3_MP_CSR_HAE_SHIFT 1941 #define DMA_MP_CSR_HAE_WIDTH EDMA3_MP_CSR_HAE_WIDTH 1942 #define DMA_MP_CSR_HAE(x) EDMA3_MP_CSR_HAE(x) 1943 1944 #define DMA_MP_CSR_HALT_MASK EDMA3_MP_CSR_HALT_MASK 1945 #define DMA_MP_CSR_HALT_SHIFT EDMA3_MP_CSR_HALT_SHIFT 1946 #define DMA_MP_CSR_HALT_WIDTH EDMA3_MP_CSR_HALT_WIDTH 1947 #define DMA_MP_CSR_HALT(x) EDMA3_MP_CSR_HALT(x) 1948 1949 #define DMA_MP_CSR_GCLC_MASK EDMA3_MP_CSR_GCLC_MASK 1950 #define DMA_MP_CSR_GCLC_SHIFT EDMA3_MP_CSR_GCLC_SHIFT 1951 #define DMA_MP_CSR_GCLC_WIDTH EDMA3_MP_CSR_GCLC_WIDTH 1952 #define DMA_MP_CSR_GCLC(x) EDMA3_MP_CSR_GCLC(x) 1953 1954 #define DMA_MP_CSR_GMRC_MASK EDMA3_MP_CSR_GMRC_MASK 1955 #define DMA_MP_CSR_GMRC_SHIFT EDMA3_MP_CSR_GMRC_SHIFT 1956 #define DMA_MP_CSR_GMRC_WIDTH EDMA3_MP_CSR_GMRC_WIDTH 1957 #define DMA_MP_CSR_GMRC(x) EDMA3_MP_CSR_GMRC(x) 1958 1959 #define DMA_MP_CSR_ECX_MASK EDMA3_MP_CSR_ECX_MASK 1960 #define DMA_MP_CSR_ECX_SHIFT EDMA3_MP_CSR_ECX_SHIFT 1961 #define DMA_MP_CSR_ECX_WIDTH EDMA3_MP_CSR_ECX_WIDTH 1962 #define DMA_MP_CSR_ECX(x) EDMA3_MP_CSR_ECX(x) 1963 1964 #define DMA_MP_CSR_CX_MASK EDMA3_MP_CSR_CX_MASK 1965 #define DMA_MP_CSR_CX_SHIFT EDMA3_MP_CSR_CX_SHIFT 1966 #define DMA_MP_CSR_CX_WIDTH EDMA3_MP_CSR_CX_WIDTH 1967 #define DMA_MP_CSR_CX(x) EDMA3_MP_CSR_CX(x) 1968 1969 #define DMA_MP_CSR_ACTIVE_ID_MASK EDMA3_MP_CSR_ACTIVE_ID_MASK 1970 #define DMA_MP_CSR_ACTIVE_ID_SHIFT EDMA3_MP_CSR_ACTIVE_ID_SHIFT 1971 #define DMA_MP_CSR_ACTIVE_ID_WIDTH EDMA3_MP_CSR_ACTIVE_ID_WIDTH 1972 #define DMA_MP_CSR_ACTIVE_ID(x) EDMA3_MP_CSR_ACTIVE_ID(x) 1973 1974 #define DMA_MP_CSR_ACTIVE_MASK EDMA3_MP_CSR_ACTIVE_MASK 1975 #define DMA_MP_CSR_ACTIVE_SHIFT EDMA3_MP_CSR_ACTIVE_SHIFT 1976 #define DMA_MP_CSR_ACTIVE_WIDTH EDMA3_MP_CSR_ACTIVE_WIDTH 1977 #define DMA_MP_CSR_ACTIVE(x) EDMA3_MP_CSR_ACTIVE(x) 1978 1979 #define DMA_MP_CSR_EBW_MASK EDMA3_TCD_CH_CSR_EBW_MASK 1980 #define DMA_MP_CSR_EBW_SHIFT EDMA3_TCD_CH_CSR_EBW_SHIFT 1981 #define DMA_MP_CSR_EBW_WIDTH EDMA3_TCD_CH_CSR_EBW_WIDTH 1982 #define DMA_MP_CSR_EBW(x) EDMA3_TCD_CH_CSR_EBW(x) 1983 /*! @} */ 1984 1985 /*! @name ES - Management Page Error Status */ 1986 /*! @{ */ 1987 1988 #define DMA_MP_ES_DBE_MASK EDMA3_MP_ES_DBE_MASK 1989 #define DMA_MP_ES_DBE_SHIFT EDMA3_MP_ES_DBE_SHIFT 1990 #define DMA_MP_ES_DBE_WIDTH EDMA3_MP_ES_DBE_WIDTH 1991 #define DMA_MP_ES_DBE(x) EDMA3_MP_ES_DBE(x) 1992 1993 #define DMA_MP_ES_SBE_MASK EDMA3_MP_ES_SBE_MASK 1994 #define DMA_MP_ES_SBE_SHIFT EDMA3_MP_ES_SBE_SHIFT 1995 #define DMA_MP_ES_SBE_WIDTH EDMA3_MP_ES_SBE_WIDTH 1996 #define DMA_MP_ES_SBE(x) EDMA3_MP_ES_SBE(x) 1997 1998 #define DMA_MP_ES_SGE_MASK EDMA3_MP_ES_SGE_MASK 1999 #define DMA_MP_ES_SGE_SHIFT EDMA3_MP_ES_SGE_SHIFT 2000 #define DMA_MP_ES_SGE_WIDTH EDMA3_MP_ES_SGE_WIDTH 2001 #define DMA_MP_ES_SGE(x) EDMA3_MP_ES_SGE(x) 2002 2003 #define DMA_MP_ES_NCE_MASK EDMA3_MP_ES_NCE_MASK 2004 #define DMA_MP_ES_NCE_SHIFT EDMA3_MP_ES_NCE_SHIFT 2005 #define DMA_MP_ES_NCE_WIDTH EDMA3_MP_ES_NCE_WIDTH 2006 #define DMA_MP_ES_NCE(x) EDMA3_MP_ES_NCE(x) 2007 2008 #define DMA_MP_ES_DOE_MASK EDMA3_MP_ES_DOE_MASK 2009 #define DMA_MP_ES_DOE_SHIFT EDMA3_MP_ES_DOE_SHIFT 2010 #define DMA_MP_ES_DOE_WIDTH EDMA3_MP_ES_DOE_WIDTH 2011 #define DMA_MP_ES_DOE(x) EDMA3_MP_ES_DOE(x) 2012 2013 #define DMA_MP_ES_DAE_MASK EDMA3_MP_ES_DAE_MASK 2014 #define DMA_MP_ES_DAE_SHIFT EDMA3_MP_ES_DAE_SHIFT 2015 #define DMA_MP_ES_DAE_WIDTH EDMA3_MP_ES_DAE_WIDTH 2016 #define DMA_MP_ES_DAE(x) EDMA3_MP_ES_DAE(x) 2017 2018 #define DMA_MP_ES_SOE_MASK EDMA3_MP_ES_SOE_MASK 2019 #define DMA_MP_ES_SOE_SHIFT EDMA3_MP_ES_SOE_SHIFT 2020 #define DMA_MP_ES_SOE_WIDTH EDMA3_MP_ES_SOE_WIDTH 2021 #define DMA_MP_ES_SOE(x) EDMA3_MP_ES_SOE(x) 2022 2023 #define DMA_MP_ES_SAE_MASK EDMA3_MP_ES_SAE_MASK 2024 #define DMA_MP_ES_SAE_SHIFT EDMA3_MP_ES_SAE_SHIFT 2025 #define DMA_MP_ES_SAE_WIDTH EDMA3_MP_ES_SAE_WIDTH 2026 #define DMA_MP_ES_SAE(x) EDMA3_MP_ES_SAE(x) 2027 2028 #define DMA_MP_ES_ECX_MASK EDMA3_MP_ES_ECX_MASK 2029 #define DMA_MP_ES_ECX_SHIFT EDMA3_MP_ES_ECX_SHIFT 2030 #define DMA_MP_ES_ECX_WIDTH EDMA3_MP_ES_ECX_WIDTH 2031 #define DMA_MP_ES_ECX(x) EDMA3_MP_ES_ECX(x) 2032 2033 #define DMA_MP_ES_UCE_MASK EDMA3_MP_ES_UCE_MASK 2034 #define DMA_MP_ES_UCE_SHIFT EDMA3_MP_ES_UCE_SHIFT 2035 #define DMA_MP_ES_UCE_WIDTH EDMA3_MP_ES_UCE_WIDTH 2036 #define DMA_MP_ES_UCE(x) EDMA3_MP_ES_UCE(x) 2037 2038 #define DMA_MP_ES_ERRCHN_MASK EDMA3_MP_ES_ERRCHN_MASK 2039 #define DMA_MP_ES_ERRCHN_SHIFT EDMA3_MP_ES_ERRCHN_SHIFT 2040 #define DMA_MP_ES_ERRCHN_WIDTH EDMA3_MP_ES_ERRCHN_WIDTH 2041 #define DMA_MP_ES_ERRCHN(x) EDMA3_MP_ES_ERRCHN(x) 2042 2043 #define DMA_MP_ES_VLD_MASK EDMA3_MP_ES_VLD_MASK 2044 #define DMA_MP_ES_VLD_SHIFT EDMA3_MP_ES_VLD_SHIFT 2045 #define DMA_MP_ES_VLD_WIDTH EDMA3_MP_ES_VLD_WIDTH 2046 #define DMA_MP_ES_VLD(x) EDMA3_MP_ES_VLD(x) 2047 /*! @} */ 2048 2049 /*! @name INT - Management Page Interrupt Request Status */ 2050 /*! @{ */ 2051 2052 #define DMA_MP_INT_INT_MASK EDMA3_MP_INT_INT_MASK 2053 #define DMA_MP_INT_INT_SHIFT EDMA3_MP_INT_INT_SHIFT 2054 #define DMA_MP_INT_INT_WIDTH EDMA3_MP_INT_INT_WIDTH 2055 #define DMA_MP_INT_INT(x) EDMA3_MP_INT_INT(x) 2056 /*! @} */ 2057 2058 /*! @name HRS - Management Page Hardware Request Status */ 2059 /*! @{ */ 2060 2061 #define DMA_MP_HRS_HRS_MASK EDMA3_MP_HRS_HRS_MASK 2062 #define DMA_MP_HRS_HRS_SHIFT EDMA3_MP_HRS_HRS_SHIFT 2063 #define DMA_MP_HRS_HRS_WIDTH EDMA3_MP_HRS_HRS_WIDTH 2064 #define DMA_MP_HRS_HRS(x) EDMA3_MP_HRS_HRS(x) 2065 /*! @} */ 2066 2067 /*! @name CH_GRPRI - Channel Arbitration Group */ 2068 /*! @{ */ 2069 2070 #define DMA_CH_GRPRI_GRPRI_MASK EDMA3_MP_CH_GRPRI_GRPRI_MASK 2071 #define DMA_CH_GRPRI_GRPRI_SHIFT EDMA3_MP_CH_GRPRI_GRPRI_SHIFT 2072 #define DMA_CH_GRPRI_GRPRI_WIDTH EDMA3_MP_CH_GRPRI_GRPRI_WIDTH 2073 #define DMA_CH_GRPRI_GRPRI(x) EDMA3_MP_CH_GRPRI_GRPRI(x) 2074 2075 /*! 2076 * @} 2077 */ /* end of group EDMA3_MP_Register_Masks */ 2078 2079 /* ---------------------------------------------------------------------------- 2080 -- EDMA3_TCD Register Masks 2081 ---------------------------------------------------------------------------- */ 2082 2083 /*! 2084 * @addtogroup EDMA3_TCD_Register_Masks EDMA3_TCD Register Masks 2085 * @{ 2086 */ 2087 2088 /*! @name CH_CSR - Channel Control and Status */ 2089 /*! @{ */ 2090 2091 #define DMA_CH_CSR_ERQ_MASK EDMA3_TCD_CH_CSR_ERQ_MASK 2092 #define DMA_CH_CSR_ERQ_SHIFT EDMA3_TCD_CH_CSR_ERQ_SHIFT 2093 #define DMA_CH_CSR_ERQ_WIDTH EDMA3_TCD_CH_CSR_ERQ_WIDTH 2094 #define DMA_CH_CSR_ERQ(x) EDMA3_TCD_CH_CSR_ERQ(x) 2095 2096 #define DMA_CH_CSR_EARQ_MASK EDMA3_TCD_CH_CSR_EARQ_MASK 2097 #define DMA_CH_CSR_EARQ_SHIFT EDMA3_TCD_CH_CSR_EARQ_SHIFT 2098 #define DMA_CH_CSR_EARQ_WIDTH EDMA3_TCD_CH_CSR_EARQ_WIDTH 2099 #define DMA_CH_CSR_EARQ(x) EDMA3_TCD_CH_CSR_EARQ(x) 2100 2101 #define DMA_CH_CSR_EEI_MASK EDMA3_TCD_CH_CSR_EEI_MASK 2102 #define DMA_CH_CSR_EEI_SHIFT EDMA3_TCD_CH_CSR_EEI_SHIFT 2103 #define DMA_CH_CSR_EEI_WIDTH EDMA3_TCD_CH_CSR_EEI_WIDTH 2104 #define DMA_CH_CSR_EEI(x) EDMA3_TCD_CH_CSR_EEI(x) 2105 2106 #define DMA_CH_CSR_EBW_MASK EDMA3_TCD_CH_CSR_EBW_MASK 2107 #define DMA_CH_CSR_EBW_SHIFT EDMA3_TCD_CH_CSR_EBW_SHIFT 2108 #define DMA_CH_CSR_EBW_WIDTH EDMA3_TCD_CH_CSR_EBW_WIDTH 2109 #define DMA_CH_CSR_EBW(x) EDMA3_TCD_CH_CSR_EBW(x) 2110 2111 #define DMA_CH_CSR_DONE_MASK EDMA3_TCD_CH_CSR_DONE_MASK 2112 #define DMA_CH_CSR_DONE_SHIFT EDMA3_TCD_CH_CSR_DONE_SHIFT 2113 #define DMA_CH_CSR_DONE_WIDTH EDMA3_TCD_CH_CSR_DONE_WIDTH 2114 #define DMA_CH_CSR_DONE(x) EDMA3_TCD_CH_CSR_DONE(x) 2115 2116 #define DMA_CH_CSR_ACTIVE_MASK EDMA3_TCD_CH_CSR_ACTIVE_MASK 2117 #define DMA_CH_CSR_ACTIVE_SHIFT EDMA3_TCD_CH_CSR_ACTIVE_SHIFT 2118 #define DMA_CH_CSR_ACTIVE_WIDTH EDMA3_TCD_CH_CSR_ACTIVE_WIDTH 2119 #define DMA_CH_CSR_ACTIVE(x) EDMA3_TCD_CH_CSR_ACTIVE(x) 2120 /*! @} */ 2121 2122 /*! @name CH_ES - Channel Error Status */ 2123 /*! @{ */ 2124 2125 #define DMA_CH_ES_DBE_MASK EDMA3_TCD_CH_ES_DBE_MASK 2126 #define DMA_CH_ES_DBE_SHIFT EDMA3_TCD_CH_ES_DBE_SHIFT 2127 #define DMA_CH_ES_DBE_WIDTH EDMA3_TCD_CH_ES_DBE_WIDTH 2128 #define DMA_CH_ES_DBE(x) EDMA3_TCD_CH_ES_DBE(x) 2129 2130 #define DMA_CH_ES_SBE_MASK EDMA3_TCD_CH_ES_SBE_MASK 2131 #define DMA_CH_ES_SBE_SHIFT EDMA3_TCD_CH_ES_SBE_SHIFT 2132 #define DMA_CH_ES_SBE_WIDTH EDMA3_TCD_CH_ES_SBE_WIDTH 2133 #define DMA_CH_ES_SBE(x) EDMA3_TCD_CH_ES_SBE(x) 2134 2135 #define DMA_CH_ES_SGE_MASK EDMA3_TCD_CH_ES_SGE_MASK 2136 #define DMA_CH_ES_SGE_SHIFT EDMA3_TCD_CH_ES_SGE_SHIFT 2137 #define DMA_CH_ES_SGE_WIDTH EDMA3_TCD_CH_ES_SGE_WIDTH 2138 #define DMA_CH_ES_SGE(x) EDMA3_TCD_CH_ES_SGE(x) 2139 2140 #define DMA_CH_ES_NCE_MASK EDMA3_TCD_CH_ES_NCE_MASK 2141 #define DMA_CH_ES_NCE_SHIFT EDMA3_TCD_CH_ES_NCE_SHIFT 2142 #define DMA_CH_ES_NCE_WIDTH EDMA3_TCD_CH_ES_NCE_WIDTH 2143 #define DMA_CH_ES_NCE(x) EDMA3_TCD_CH_ES_NCE(x) 2144 2145 #define DMA_CH_ES_DOE_MASK EDMA3_TCD_CH_ES_DOE_MASK 2146 #define DMA_CH_ES_DOE_SHIFT EDMA3_TCD_CH_ES_DOE_SHIFT 2147 #define DMA_CH_ES_DOE_WIDTH EDMA3_TCD_CH_ES_DOE_WIDTH 2148 #define DMA_CH_ES_DOE(x) EDMA3_TCD_CH_ES_DOE(x) 2149 2150 #define DMA_CH_ES_DAE_MASK EDMA3_TCD_CH_ES_DAE_MASK 2151 #define DMA_CH_ES_DAE_SHIFT EDMA3_TCD_CH_ES_DAE_SHIFT 2152 #define DMA_CH_ES_DAE_WIDTH EDMA3_TCD_CH_ES_DAE_WIDTH 2153 #define DMA_CH_ES_DAE(x) EDMA3_TCD_CH_ES_DAE(x) 2154 2155 #define DMA_CH_ES_SOE_MASK EDMA3_TCD_CH_ES_SOE_MASK 2156 #define DMA_CH_ES_SOE_SHIFT EDMA3_TCD_CH_ES_SOE_SHIFT 2157 #define DMA_CH_ES_SOE_WIDTH EDMA3_TCD_CH_ES_SOE_WIDTH 2158 #define DMA_CH_ES_SOE(x) EDMA3_TCD_CH_ES_SOE(x) 2159 2160 #define DMA_CH_ES_SAE_MASK EDMA3_TCD_CH_ES_SAE_MASK 2161 #define DMA_CH_ES_SAE_SHIFT EDMA3_TCD_CH_ES_SAE_SHIFT 2162 #define DMA_CH_ES_SAE_WIDTH EDMA3_TCD_CH_ES_SAE_WIDTH 2163 #define DMA_CH_ES_SAE(x) EDMA3_TCD_CH_ES_SAE(x) 2164 2165 #define DMA_CH_ES_ERR_MASK EDMA3_TCD_CH_ES_ERR_MASK 2166 #define DMA_CH_ES_ERR_SHIFT EDMA3_TCD_CH_ES_ERR_SHIFT 2167 #define DMA_CH_ES_ERR_WIDTH EDMA3_TCD_CH_ES_ERR_WIDTH 2168 #define DMA_CH_ES_ERR(x) EDMA3_TCD_CH_ES_ERR(x) 2169 /*! @} */ 2170 2171 /*! @name CH_INT - Channel Interrupt Status */ 2172 /*! @{ */ 2173 2174 #define DMA_CH_INT_INT_MASK EDMA3_TCD_CH_INT_INT_MASK 2175 #define DMA_CH_INT_INT_SHIFT EDMA3_TCD_CH_INT_INT_SHIFT 2176 #define DMA_CH_INT_INT_WIDTH EDMA3_TCD_CH_INT_INT_WIDTH 2177 #define DMA_CH_INT_INT(x) EDMA3_TCD_CH_INT_INT(x) 2178 /*! @} */ 2179 2180 /*! @name CH_SBR - Channel System Bus */ 2181 /*! @{ */ 2182 2183 #define DMA_CH_SBR_MID_MASK EDMA3_TCD_CH_SBR_MID_MASK 2184 #define DMA_CH_SBR_MID_SHIFT EDMA3_TCD_CH_SBR_MID_SHIFT 2185 #define DMA_CH_SBR_MID_WIDTH EDMA3_TCD_CH_SBR_MID_WIDTH 2186 #define DMA_CH_SBR_MID(x) EDMA3_TCD_CH_SBR_MID(x) 2187 2188 #define DMA_CH_SBR_PAL_MASK EDMA3_TCD_CH_SBR_PAL_MASK 2189 #define DMA_CH_SBR_PAL_SHIFT EDMA3_TCD_CH_SBR_PAL_SHIFT 2190 #define DMA_CH_SBR_PAL_WIDTH EDMA3_TCD_CH_SBR_PAL_WIDTH 2191 #define DMA_CH_SBR_PAL(x) EDMA3_TCD_CH_SBR_PAL(x) 2192 2193 #define DMA_CH_SBR_EMI_MASK EDMA3_TCD_CH_SBR_EMI_MASK 2194 #define DMA_CH_SBR_EMI_SHIFT EDMA3_TCD_CH_SBR_EMI_SHIFT 2195 #define DMA_CH_SBR_EMI_WIDTH EDMA3_TCD_CH_SBR_EMI_WIDTH 2196 #define DMA_CH_SBR_EMI(x) EDMA3_TCD_CH_SBR_EMI(x) 2197 2198 #define DMA_CH_SBR_ATTR_MASK EDMA3_TCD_CH_SBR_ATTR_MASK 2199 #define DMA_CH_SBR_ATTR_SHIFT EDMA3_TCD_CH_SBR_ATTR_SHIFT 2200 #define DMA_CH_SBR_ATTR_WIDTH EDMA3_TCD_CH_SBR_ATTR_WIDTH 2201 #define DMA_CH_SBR_ATTR(x) EDMA3_TCD_CH_SBR_ATTR(x) 2202 /*! @} */ 2203 2204 /*! @name CH_PRI - Channel Priority */ 2205 /*! @{ */ 2206 2207 #define DMA_CH_PRI_APL_MASK EDMA3_TCD_CH_PRI_APL_MASK 2208 #define DMA_CH_PRI_APL_SHIFT EDMA3_TCD_CH_PRI_APL_SHIFT 2209 #define DMA_CH_PRI_APL_WIDTH EDMA3_TCD_CH_PRI_APL_WIDTH 2210 #define DMA_CH_PRI_APL(x) EDMA3_TCD_CH_PRI_APL(x) 2211 2212 #define DMA_CH_PRI_DPA_MASK EDMA3_TCD_CH_PRI_DPA_MASK 2213 #define DMA_CH_PRI_DPA_SHIFT EDMA3_TCD_CH_PRI_DPA_SHIFT 2214 #define DMA_CH_PRI_DPA_WIDTH EDMA3_TCD_CH_PRI_DPA_WIDTH 2215 #define DMA_CH_PRI_DPA(x) EDMA3_TCD_CH_PRI_DPA(x) 2216 2217 #define DMA_CH_PRI_ECP_MASK EDMA3_TCD_CH_PRI_ECP_MASK 2218 #define DMA_CH_PRI_ECP_SHIFT EDMA3_TCD_CH_PRI_ECP_SHIFT 2219 #define DMA_CH_PRI_ECP_WIDTH EDMA3_TCD_CH_PRI_ECP_WIDTH 2220 #define DMA_CH_PRI_ECP(x) EDMA3_TCD_CH_PRI_ECP(x) 2221 /*! @} */ 2222 2223 /*! @name SADDR - TCD Source Address */ 2224 /*! @{ */ 2225 2226 #define DMA_TCD_SADDR_SADDR_MASK EDMA3_TCD_SADDR_SADDR_MASK 2227 #define DMA_TCD_SADDR_SADDR_SHIFT EDMA3_TCD_SADDR_SADDR_SHIFT 2228 #define DMA_TCD_SADDR_SADDR_WIDTH EDMA3_TCD_SADDR_SADDR_WIDTH 2229 #define DMA_TCD_SADDR_SADDR(x) EDMA3_TCD_SADDR_SADDR(x) 2230 /*! @} */ 2231 2232 /*! @name SOFF - TCD Signed Source Address Offset */ 2233 /*! @{ */ 2234 2235 #define DMA_TCD_SOFF_SOFF_MASK EDMA3_TCD_SOFF_SOFF_MASK 2236 #define DMA_TCD_SOFF_SOFF_SHIFT EDMA3_TCD_SOFF_SOFF_SHIFT 2237 #define DMA_TCD_SOFF_SOFF_WIDTH EDMA3_TCD_SOFF_SOFF_WIDTH 2238 #define DMA_TCD_SOFF_SOFF(x) EDMA3_TCD_SOFF_SOFF(x) 2239 /*! @} */ 2240 2241 /*! @name ATTR - TCD Transfer Attributes */ 2242 /*! @{ */ 2243 2244 #define DMA_TCD_ATTR_DSIZE_MASK EDMA3_TCD_ATTR_DSIZE_MASK 2245 #define DMA_TCD_ATTR_DSIZE_SHIFT EDMA3_TCD_ATTR_DSIZE_SHIFT 2246 #define DMA_TCD_ATTR_DSIZE_WIDTH EDMA3_TCD_ATTR_DSIZE_WIDTH 2247 #define DMA_TCD_ATTR_DSIZE(x) EDMA3_TCD_ATTR_DSIZE(x) 2248 2249 #define DMA_TCD_ATTR_DMOD_MASK EDMA3_TCD_ATTR_DMOD_MASK 2250 #define DMA_TCD_ATTR_DMOD_SHIFT EDMA3_TCD_ATTR_DMOD_SHIFT 2251 #define DMA_TCD_ATTR_DMOD_WIDTH EDMA3_TCD_ATTR_DMOD_WIDTH 2252 #define DMA_TCD_ATTR_DMOD(x) EDMA3_TCD_ATTR_DMOD(x) 2253 2254 #define DMA_TCD_ATTR_SSIZE_MASK EDMA3_TCD_ATTR_SSIZE_MASK 2255 #define DMA_TCD_ATTR_SSIZE_SHIFT EDMA3_TCD_ATTR_SSIZE_SHIFT 2256 #define DMA_TCD_ATTR_SSIZE_WIDTH EDMA3_TCD_ATTR_SSIZE_WIDTH 2257 #define DMA_TCD_ATTR_SSIZE(x) EDMA3_TCD_ATTR_SSIZE(x) 2258 2259 #define DMA_TCD_ATTR_SMOD_MASK EDMA3_TCD_ATTR_SMOD_MASK 2260 #define DMA_TCD_ATTR_SMOD_SHIFT EDMA3_TCD_ATTR_SMOD_SHIFT 2261 #define DMA_TCD_ATTR_SMOD_WIDTH EDMA3_TCD_ATTR_SMOD_WIDTH 2262 #define DMA_TCD_ATTR_SMOD(x) EDMA3_TCD_ATTR_SMOD(x) 2263 /*! @} */ 2264 2265 /*! @name NBYTES_MLOFFNO - TCD Transfer Size Without Minor Loop Offsets */ 2266 /*! @{ */ 2267 2268 #define DMA_TCD_NBYTES_MLOFFNO_NBYTES_MASK EDMA3_TCD_NBYTES_MLOFFNO_NBYTES_MASK 2269 #define DMA_TCD_NBYTES_MLOFFNO_NBYTES_SHIFT EDMA3_TCD_NBYTES_MLOFFNO_NBYTES_SHIFT 2270 #define DMA_TCD_NBYTES_MLOFFNO_NBYTES_WIDTH EDMA3_TCD_NBYTES_MLOFFNO_NBYTES_WIDTH 2271 #define DMA_TCD_NBYTES_MLOFFNO_NBYTES(x) EDMA3_TCD_NBYTES_MLOFFNO_NBYTES(x) 2272 2273 #define DMA_TCD_NBYTES_MLOFFNO_DMLOE_MASK EDMA3_TCD_NBYTES_MLOFFNO_DMLOE_MASK 2274 #define DMA_TCD_NBYTES_MLOFFNO_DMLOE_SHIFT EDMA3_TCD_NBYTES_MLOFFNO_DMLOE_SHIFT 2275 #define DMA_TCD_NBYTES_MLOFFNO_DMLOE_WIDTH EDMA3_TCD_NBYTES_MLOFFNO_DMLOE_WIDTH 2276 #define DMA_TCD_NBYTES_MLOFFNO_DMLOE(x) EDMA3_TCD_NBYTES_MLOFFNO_DMLOE(x) 2277 2278 #define DMA_TCD_NBYTES_MLOFFNO_SMLOE_MASK EDMA3_TCD_NBYTES_MLOFFNO_SMLOE_MASK 2279 #define DMA_TCD_NBYTES_MLOFFNO_SMLOE_SHIFT EDMA3_TCD_NBYTES_MLOFFNO_SMLOE_SHIFT 2280 #define DMA_TCD_NBYTES_MLOFFNO_SMLOE_WIDTH EDMA3_TCD_NBYTES_MLOFFNO_SMLOE_WIDTH 2281 #define DMA_TCD_NBYTES_MLOFFNO_SMLOE(x) EDMA3_TCD_NBYTES_MLOFFNO_SMLOE(x) 2282 /*! @} */ 2283 2284 /*! @name NBYTES_MLOFFYES - TCD Transfer Size with Minor Loop Offsets */ 2285 /*! @{ */ 2286 2287 #define DMA_TCD_NBYTES_MLOFFYES_NBYTES_MASK EDMA3_TCD_NBYTES_MLOFFYES_NBYTES_MASK 2288 #define DMA_TCD_NBYTES_MLOFFYES_NBYTES_SHIFT EDMA3_TCD_NBYTES_MLOFFYES_NBYTES_SHIFT 2289 #define DMA_TCD_NBYTES_MLOFFYES_NBYTES_WIDTH EDMA3_TCD_NBYTES_MLOFFYES_NBYTES_WIDTH 2290 #define DMA_TCD_NBYTES_MLOFFYES_NBYTES(x) EDMA3_TCD_NBYTES_MLOFFYES_NBYTES(x) 2291 2292 #define DMA_TCD_NBYTES_MLOFFYES_MLOFF_MASK EDMA3_TCD_NBYTES_MLOFFYES_MLOFF_MASK 2293 #define DMA_TCD_NBYTES_MLOFFYES_MLOFF_SHIFT EDMA3_TCD_NBYTES_MLOFFYES_MLOFF_SHIFT 2294 #define DMA_TCD_NBYTES_MLOFFYES_MLOFF_WIDTH EDMA3_TCD_NBYTES_MLOFFYES_MLOFF_WIDTH 2295 #define DMA_TCD_NBYTES_MLOFFYES_MLOFF(x) EDMA3_TCD_NBYTES_MLOFFYES_MLOFF(x) 2296 2297 #define DMA_TCD_NBYTES_MLOFFYES_DMLOE_MASK EDMA3_TCD_NBYTES_MLOFFYES_DMLOE_MASK 2298 #define DMA_TCD_NBYTES_MLOFFYES_DMLOE_SHIFT EDMA3_TCD_NBYTES_MLOFFYES_DMLOE_SHIFT 2299 #define DMA_TCD_NBYTES_MLOFFYES_DMLOE_WIDTH EDMA3_TCD_NBYTES_MLOFFYES_DMLOE_WIDTH 2300 #define DMA_TCD_NBYTES_MLOFFYES_DMLOE(x) EDMA3_TCD_NBYTES_MLOFFYES_DMLOE(x) 2301 2302 #define DMA_TCD_NBYTES_MLOFFYES_SMLOE_MASK EDMA3_TCD_NBYTES_MLOFFYES_SMLOE_MASK 2303 #define DMA_TCD_NBYTES_MLOFFYES_SMLOE_SHIFT EDMA3_TCD_NBYTES_MLOFFYES_SMLOE_SHIFT 2304 #define DMA_TCD_NBYTES_MLOFFYES_SMLOE_WIDTH EDMA3_TCD_NBYTES_MLOFFYES_SMLOE_WIDTH 2305 #define DMA_TCD_NBYTES_MLOFFYES_SMLOE(x) EDMA3_TCD_NBYTES_MLOFFYES_SMLOE(x) 2306 /*! @} */ 2307 2308 /*! @name SLAST_SDA - TCD Last Source Address Adjustment / Store DADDR Address */ 2309 /*! @{ */ 2310 2311 #define DMA_TCD_SLAST_SDA_SLAST_SDA_MASK EDMA3_TCD_SLAST_SDA_SLAST_SDA_MASK 2312 #define DMA_TCD_SLAST_SDA_SLAST_SDA_SHIFT EDMA3_TCD_SLAST_SDA_SLAST_SDA_SHIFT 2313 #define DMA_TCD_SLAST_SDA_SLAST_SDA_WIDTH EDMA3_TCD_SLAST_SDA_SLAST_SDA_WIDTH 2314 #define DMA_TCD_SLAST_SDA_SLAST_SDA(x) EDMA3_TCD_SLAST_SDA_SLAST_SDA(x) 2315 /*! @} */ 2316 2317 /*! @name DADDR - TCD Destination Address */ 2318 /*! @{ */ 2319 2320 #define DMA_TCD_DADDR_DADDR_MASK EDMA3_TCD_DADDR_DADDR_MASK 2321 #define DMA_TCD_DADDR_DADDR_SHIFT EDMA3_TCD_DADDR_DADDR_SHIFT 2322 #define DMA_TCD_DADDR_DADDR_WIDTH EDMA3_TCD_DADDR_DADDR_WIDTH 2323 #define DMA_TCD_DADDR_DADDR(x) EDMA3_TCD_DADDR_DADDR(x) 2324 /*! @} */ 2325 2326 /*! @name DOFF - TCD Signed Destination Address Offset */ 2327 /*! @{ */ 2328 2329 #define DMA_TCD_DOFF_DOFF_MASK EDMA3_TCD_DOFF_DOFF_MASK 2330 #define DMA_TCD_DOFF_DOFF_SHIFT EDMA3_TCD_DOFF_DOFF_SHIFT 2331 #define DMA_TCD_DOFF_DOFF_WIDTH EDMA3_TCD_DOFF_DOFF_WIDTH 2332 #define DMA_TCD_DOFF_DOFF(x) EDMA3_TCD_DOFF_DOFF(x) 2333 /*! @} */ 2334 2335 /*! @name CITER_ELINKNO - TCD Current Major Loop Count (Minor Loop Channel Linking Disabled) */ 2336 /*! @{ */ 2337 2338 #define DMA_TCD_CITER_ELINKNO_CITER_MASK EDMA3_TCD_CITER_ELINKNO_CITER_MASK 2339 #define DMA_TCD_CITER_ELINKNO_CITER_SHIFT EDMA3_TCD_CITER_ELINKNO_CITER_SHIFT 2340 #define DMA_TCD_CITER_ELINKNO_CITER_WIDTH EDMA3_TCD_CITER_ELINKNO_CITER_WIDTH 2341 #define DMA_TCD_CITER_ELINKNO_CITER(x) EDMA3_TCD_CITER_ELINKNO_CITER(x) 2342 2343 #define DMA_TCD_CITER_ELINKNO_ELINK_MASK EDMA3_TCD_CITER_ELINKNO_ELINK_MASK 2344 #define DMA_TCD_CITER_ELINKNO_ELINK_SHIFT EDMA3_TCD_CITER_ELINKNO_ELINK_SHIFT 2345 #define DMA_TCD_CITER_ELINKNO_ELINK_WIDTH EDMA3_TCD_CITER_ELINKNO_ELINK_WIDTH 2346 #define DMA_TCD_CITER_ELINKNO_ELINK(x) EDMA3_TCD_CITER_ELINKNO_ELINK(x) 2347 /*! @} */ 2348 2349 /*! @name CITER_ELINKYES - TCD Current Major Loop Count (Minor Loop Channel Linking Enabled) */ 2350 /*! @{ */ 2351 2352 #define DMA_TCD_CITER_ELINKYES_CITER_MASK EDMA3_TCD_CITER_ELINKYES_CITER_MASK 2353 #define DMA_TCD_CITER_ELINKYES_CITER_SHIFT EDMA3_TCD_CITER_ELINKYES_CITER_SHIFT 2354 #define DMA_TCD_CITER_ELINKYES_CITER_WIDTH EDMA3_TCD_CITER_ELINKYES_CITER_WIDTH 2355 #define DMA_TCD_CITER_ELINKYES_CITER(x) EDMA3_TCD_CITER_ELINKYES_CITER(x) 2356 2357 #define DMA_TCD_CITER_ELINKYES_LINKCH_MASK EDMA3_TCD_CITER_ELINKYES_LINKCH_MASK 2358 #define DMA_TCD_CITER_ELINKYES_LINKCH_SHIFT EDMA3_TCD_CITER_ELINKYES_LINKCH_SHIFT 2359 #define DMA_TCD_CITER_ELINKYES_LINKCH_WIDTH EDMA3_TCD_CITER_ELINKYES_LINKCH_WIDTH 2360 #define DMA_TCD_CITER_ELINKYES_LINKCH(x) EDMA3_TCD_CITER_ELINKYES_LINKCH(x) 2361 2362 #define DMA_TCD_CITER_ELINKYES_ELINK_MASK EDMA3_TCD_CITER_ELINKYES_ELINK_MASK 2363 #define DMA_TCD_CITER_ELINKYES_ELINK_SHIFT EDMA3_TCD_CITER_ELINKYES_ELINK_SHIFT 2364 #define DMA_TCD_CITER_ELINKYES_ELINK_WIDTH EDMA3_TCD_CITER_ELINKYES_ELINK_WIDTH 2365 #define DMA_TCD_CITER_ELINKYES_ELINK(x) EDMA3_TCD_CITER_ELINKYES_ELINK(x) 2366 /*! @} */ 2367 2368 /*! @name DLAST_SGA - TCD Last Destination Address Adjustment / Scatter Gather Address */ 2369 /*! @{ */ 2370 2371 #define DMA_TCD_DLAST_SGA_DLAST_SGA_MASK EDMA3_TCD_DLAST_SGA_DLAST_SGA_MASK 2372 #define DMA_TCD_DLAST_SGA_DLAST_SGA_SHIFT EDMA3_TCD_DLAST_SGA_DLAST_SGA_SHIFT 2373 #define DMA_TCD_DLAST_SGA_DLAST_SGA_WIDTH EDMA3_TCD_DLAST_SGA_DLAST_SGA_WIDTH 2374 #define DMA_TCD_DLAST_SGA_DLAST_SGA(x) EDMA3_TCD_DLAST_SGA_DLAST_SGA(x) 2375 /*! @} */ 2376 2377 /*! @name CSR - TCD Control and Status */ 2378 /*! @{ */ 2379 2380 #define DMA_TCD_CSR_START_MASK EDMA3_TCD_CSR_START_MASK 2381 #define DMA_TCD_CSR_START_SHIFT EDMA3_TCD_CSR_START_SHIFT 2382 #define DMA_TCD_CSR_START_WIDTH EDMA3_TCD_CSR_START_WIDTH 2383 #define DMA_TCD_CSR_START(x) EDMA3_TCD_CSR_START(x) 2384 2385 #define DMA_TCD_CSR_INTMAJOR_MASK EDMA3_TCD_CSR_INTMAJOR_MASK 2386 #define DMA_TCD_CSR_INTMAJOR_SHIFT EDMA3_TCD_CSR_INTMAJOR_SHIFT 2387 #define DMA_TCD_CSR_INTMAJOR_WIDTH EDMA3_TCD_CSR_INTMAJOR_WIDTH 2388 #define DMA_TCD_CSR_INTMAJOR(x) EDMA3_TCD_CSR_INTMAJOR(x) 2389 2390 #define DMA_TCD_CSR_INTHALF_MASK EDMA3_TCD_CSR_INTHALF_MASK 2391 #define DMA_TCD_CSR_INTHALF_SHIFT EDMA3_TCD_CSR_INTHALF_SHIFT 2392 #define DMA_TCD_CSR_INTHALF_WIDTH EDMA3_TCD_CSR_INTHALF_WIDTH 2393 #define DMA_TCD_CSR_INTHALF(x) EDMA3_TCD_CSR_INTHALF(x) 2394 2395 #define DMA_TCD_CSR_DREQ_MASK EDMA3_TCD_CSR_DREQ_MASK 2396 #define DMA_TCD_CSR_DREQ_SHIFT EDMA3_TCD_CSR_DREQ_SHIFT 2397 #define DMA_TCD_CSR_DREQ_WIDTH EDMA3_TCD_CSR_DREQ_WIDTH 2398 #define DMA_TCD_CSR_DREQ(x) EDMA3_TCD_CSR_DREQ(x) 2399 2400 #define DMA_TCD_CSR_ESG_MASK EDMA3_TCD_CSR_ESG_MASK 2401 #define DMA_TCD_CSR_ESG_SHIFT EDMA3_TCD_CSR_ESG_SHIFT 2402 #define DMA_TCD_CSR_ESG_WIDTH EDMA3_TCD_CSR_ESG_WIDTH 2403 #define DMA_TCD_CSR_ESG(x) EDMA3_TCD_CSR_ESG(x) 2404 2405 #define DMA_TCD_CSR_MAJORELINK_MASK EDMA3_TCD_CSR_MAJORELINK_MASK 2406 #define DMA_TCD_CSR_MAJORELINK_SHIFT EDMA3_TCD_CSR_MAJORELINK_SHIFT 2407 #define DMA_TCD_CSR_MAJORELINK_WIDTH EDMA3_TCD_CSR_MAJORELINK_WIDTH 2408 #define DMA_TCD_CSR_MAJORELINK(x) EDMA3_TCD_CSR_MAJORELINK(x) 2409 2410 #define DMA_TCD_CSR_ESDA_MASK EDMA3_TCD_CSR_ESDA_MASK 2411 #define DMA_TCD_CSR_ESDA_SHIFT EDMA3_TCD_CSR_ESDA_SHIFT 2412 #define DMA_TCD_CSR_ESDA_WIDTH EDMA3_TCD_CSR_ESDA_WIDTH 2413 #define DMA_TCD_CSR_ESDA(x) EDMA3_TCD_CSR_ESDA(x) 2414 2415 #define DMA_TCD_CSR_MAJORLINKCH_MASK EDMA3_TCD_CSR_MAJORLINKCH_MASK 2416 #define DMA_TCD_CSR_MAJORLINKCH_SHIFT EDMA3_TCD_CSR_MAJORLINKCH_SHIFT 2417 #define DMA_TCD_CSR_MAJORLINKCH_WIDTH EDMA3_TCD_CSR_MAJORLINKCH_WIDTH 2418 #define DMA_TCD_CSR_MAJORLINKCH(x) EDMA3_TCD_CSR_MAJORLINKCH(x) 2419 2420 #define DMA_TCD_CSR_BWC_MASK EDMA3_TCD_CSR_BWC_MASK 2421 #define DMA_TCD_CSR_BWC_SHIFT EDMA3_TCD_CSR_BWC_SHIFT 2422 #define DMA_TCD_CSR_BWC_WIDTH EDMA3_TCD_CSR_BWC_WIDTH 2423 #define DMA_TCD_CSR_BWC(x) EDMA3_TCD_CSR_BWC(x) 2424 /*! @} */ 2425 2426 /*! @name BITER_ELINKNO - TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled) */ 2427 /*! @{ */ 2428 2429 #define DMA_TCD_BITER_ELINKNO_BITER_MASK EDMA3_TCD_BITER_ELINKNO_BITER_MASK 2430 #define DMA_TCD_BITER_ELINKNO_BITER_SHIFT EDMA3_TCD_BITER_ELINKNO_BITER_SHIFT 2431 #define DMA_TCD_BITER_ELINKNO_BITER_WIDTH EDMA3_TCD_BITER_ELINKNO_BITER_WIDTH 2432 #define DMA_TCD_BITER_ELINKNO_BITER(x) EDMA3_TCD_BITER_ELINKNO_BITER(x) 2433 2434 #define DMA_TCD_BITER_ELINKNO_ELINK_MASK EDMA3_TCD_BITER_ELINKNO_ELINK_MASK 2435 #define DMA_TCD_BITER_ELINKNO_ELINK_SHIFT EDMA3_TCD_BITER_ELINKNO_ELINK_SHIFT 2436 #define DMA_TCD_BITER_ELINKNO_ELINK_WIDTH EDMA3_TCD_BITER_ELINKNO_ELINK_WIDTH 2437 #define DMA_TCD_BITER_ELINKNO_ELINK(x) EDMA3_TCD_BITER_ELINKNO_ELINK(x) 2438 /*! @} */ 2439 2440 /*! @name BITER_ELINKYES - TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled) */ 2441 /*! @{ */ 2442 2443 #define DMA_TCD_BITER_ELINKYES_BITER_MASK EDMA3_TCD_BITER_ELINKYES_BITER_MASK 2444 #define DMA_TCD_BITER_ELINKYES_BITER_SHIFT EDMA3_TCD_BITER_ELINKYES_BITER_SHIFT 2445 #define DMA_TCD_BITER_ELINKYES_BITER_WIDTH EDMA3_TCD_BITER_ELINKYES_BITER_WIDTH 2446 #define DMA_TCD_BITER_ELINKYES_BITER(x) EDMA3_TCD_BITER_ELINKYES_BITER(x) 2447 2448 #define DMA_TCD_BITER_ELINKYES_LINKCH_MASK EDMA3_TCD_BITER_ELINKYES_LINKCH_MASK 2449 #define DMA_TCD_BITER_ELINKYES_LINKCH_SHIFT EDMA3_TCD_BITER_ELINKYES_LINKCH_SHIFT 2450 #define DMA_TCD_BITER_ELINKYES_LINKCH_WIDTH EDMA3_TCD_BITER_ELINKYES_LINKCH_WIDTH 2451 #define DMA_TCD_BITER_ELINKYES_LINKCH(x) EDMA3_TCD_BITER_ELINKYES_LINKCH(x) 2452 2453 #define DMA_TCD_BITER_ELINKYES_ELINK_MASK EDMA3_TCD_BITER_ELINKYES_ELINK_MASK 2454 #define DMA_TCD_BITER_ELINKYES_ELINK_SHIFT EDMA3_TCD_BITER_ELINKYES_ELINK_SHIFT 2455 #define DMA_TCD_BITER_ELINKYES_ELINK_WIDTH EDMA3_TCD_BITER_ELINKYES_ELINK_WIDTH 2456 #define DMA_TCD_BITER_ELINKYES_ELINK(x) EDMA3_TCD_BITER_ELINKYES_ELINK(x) 2457 /*! @} */ 2458 2459 /*! 2460 * @addtogroup DMAMUX_Register_Masks DMAMUX Register Masks 2461 * @{ 2462 */ 2463 2464 #define DMAMUX_CHCFG_SOURCE_MASK DMAMUX_CHCONF_SOURCE_MASK 2465 #define DMAMUX_CHCFG_SOURCE_SHIFT DMAMUX_CHCONF_SOURCE_SHIFT 2466 #define DMAMUX_CHCFG_SOURCE_WIDTH DMAMUX_CHCONF_SOURCE_WIDTH 2467 #define DMAMUX_CHCFG_SOURCE(x) DMAMUX_CHCONF_SOURCE(x) 2468 2469 #define DMAMUX_CHCFG_TRIG_MASK DMAMUX_CHCONF_TRIG_MASK 2470 #define DMAMUX_CHCFG_TRIG_SHIFT DMAMUX_CHCONF_TRIG_SHIFT 2471 #define DMAMUX_CHCFG_TRIG_WIDTH DMAMUX_CHCONF_TRIG_WIDTH 2472 #define DMAMUX_CHCFG_TRIG(x) DMAMUX_CHCONF_TRIG(x) 2473 2474 #define DMAMUX_CHCFG_ENBL_MASK DMAMUX_CHCONF_ENBL_MASK 2475 #define DMAMUX_CHCFG_ENBL_SHIFT DMAMUX_CHCONF_ENBL_SHIFT 2476 #define DMAMUX_CHCFG_ENBL_WIDTH DMAMUX_CHCONF_ENBL_WIDTH 2477 #define DMAMUX_CHCFG_ENBL(x) DMAMUX_CHCONF_ENBL(x) 2478 2479 /* ---------------------------------------------------------------------------- 2480 -- DSPI Peripheral Access Layer 2481 ---------------------------------------------------------------------------- */ 2482 2483 /*! 2484 * @addtogroup DSPI_Peripheral_Access_Layer DSPI Peripheral Access Layer 2485 * @{ 2486 */ 2487 2488 /** DSPI - Register Layout Typedef */ 2489 2490 typedef struct { 2491 __IO uint32_t MCR; /**< Module Configuration Register, offset: 0x0 */ 2492 uint8_t RESERVED_0[4]; 2493 __IO uint32_t TCR; /**< Transfer Count Register, offset: 0x8 */ 2494 union { /* offset: 0xC */ 2495 __IO uint32_t CTAR[6]; /**< Clock and Transfer Attributes Register (In Master Mode), array offset: 0xC, array step: 0x4 */ 2496 }; 2497 uint8_t RESERVED_1[8]; 2498 __IO uint32_t SR; /**< Status Register, offset: 0x2C */ 2499 __IO uint32_t RSER; /**< DMA/Interrupt Request Select and Enable Register, offset: 0x30 */ 2500 union { /* offset: 0x34 */ 2501 __IO uint32_t PUSHR; /**< PUSH TX FIFO Register In Master Mode, offset: 0x34 */ 2502 }; 2503 __I uint32_t POPR; /**< POP RX FIFO Register, offset: 0x38 */ 2504 __I uint32_t TXFR[16]; /**< Transmit FIFO Registers, array offset: 0x3C, array step: 0x4 */ 2505 __I uint32_t RXFR[16]; /**< Receive FIFO Registers, array offset: 0x7C, array step: 0x4 */ 2506 __IO uint32_t DSICR0; /**< DSI Configuration Register 0, offset: 0xBC */ 2507 __I uint32_t SDR0; /**< DSI Serialization Data Register 0, offset: 0xC0 */ 2508 __IO uint32_t ASDR0; /**< DSI Alternate Serialization Data Register 0, offset: 0xC4 */ 2509 __I uint32_t COMPR0; /**< DSI Transmit Comparison Register 0, offset: 0xC8 */ 2510 __I uint32_t DDR0; /**< DSI Deserialization Data Register 0, offset: 0xCC */ 2511 __IO uint32_t DSICR1; /**< DSI Configuration Register 1, offset: 0xD0 */ 2512 __IO uint32_t SSR0; /**< DSI Serialization Source Select Register 0, offset: 0xD4 */ 2513 uint8_t RESERVED_2[16]; 2514 __IO uint32_t DIMR0; /**< DSI Deserialized Data Interrupt Mask Register 0, offset: 0xE8 */ 2515 __IO uint32_t DPIR0; /**< DSI Deserialized Data Polarity Interrupt Register 0, offset: 0xEC */ 2516 __I uint32_t SDR1; /**< DSI Serialization Data Register 1, offset: 0xF0 */ 2517 __IO uint32_t ASDR1; /**< DSI Alternate Serialization Data Register 1, offset: 0xF4 */ 2518 __I uint32_t COMPR1; /**< DSI Transmit Comparison Register 1, offset: 0xF8 */ 2519 __I uint32_t DDR1; /**< DSI Deserialization Data Register 1, offset: 0xFC */ 2520 __IO uint32_t SSR1; /**< DSI Serialization Source Select Register 1, offset: 0x100 */ 2521 uint8_t RESERVED_3[16]; 2522 __IO uint32_t DIMR1; /**< DSI Deserialized Data Interrupt Mask Register 1, offset: 0x114 */ 2523 __IO uint32_t DPIR1; /**< DSI Deserialized Data Polarity Interrupt Register 1, offset: 0x118 */ 2524 __IO uint32_t CTARE[6]; /**< Clock and Transfer Attributes Register Extended, array offset: 0x11C, array step: 0x4 */ 2525 uint8_t RESERVED_4[8]; 2526 __I uint32_t SREX; /**< Status Register Extended, offset: 0x13C */ 2527 uint8_t RESERVED_5[16]; 2528 __IO uint32_t TSL; /**< Time Slot Length Register, offset: 0x150 */ 2529 __IO uint32_t TS_CONF; /**< Time Slot Configuration Register, offset: 0x154 */ 2530 } SPI_Type; 2531 2532 2533 /* ---------------------------------------------------------------------------- 2534 -- DSPI Register Masks 2535 ---------------------------------------------------------------------------- */ 2536 2537 /*! 2538 * @addtogroup DSPI_Register_Masks DSPI Register Masks 2539 * @{ 2540 */ 2541 2542 /*! @name MCR - Module Configuration Register */ 2543 /*! @{ */ 2544 2545 #define SPI_MCR_HALT_MASK DSPI_MCR_HALT_MASK 2546 #define SPI_MCR_HALT_SHIFT DSPI_MCR_HALT_SHIFT 2547 #define SPI_MCR_HALT_WIDTH DSPI_MCR_HALT_WIDTH 2548 #define SPI_MCR_HALT(x) DSPI_MCR_HALT(x) 2549 2550 #define SPI_MCR_PES_MASK DSPI_MCR_PES_MASK 2551 #define SPI_MCR_PES_SHIFT DSPI_MCR_PES_SHIFT 2552 #define SPI_MCR_PES_WIDTH DSPI_MCR_PES_WIDTH 2553 #define SPI_MCR_PES(x) DSPI_MCR_PES(x) 2554 2555 #define SPI_MCR_FCPCS_MASK DSPI_MCR_FCPCS_MASK 2556 #define SPI_MCR_FCPCS_SHIFT DSPI_MCR_FCPCS_SHIFT 2557 #define SPI_MCR_FCPCS_WIDTH DSPI_MCR_FCPCS_WIDTH 2558 #define SPI_MCR_FCPCS(x) DSPI_MCR_FCPCS(x) 2559 2560 #define SPI_MCR_XSPI_MASK DSPI_MCR_XSPI_MASK 2561 #define SPI_MCR_XSPI_SHIFT DSPI_MCR_XSPI_SHIFT 2562 #define SPI_MCR_XSPI_WIDTH DSPI_MCR_XSPI_WIDTH 2563 #define SPI_MCR_XSPI(x) DSPI_MCR_XSPI(x) 2564 2565 #define SPI_MCR_SMPL_PT_MASK DSPI_MCR_SMPL_PT_MASK 2566 #define SPI_MCR_SMPL_PT_SHIFT DSPI_MCR_SMPL_PT_SHIFT 2567 #define SPI_MCR_SMPL_PT_WIDTH DSPI_MCR_SMPL_PT_WIDTH 2568 #define SPI_MCR_SMPL_PT(x) DSPI_MCR_SMPL_PT(x) 2569 2570 #define SPI_MCR_CLR_RXF_MASK DSPI_MCR_CLR_RXF_MASK 2571 #define SPI_MCR_CLR_RXF_SHIFT DSPI_MCR_CLR_RXF_SHIFT 2572 #define SPI_MCR_CLR_RXF_WIDTH DSPI_MCR_CLR_RXF_WIDTH 2573 #define SPI_MCR_CLR_RXF(x) DSPI_MCR_CLR_RXF(x) 2574 2575 #define SPI_MCR_CLR_TXF_MASK DSPI_MCR_CLR_TXF_MASK 2576 #define SPI_MCR_CLR_TXF_SHIFT DSPI_MCR_CLR_TXF_SHIFT 2577 #define SPI_MCR_CLR_TXF_WIDTH DSPI_MCR_CLR_TXF_WIDTH 2578 #define SPI_MCR_CLR_TXF(x) DSPI_MCR_CLR_TXF(x) 2579 2580 #define SPI_MCR_DIS_RXF_MASK DSPI_MCR_DIS_RXF_MASK 2581 #define SPI_MCR_DIS_RXF_SHIFT DSPI_MCR_DIS_RXF_SHIFT 2582 #define SPI_MCR_DIS_RXF_WIDTH DSPI_MCR_DIS_RXF_WIDTH 2583 #define SPI_MCR_DIS_RXF(x) DSPI_MCR_DIS_RXF(x) 2584 2585 #define SPI_MCR_DIS_TXF_MASK DSPI_MCR_DIS_TXF_MASK 2586 #define SPI_MCR_DIS_TXF_SHIFT DSPI_MCR_DIS_TXF_SHIFT 2587 #define SPI_MCR_DIS_TXF_WIDTH DSPI_MCR_DIS_TXF_WIDTH 2588 #define SPI_MCR_DIS_TXF(x) DSPI_MCR_DIS_TXF(x) 2589 2590 #define SPI_MCR_MDIS_MASK DSPI_MCR_MDIS_MASK 2591 #define SPI_MCR_MDIS_SHIFT DSPI_MCR_MDIS_SHIFT 2592 #define SPI_MCR_MDIS_WIDTH DSPI_MCR_MDIS_WIDTH 2593 #define SPI_MCR_MDIS(x) DSPI_MCR_MDIS(x) 2594 2595 #define SPI_MCR_PCSIS_MASK DSPI_MCR_PCSIS_MASK 2596 #define SPI_MCR_PCSIS_SHIFT DSPI_MCR_PCSIS_SHIFT 2597 #define SPI_MCR_PCSIS_WIDTH DSPI_MCR_PCSIS_WIDTH 2598 #define SPI_MCR_PCSIS(x) DSPI_MCR_PCSIS(x) 2599 2600 #define SPI_MCR_ROOE_MASK DSPI_MCR_ROOE_MASK 2601 #define SPI_MCR_ROOE_SHIFT DSPI_MCR_ROOE_SHIFT 2602 #define SPI_MCR_ROOE_WIDTH DSPI_MCR_ROOE_WIDTH 2603 #define SPI_MCR_ROOE(x) DSPI_MCR_ROOE(x) 2604 2605 #define SPI_MCR_MTFE_MASK DSPI_MCR_MTFE_MASK 2606 #define SPI_MCR_MTFE_SHIFT DSPI_MCR_MTFE_SHIFT 2607 #define SPI_MCR_MTFE_WIDTH DSPI_MCR_MTFE_WIDTH 2608 #define SPI_MCR_MTFE(x) DSPI_MCR_MTFE(x) 2609 2610 #define SPI_MCR_FRZ_MASK DSPI_MCR_FRZ_MASK 2611 #define SPI_MCR_FRZ_SHIFT DSPI_MCR_FRZ_SHIFT 2612 #define SPI_MCR_FRZ_WIDTH DSPI_MCR_FRZ_WIDTH 2613 #define SPI_MCR_FRZ(x) DSPI_MCR_FRZ(x) 2614 2615 #define SPI_MCR_DCONF_MASK DSPI_MCR_DCONF_MASK 2616 #define SPI_MCR_DCONF_SHIFT DSPI_MCR_DCONF_SHIFT 2617 #define SPI_MCR_DCONF_WIDTH DSPI_MCR_DCONF_WIDTH 2618 #define SPI_MCR_DCONF(x) DSPI_MCR_DCONF(x) 2619 2620 #define SPI_MCR_CONT_SCKE_MASK DSPI_MCR_CONT_SCKE_MASK 2621 #define SPI_MCR_CONT_SCKE_SHIFT DSPI_MCR_CONT_SCKE_SHIFT 2622 #define SPI_MCR_CONT_SCKE_WIDTH DSPI_MCR_CONT_SCKE_WIDTH 2623 #define SPI_MCR_CONT_SCKE(x) DSPI_MCR_CONT_SCKE(x) 2624 2625 #define SPI_MCR_MSTR_MASK DSPI_MCR_MSTR_MASK 2626 #define SPI_MCR_MSTR_SHIFT DSPI_MCR_MSTR_SHIFT 2627 #define SPI_MCR_MSTR_WIDTH DSPI_MCR_MSTR_WIDTH 2628 #define SPI_MCR_MSTR(x) DSPI_MCR_MSTR(x) 2629 /*! @} */ 2630 2631 /*! @name TCR - Transfer Count Register */ 2632 /*! @{ */ 2633 2634 #define SPI_TCR_SPI_TCNT_MASK DSPI_TCR_SPI_TCNT_MASK 2635 #define SPI_TCR_SPI_TCNT_SHIFT DSPI_TCR_SPI_TCNT_SHIFT 2636 #define SPI_TCR_SPI_TCNT_WIDTH DSPI_TCR_SPI_TCNT_WIDTH 2637 #define SPI_TCR_SPI_TCNT(x) DSPI_TCR_SPI_TCNT(x) 2638 /*! @} */ 2639 2640 /*! @name CTAR - Clock and Transfer Attributes Register (In Master Mode) */ 2641 /*! @{ */ 2642 2643 #define SPI_CTAR_BR_MASK DSPI_CTAR_BR_MASK 2644 #define SPI_CTAR_BR_SHIFT DSPI_CTAR_BR_SHIFT 2645 #define SPI_CTAR_BR_WIDTH DSPI_CTAR_BR_WIDTH 2646 #define SPI_CTAR_BR(x) DSPI_CTAR_BR(x) 2647 2648 #define SPI_CTAR_DT_MASK DSPI_CTAR_DT_MASK 2649 #define SPI_CTAR_DT_SHIFT DSPI_CTAR_DT_SHIFT 2650 #define SPI_CTAR_DT_WIDTH DSPI_CTAR_DT_WIDTH 2651 #define SPI_CTAR_DT(x) DSPI_CTAR_DT(x) 2652 2653 #define SPI_CTAR_ASC_MASK DSPI_CTAR_ASC_MASK 2654 #define SPI_CTAR_ASC_SHIFT DSPI_CTAR_ASC_SHIFT 2655 #define SPI_CTAR_ASC_WIDTH DSPI_CTAR_ASC_WIDTH 2656 #define SPI_CTAR_ASC(x) DSPI_CTAR_ASC(x) 2657 2658 #define SPI_CTAR_CSSCK_MASK DSPI_CTAR_CSSCK_MASK 2659 #define SPI_CTAR_CSSCK_SHIFT DSPI_CTAR_CSSCK_SHIFT 2660 #define SPI_CTAR_CSSCK_WIDTH DSPI_CTAR_CSSCK_WIDTH 2661 #define SPI_CTAR_CSSCK(x) DSPI_CTAR_CSSCK(x) 2662 2663 #define SPI_CTAR_PBR_MASK DSPI_CTAR_PBR_MASK 2664 #define SPI_CTAR_PBR_SHIFT DSPI_CTAR_PBR_SHIFT 2665 #define SPI_CTAR_PBR_WIDTH DSPI_CTAR_PBR_WIDTH 2666 #define SPI_CTAR_PBR(x) DSPI_CTAR_PBR(x) 2667 2668 #define SPI_CTAR_PDT_MASK DSPI_CTAR_PDT_MASK 2669 #define SPI_CTAR_PDT_SHIFT DSPI_CTAR_PDT_SHIFT 2670 #define SPI_CTAR_PDT_WIDTH DSPI_CTAR_PDT_WIDTH 2671 #define SPI_CTAR_PDT(x) DSPI_CTAR_PDT(x) 2672 2673 #define SPI_CTAR_PASC_MASK DSPI_CTAR_PASC_MASK 2674 #define SPI_CTAR_PASC_SHIFT DSPI_CTAR_PASC_SHIFT 2675 #define SPI_CTAR_PASC_WIDTH DSPI_CTAR_PASC_WIDTH 2676 #define SPI_CTAR_PASC(x) DSPI_CTAR_PASC(x) 2677 2678 #define SPI_CTAR_PCSSCK_MASK DSPI_CTAR_PCSSCK_MASK 2679 #define SPI_CTAR_PCSSCK_SHIFT DSPI_CTAR_PCSSCK_SHIFT 2680 #define SPI_CTAR_PCSSCK_WIDTH DSPI_CTAR_PCSSCK_WIDTH 2681 #define SPI_CTAR_PCSSCK(x) DSPI_CTAR_PCSSCK(x) 2682 2683 #define SPI_CTAR_LSBFE_MASK DSPI_CTAR_LSBFE_MASK 2684 #define SPI_CTAR_LSBFE_SHIFT DSPI_CTAR_LSBFE_SHIFT 2685 #define SPI_CTAR_LSBFE_WIDTH DSPI_CTAR_LSBFE_WIDTH 2686 #define SPI_CTAR_LSBFE(x) DSPI_CTAR_LSBFE(x) 2687 2688 #define SPI_CTAR_CPHA_MASK DSPI_CTAR_CPHA_MASK 2689 #define SPI_CTAR_CPHA_SHIFT DSPI_CTAR_CPHA_SHIFT 2690 #define SPI_CTAR_CPHA_WIDTH DSPI_CTAR_CPHA_WIDTH 2691 #define SPI_CTAR_CPHA(x) DSPI_CTAR_CPHA(x) 2692 2693 #define SPI_CTAR_CPOL_MASK DSPI_CTAR_CPOL_MASK 2694 #define SPI_CTAR_CPOL_SHIFT DSPI_CTAR_CPOL_SHIFT 2695 #define SPI_CTAR_CPOL_WIDTH DSPI_CTAR_CPOL_WIDTH 2696 #define SPI_CTAR_CPOL(x) DSPI_CTAR_CPOL(x) 2697 2698 #define SPI_CTAR_FMSZ_MASK DSPI_CTAR_FMSZ_MASK 2699 #define SPI_CTAR_FMSZ_SHIFT DSPI_CTAR_FMSZ_SHIFT 2700 #define SPI_CTAR_FMSZ_WIDTH DSPI_CTAR_FMSZ_WIDTH 2701 #define SPI_CTAR_FMSZ(x) DSPI_CTAR_FMSZ(x) 2702 2703 #define SPI_CTAR_DBR_MASK DSPI_CTAR_DBR_MASK 2704 #define SPI_CTAR_DBR_SHIFT DSPI_CTAR_DBR_SHIFT 2705 #define SPI_CTAR_DBR_WIDTH DSPI_CTAR_DBR_WIDTH 2706 #define SPI_CTAR_DBR(x) DSPI_CTAR_DBR(x) 2707 /*! @} */ 2708 2709 /*! @name SR - Status Register */ 2710 /*! @{ */ 2711 2712 #define SPI_SR_POPNXTPTR_MASK DSPI_SR_POPNXTPTR_MASK 2713 #define SPI_SR_POPNXTPTR_SHIFT DSPI_SR_POPNXTPTR_SHIFT 2714 #define SPI_SR_POPNXTPTR_WIDTH DSPI_SR_POPNXTPTR_WIDTH 2715 #define SPI_SR_POPNXTPTR(x) DSPI_SR_POPNXTPTR(x) 2716 2717 #define SPI_SR_RXCTR_MASK DSPI_SR_RXCTR_MASK 2718 #define SPI_SR_RXCTR_SHIFT DSPI_SR_RXCTR_SHIFT 2719 #define SPI_SR_RXCTR_WIDTH DSPI_SR_RXCTR_WIDTH 2720 #define SPI_SR_RXCTR(x) DSPI_SR_RXCTR(x) 2721 2722 #define SPI_SR_TXNXTPTR_MASK DSPI_SR_TXNXTPTR_MASK 2723 #define SPI_SR_TXNXTPTR_SHIFT DSPI_SR_TXNXTPTR_SHIFT 2724 #define SPI_SR_TXNXTPTR_WIDTH DSPI_SR_TXNXTPTR_WIDTH 2725 #define SPI_SR_TXNXTPTR(x) DSPI_SR_TXNXTPTR(x) 2726 2727 #define SPI_SR_TXCTR_MASK DSPI_SR_TXCTR_MASK 2728 #define SPI_SR_TXCTR_SHIFT DSPI_SR_TXCTR_SHIFT 2729 #define SPI_SR_TXCTR_WIDTH DSPI_SR_TXCTR_WIDTH 2730 #define SPI_SR_TXCTR(x) DSPI_SR_TXCTR(x) 2731 2732 #define SPI_SR_CMDFFF_MASK DSPI_SR_CMDFFF_MASK 2733 #define SPI_SR_CMDFFF_SHIFT DSPI_SR_CMDFFF_SHIFT 2734 #define SPI_SR_CMDFFF_WIDTH DSPI_SR_CMDFFF_WIDTH 2735 #define SPI_SR_CMDFFF(x) DSPI_SR_CMDFFF(x) 2736 2737 #define SPI_SR_RFDF_MASK DSPI_SR_RFDF_MASK 2738 #define SPI_SR_RFDF_SHIFT DSPI_SR_RFDF_SHIFT 2739 #define SPI_SR_RFDF_WIDTH DSPI_SR_RFDF_WIDTH 2740 #define SPI_SR_RFDF(x) DSPI_SR_RFDF(x) 2741 2742 #define SPI_SR_TFIWF_MASK DSPI_SR_TFIWF_MASK 2743 #define SPI_SR_TFIWF_SHIFT DSPI_SR_TFIWF_SHIFT 2744 #define SPI_SR_TFIWF_WIDTH DSPI_SR_TFIWF_WIDTH 2745 #define SPI_SR_TFIWF(x) DSPI_SR_TFIWF(x) 2746 2747 #define SPI_SR_RFOF_MASK DSPI_SR_RFOF_MASK 2748 #define SPI_SR_RFOF_SHIFT DSPI_SR_RFOF_SHIFT 2749 #define SPI_SR_RFOF_WIDTH DSPI_SR_RFOF_WIDTH 2750 #define SPI_SR_RFOF(x) DSPI_SR_RFOF(x) 2751 2752 #define SPI_SR_DDIF_MASK DSPI_SR_DDIF_MASK 2753 #define SPI_SR_DDIF_SHIFT DSPI_SR_DDIF_SHIFT 2754 #define SPI_SR_DDIF_WIDTH DSPI_SR_DDIF_WIDTH 2755 #define SPI_SR_DDIF(x) DSPI_SR_DDIF(x) 2756 2757 #define SPI_SR_SPEF_MASK DSPI_SR_SPEF_MASK 2758 #define SPI_SR_SPEF_SHIFT DSPI_SR_SPEF_SHIFT 2759 #define SPI_SR_SPEF_WIDTH DSPI_SR_SPEF_WIDTH 2760 #define SPI_SR_SPEF(x) DSPI_SR_SPEF(x) 2761 2762 #define SPI_SR_DPEF_MASK DSPI_SR_DPEF_MASK 2763 #define SPI_SR_DPEF_SHIFT DSPI_SR_DPEF_SHIFT 2764 #define SPI_SR_DPEF_WIDTH DSPI_SR_DPEF_WIDTH 2765 #define SPI_SR_DPEF(x) DSPI_SR_DPEF(x) 2766 2767 #define SPI_SR_CMDTCF_MASK DSPI_SR_CMDTCF_MASK 2768 #define SPI_SR_CMDTCF_SHIFT DSPI_SR_CMDTCF_SHIFT 2769 #define SPI_SR_CMDTCF_WIDTH DSPI_SR_CMDTCF_WIDTH 2770 #define SPI_SR_CMDTCF(x) DSPI_SR_CMDTCF(x) 2771 2772 #define SPI_SR_BSYF_MASK DSPI_SR_BSYF_MASK 2773 #define SPI_SR_BSYF_SHIFT DSPI_SR_BSYF_SHIFT 2774 #define SPI_SR_BSYF_WIDTH DSPI_SR_BSYF_WIDTH 2775 #define SPI_SR_BSYF(x) DSPI_SR_BSYF(x) 2776 2777 #define SPI_SR_TFFF_MASK DSPI_SR_TFFF_MASK 2778 #define SPI_SR_TFFF_SHIFT DSPI_SR_TFFF_SHIFT 2779 #define SPI_SR_TFFF_WIDTH DSPI_SR_TFFF_WIDTH 2780 #define SPI_SR_TFFF(x) DSPI_SR_TFFF(x) 2781 2782 #define SPI_SR_EOQF_MASK DSPI_SR_EOQF_MASK 2783 #define SPI_SR_EOQF_SHIFT DSPI_SR_EOQF_SHIFT 2784 #define SPI_SR_EOQF_WIDTH DSPI_SR_EOQF_WIDTH 2785 #define SPI_SR_EOQF(x) DSPI_SR_EOQF(x) 2786 2787 #define SPI_SR_SPITCF_MASK DSPI_SR_SPITCF_MASK 2788 #define SPI_SR_SPITCF_SHIFT DSPI_SR_SPITCF_SHIFT 2789 #define SPI_SR_SPITCF_WIDTH DSPI_SR_SPITCF_WIDTH 2790 #define SPI_SR_SPITCF(x) DSPI_SR_SPITCF(x) 2791 2792 #define SPI_SR_TXRXS_MASK DSPI_SR_TXRXS_MASK 2793 #define SPI_SR_TXRXS_SHIFT DSPI_SR_TXRXS_SHIFT 2794 #define SPI_SR_TXRXS_WIDTH DSPI_SR_TXRXS_WIDTH 2795 #define SPI_SR_TXRXS(x) DSPI_SR_TXRXS(x) 2796 2797 #define SPI_SR_TCF_MASK DSPI_SR_TCF_MASK 2798 #define SPI_SR_TCF_SHIFT DSPI_SR_TCF_SHIFT 2799 #define SPI_SR_TCF_WIDTH DSPI_SR_TCF_WIDTH 2800 #define SPI_SR_TCF(x) DSPI_SR_TCF(x) 2801 /*! @} */ 2802 2803 /*! @name RSER - DMA/Interrupt Request Select and Enable Register */ 2804 /*! @{ */ 2805 2806 #define SPI_RSER_DDIF_DIRS_MASK DSPI_RSER_DDIF_DIRS_MASK 2807 #define SPI_RSER_DDIF_DIRS_SHIFT DSPI_RSER_DDIF_DIRS_SHIFT 2808 #define SPI_RSER_DDIF_DIRS_WIDTH DSPI_RSER_DDIF_DIRS_WIDTH 2809 #define SPI_RSER_DDIF_DIRS(x) DSPI_RSER_DDIF_DIRS(x) 2810 2811 #define SPI_RSER_CMDFFF_DIRS_MASK DSPI_RSER_CMDFFF_DIRS_MASK 2812 #define SPI_RSER_CMDFFF_DIRS_SHIFT DSPI_RSER_CMDFFF_DIRS_SHIFT 2813 #define SPI_RSER_CMDFFF_DIRS_WIDTH DSPI_RSER_CMDFFF_DIRS_WIDTH 2814 #define SPI_RSER_CMDFFF_DIRS(x) DSPI_RSER_CMDFFF_DIRS(x) 2815 2816 #define SPI_RSER_RFDF_DIRS_MASK DSPI_RSER_RFDF_DIRS_MASK 2817 #define SPI_RSER_RFDF_DIRS_SHIFT DSPI_RSER_RFDF_DIRS_SHIFT 2818 #define SPI_RSER_RFDF_DIRS_WIDTH DSPI_RSER_RFDF_DIRS_WIDTH 2819 #define SPI_RSER_RFDF_DIRS(x) DSPI_RSER_RFDF_DIRS(x) 2820 2821 #define SPI_RSER_RFDF_RE_MASK DSPI_RSER_RFDF_RE_MASK 2822 #define SPI_RSER_RFDF_RE_SHIFT DSPI_RSER_RFDF_RE_SHIFT 2823 #define SPI_RSER_RFDF_RE_WIDTH DSPI_RSER_RFDF_RE_WIDTH 2824 #define SPI_RSER_RFDF_RE(x) DSPI_RSER_RFDF_RE(x) 2825 2826 #define SPI_RSER_TFIWF_RE_MASK DSPI_RSER_TFIWF_RE_MASK 2827 #define SPI_RSER_TFIWF_RE_SHIFT DSPI_RSER_TFIWF_RE_SHIFT 2828 #define SPI_RSER_TFIWF_RE_WIDTH DSPI_RSER_TFIWF_RE_WIDTH 2829 #define SPI_RSER_TFIWF_RE(x) DSPI_RSER_TFIWF_RE(x) 2830 2831 #define SPI_RSER_RFOF_RE_MASK DSPI_RSER_RFOF_RE_MASK 2832 #define SPI_RSER_RFOF_RE_SHIFT DSPI_RSER_RFOF_RE_SHIFT 2833 #define SPI_RSER_RFOF_RE_WIDTH DSPI_RSER_RFOF_RE_WIDTH 2834 #define SPI_RSER_RFOF_RE(x) DSPI_RSER_RFOF_RE(x) 2835 2836 #define SPI_RSER_DDIF_RE_MASK DSPI_RSER_DDIF_RE_MASK 2837 #define SPI_RSER_DDIF_RE_SHIFT DSPI_RSER_DDIF_RE_SHIFT 2838 #define SPI_RSER_DDIF_RE_WIDTH DSPI_RSER_DDIF_RE_WIDTH 2839 #define SPI_RSER_DDIF_RE(x) DSPI_RSER_DDIF_RE(x) 2840 2841 #define SPI_RSER_SPEF_RE_MASK DSPI_RSER_SPEF_RE_MASK 2842 #define SPI_RSER_SPEF_RE_SHIFT DSPI_RSER_SPEF_RE_SHIFT 2843 #define SPI_RSER_SPEF_RE_WIDTH DSPI_RSER_SPEF_RE_WIDTH 2844 #define SPI_RSER_SPEF_RE(x) DSPI_RSER_SPEF_RE(x) 2845 2846 #define SPI_RSER_DPEF_RE_MASK DSPI_RSER_DPEF_RE_MASK 2847 #define SPI_RSER_DPEF_RE_SHIFT DSPI_RSER_DPEF_RE_SHIFT 2848 #define SPI_RSER_DPEF_RE_WIDTH DSPI_RSER_DPEF_RE_WIDTH 2849 #define SPI_RSER_DPEF_RE(x) DSPI_RSER_DPEF_RE(x) 2850 2851 #define SPI_RSER_CMDTCF_RE_MASK DSPI_RSER_CMDTCF_RE_MASK 2852 #define SPI_RSER_CMDTCF_RE_SHIFT DSPI_RSER_CMDTCF_RE_SHIFT 2853 #define SPI_RSER_CMDTCF_RE_WIDTH DSPI_RSER_CMDTCF_RE_WIDTH 2854 #define SPI_RSER_CMDTCF_RE(x) DSPI_RSER_CMDTCF_RE(x) 2855 2856 #define SPI_RSER_TFFF_DIRS_MASK DSPI_RSER_TFFF_DIRS_MASK 2857 #define SPI_RSER_TFFF_DIRS_SHIFT DSPI_RSER_TFFF_DIRS_SHIFT 2858 #define SPI_RSER_TFFF_DIRS_WIDTH DSPI_RSER_TFFF_DIRS_WIDTH 2859 #define SPI_RSER_TFFF_DIRS(x) DSPI_RSER_TFFF_DIRS(x) 2860 2861 #define SPI_RSER_TFFF_RE_MASK DSPI_RSER_TFFF_RE_MASK 2862 #define SPI_RSER_TFFF_RE_SHIFT DSPI_RSER_TFFF_RE_SHIFT 2863 #define SPI_RSER_TFFF_RE_WIDTH DSPI_RSER_TFFF_RE_WIDTH 2864 #define SPI_RSER_TFFF_RE(x) DSPI_RSER_TFFF_RE(x) 2865 2866 #define SPI_RSER_EOQF_RE_MASK DSPI_RSER_EOQF_RE_MASK 2867 #define SPI_RSER_EOQF_RE_SHIFT DSPI_RSER_EOQF_RE_SHIFT 2868 #define SPI_RSER_EOQF_RE_WIDTH DSPI_RSER_EOQF_RE_WIDTH 2869 #define SPI_RSER_EOQF_RE(x) DSPI_RSER_EOQF_RE(x) 2870 2871 #define SPI_RSER_CMDFFF_RE_MASK DSPI_RSER_CMDFFF_RE_MASK 2872 #define SPI_RSER_CMDFFF_RE_SHIFT DSPI_RSER_CMDFFF_RE_SHIFT 2873 #define SPI_RSER_CMDFFF_RE_WIDTH DSPI_RSER_CMDFFF_RE_WIDTH 2874 #define SPI_RSER_CMDFFF_RE(x) DSPI_RSER_CMDFFF_RE(x) 2875 2876 #define SPI_RSER_TCF_RE_MASK DSPI_RSER_TCF_RE_MASK 2877 #define SPI_RSER_TCF_RE_SHIFT DSPI_RSER_TCF_RE_SHIFT 2878 #define SPI_RSER_TCF_RE_WIDTH DSPI_RSER_TCF_RE_WIDTH 2879 #define SPI_RSER_TCF_RE(x) DSPI_RSER_TCF_RE(x) 2880 /*! @} */ 2881 2882 /*! @name TX - DSPI_TX register */ 2883 /*! @{ */ 2884 2885 #define SPI_TX_TX_MASK DSPI_TX_TX_MASK 2886 #define SPI_TX_TX_SHIFT DSPI_TX_TX_SHIFT 2887 #define SPI_TX_TX_WIDTH DSPI_TX_TX_WIDTH 2888 #define SPI_TX_TX(x) DSPI_TX_TX(x) 2889 /*! @} */ 2890 2891 /*! @name CMD - DSPI_CMD register */ 2892 /*! @{ */ 2893 2894 #define SPI_CMD_CMD_MASK DSPI_CMD_CMD_MASK 2895 #define SPI_CMD_CMD_SHIFT DSPI_CMD_CMD_SHIFT 2896 #define SPI_CMD_CMD_WIDTH DSPI_CMD_CMD_WIDTH 2897 #define SPI_CMD_CMD(x) DSPI_CMD_CMD(x) 2898 /*! @} */ 2899 2900 /*! @name PUSHR - PUSH TX FIFO Register In Master Mode */ 2901 /*! @{ */ 2902 2903 #define SPI_PUSHR_TXDATA_MASK DSPI_PUSHR_TXDATA_MASK 2904 #define SPI_PUSHR_TXDATA_SHIFT DSPI_PUSHR_TXDATA_SHIFT 2905 #define SPI_PUSHR_TXDATA_WIDTH DSPI_PUSHR_TXDATA_WIDTH 2906 #define SPI_PUSHR_TXDATA(x) DSPI_PUSHR_TXDATA(x) 2907 2908 #define SPI_PUSHR_PCS_MASK DSPI_PUSHR_PCS_MASK 2909 #define SPI_PUSHR_PCS_SHIFT DSPI_PUSHR_PCS_SHIFT 2910 #define SPI_PUSHR_PCS_WIDTH DSPI_PUSHR_PCS_WIDTH 2911 #define SPI_PUSHR_PCS(x) DSPI_PUSHR_PCS(x) 2912 2913 #define SPI_PUSHR_PP_MCSC_MASK DSPI_PUSHR_PP_MCSC_MASK 2914 #define SPI_PUSHR_PP_MCSC_SHIFT DSPI_PUSHR_PP_MCSC_SHIFT 2915 #define SPI_PUSHR_PP_MCSC_WIDTH DSPI_PUSHR_PP_MCSC_WIDTH 2916 #define SPI_PUSHR_PP_MCSC(x) DSPI_PUSHR_PP_MCSC(x) 2917 2918 #define SPI_PUSHR_PE_MASC_MASK DSPI_PUSHR_PE_MASC_MASK 2919 #define SPI_PUSHR_PE_MASC_SHIFT DSPI_PUSHR_PE_MASC_SHIFT 2920 #define SPI_PUSHR_PE_MASC_WIDTH DSPI_PUSHR_PE_MASC_WIDTH 2921 #define SPI_PUSHR_PE_MASC(x) DSPI_PUSHR_PE_MASC(x) 2922 2923 #define SPI_PUSHR_CTCNT_MASK DSPI_PUSHR_CTCNT_MASK 2924 #define SPI_PUSHR_CTCNT_SHIFT DSPI_PUSHR_CTCNT_SHIFT 2925 #define SPI_PUSHR_CTCNT_WIDTH DSPI_PUSHR_CTCNT_WIDTH 2926 #define SPI_PUSHR_CTCNT(x) DSPI_PUSHR_CTCNT(x) 2927 2928 #define SPI_PUSHR_EOQ_MASK DSPI_PUSHR_EOQ_MASK 2929 #define SPI_PUSHR_EOQ_SHIFT DSPI_PUSHR_EOQ_SHIFT 2930 #define SPI_PUSHR_EOQ_WIDTH DSPI_PUSHR_EOQ_WIDTH 2931 #define SPI_PUSHR_EOQ(x) DSPI_PUSHR_EOQ(x) 2932 2933 #define SPI_PUSHR_CTAS_MASK DSPI_PUSHR_CTAS_MASK 2934 #define SPI_PUSHR_CTAS_SHIFT DSPI_PUSHR_CTAS_SHIFT 2935 #define SPI_PUSHR_CTAS_WIDTH DSPI_PUSHR_CTAS_WIDTH 2936 #define SPI_PUSHR_CTAS(x) DSPI_PUSHR_CTAS(x) 2937 2938 #define SPI_PUSHR_CONT_MASK DSPI_PUSHR_CONT_MASK 2939 #define SPI_PUSHR_CONT_SHIFT DSPI_PUSHR_CONT_SHIFT 2940 #define SPI_PUSHR_CONT_WIDTH DSPI_PUSHR_CONT_WIDTH 2941 #define SPI_PUSHR_CONT(x) DSPI_PUSHR_CONT(x) 2942 /*! @} */ 2943 2944 /*! @name POPR - POP RX FIFO Register */ 2945 /*! @{ */ 2946 2947 #define SPI_POPR_RXDATA_MASK DSPI_POPR_RXDATA_MASK 2948 #define SPI_POPR_RXDATA_SHIFT DSPI_POPR_RXDATA_SHIFT 2949 #define SPI_POPR_RXDATA_WIDTH DSPI_POPR_RXDATA_WIDTH 2950 #define SPI_POPR_RXDATA(x) DSPI_POPR_RXDATA(x) 2951 /*! @} */ 2952 2953 /*! @name TXFR - Transmit FIFO Registers */ 2954 /*! @{ */ 2955 2956 #define SPI_TXFR_TXDATA_MASK DSPI_TXFR_TXDATA_MASK 2957 #define SPI_TXFR_TXDATA_SHIFT DSPI_TXFR_TXDATA_SHIFT 2958 #define SPI_TXFR_TXDATA_WIDTH DSPI_TXFR_TXDATA_WIDTH 2959 #define SPI_TXFR_TXDATA(x) DSPI_TXFR_TXDATA(x) 2960 2961 #define SPI_TXFR_TXCMD_TXDATA_MASK DSPI_TXFR_TXCMD_TXDATA_MASK 2962 #define SPI_TXFR_TXCMD_TXDATA_SHIFT DSPI_TXFR_TXCMD_TXDATA_SHIFT 2963 #define SPI_TXFR_TXCMD_TXDATA_WIDTH DSPI_TXFR_TXCMD_TXDATA_WIDTH 2964 #define SPI_TXFR_TXCMD_TXDATA(x) DSPI_TXFR_TXCMD_TXDATA(x) 2965 /*! @} */ 2966 2967 /*! @name RXFR - Receive FIFO Registers */ 2968 /*! @{ */ 2969 2970 #define SPI_RXFR_RXDATA_MASK DSPI_RXFR_RXDATA_MASK 2971 #define SPI_RXFR_RXDATA_SHIFT DSPI_RXFR_RXDATA_SHIFT 2972 #define SPI_RXFR_RXDATA_WIDTH DSPI_RXFR_RXDATA_WIDTH 2973 #define SPI_RXFR_RXDATA(x) DSPI_RXFR_RXDATA(x) 2974 /*! @} */ 2975 2976 /*! @name DSICR0 - DSI Configuration Register 0 */ 2977 /*! @{ */ 2978 2979 #define SPI_DSICR0_DPCSx_MASK DSPI_DSICR0_DPCSx_MASK 2980 #define SPI_DSICR0_DPCSx_SHIFT DSPI_DSICR0_DPCSx_SHIFT 2981 #define SPI_DSICR0_DPCSx_WIDTH DSPI_DSICR0_DPCSx_WIDTH 2982 #define SPI_DSICR0_DPCSx(x) DSPI_DSICR0_DPCSx(x) 2983 2984 #define SPI_DSICR0_PP_MASK DSPI_DSICR0_PP_MASK 2985 #define SPI_DSICR0_PP_SHIFT DSPI_DSICR0_PP_SHIFT 2986 #define SPI_DSICR0_PP_WIDTH DSPI_DSICR0_PP_WIDTH 2987 #define SPI_DSICR0_PP(x) DSPI_DSICR0_PP(x) 2988 2989 #define SPI_DSICR0_PE_MASK DSPI_DSICR0_PE_MASK 2990 #define SPI_DSICR0_PE_SHIFT DSPI_DSICR0_PE_SHIFT 2991 #define SPI_DSICR0_PE_WIDTH DSPI_DSICR0_PE_WIDTH 2992 #define SPI_DSICR0_PE(x) DSPI_DSICR0_PE(x) 2993 2994 #define SPI_DSICR0_PES_MASK DSPI_DSICR0_PES_MASK 2995 #define SPI_DSICR0_PES_SHIFT DSPI_DSICR0_PES_SHIFT 2996 #define SPI_DSICR0_PES_WIDTH DSPI_DSICR0_PES_WIDTH 2997 #define SPI_DSICR0_PES(x) DSPI_DSICR0_PES(x) 2998 2999 #define SPI_DSICR0_DMS_MASK DSPI_DSICR0_DMS_MASK 3000 #define SPI_DSICR0_DMS_SHIFT DSPI_DSICR0_DMS_SHIFT 3001 #define SPI_DSICR0_DMS_WIDTH DSPI_DSICR0_DMS_WIDTH 3002 #define SPI_DSICR0_DMS(x) DSPI_DSICR0_DMS(x) 3003 3004 #define SPI_DSICR0_DSICTAS_MASK DSPI_DSICR0_DSICTAS_MASK 3005 #define SPI_DSICR0_DSICTAS_SHIFT DSPI_DSICR0_DSICTAS_SHIFT 3006 #define SPI_DSICR0_DSICTAS_WIDTH DSPI_DSICR0_DSICTAS_WIDTH 3007 #define SPI_DSICR0_DSICTAS(x) DSPI_DSICR0_DSICTAS(x) 3008 3009 #define SPI_DSICR0_DCONT_MASK DSPI_DSICR0_DCONT_MASK 3010 #define SPI_DSICR0_DCONT_SHIFT DSPI_DSICR0_DCONT_SHIFT 3011 #define SPI_DSICR0_DCONT_WIDTH DSPI_DSICR0_DCONT_WIDTH 3012 #define SPI_DSICR0_DCONT(x) DSPI_DSICR0_DCONT(x) 3013 3014 #define SPI_DSICR0_CID_MASK DSPI_DSICR0_CID_MASK 3015 #define SPI_DSICR0_CID_SHIFT DSPI_DSICR0_CID_SHIFT 3016 #define SPI_DSICR0_CID_WIDTH DSPI_DSICR0_CID_WIDTH 3017 #define SPI_DSICR0_CID(x) DSPI_DSICR0_CID(x) 3018 3019 #define SPI_DSICR0_TXSS_MASK DSPI_DSICR0_TXSS_MASK 3020 #define SPI_DSICR0_TXSS_SHIFT DSPI_DSICR0_TXSS_SHIFT 3021 #define SPI_DSICR0_TXSS_WIDTH DSPI_DSICR0_TXSS_WIDTH 3022 #define SPI_DSICR0_TXSS(x) DSPI_DSICR0_TXSS(x) 3023 3024 #define SPI_DSICR0_TSBC_MASK DSPI_DSICR0_TSBC_MASK 3025 #define SPI_DSICR0_TSBC_SHIFT DSPI_DSICR0_TSBC_SHIFT 3026 #define SPI_DSICR0_TSBC_WIDTH DSPI_DSICR0_TSBC_WIDTH 3027 #define SPI_DSICR0_TSBC(x) DSPI_DSICR0_TSBC(x) 3028 3029 #define SPI_DSICR0_ITSB_MASK DSPI_DSICR0_ITSB_MASK 3030 #define SPI_DSICR0_ITSB_SHIFT DSPI_DSICR0_ITSB_SHIFT 3031 #define SPI_DSICR0_ITSB_WIDTH DSPI_DSICR0_ITSB_WIDTH 3032 #define SPI_DSICR0_ITSB(x) DSPI_DSICR0_ITSB(x) 3033 3034 #define SPI_DSICR0_FMSZ5_MASK DSPI_DSICR0_FMSZ5_MASK 3035 #define SPI_DSICR0_FMSZ5_SHIFT DSPI_DSICR0_FMSZ5_SHIFT 3036 #define SPI_DSICR0_FMSZ5_WIDTH DSPI_DSICR0_FMSZ5_WIDTH 3037 #define SPI_DSICR0_FMSZ5(x) DSPI_DSICR0_FMSZ5(x) 3038 3039 #define SPI_DSICR0_FMSZ4_MASK DSPI_DSICR0_FMSZ4_MASK 3040 #define SPI_DSICR0_FMSZ4_SHIFT DSPI_DSICR0_FMSZ4_SHIFT 3041 #define SPI_DSICR0_FMSZ4_WIDTH DSPI_DSICR0_FMSZ4_WIDTH 3042 #define SPI_DSICR0_FMSZ4(x) DSPI_DSICR0_FMSZ4(x) 3043 /*! @} */ 3044 3045 /*! @name SDR0 - DSI Serialization Data Register 0 */ 3046 /*! @{ */ 3047 3048 #define SPI_SDR0_SER_DATA_MASK DSPI_SDR0_SER_DATA_MASK 3049 #define SPI_SDR0_SER_DATA_SHIFT DSPI_SDR0_SER_DATA_SHIFT 3050 #define SPI_SDR0_SER_DATA_WIDTH DSPI_SDR0_SER_DATA_WIDTH 3051 #define SPI_SDR0_SER_DATA(x) DSPI_SDR0_SER_DATA(x) 3052 /*! @} */ 3053 3054 /*! @name ASDR0 - DSI Alternate Serialization Data Register 0 */ 3055 /*! @{ */ 3056 3057 #define SPI_ASDR0_ASER_DATA_MASK DSPI_ASDR0_ASER_DATA_MASK 3058 #define SPI_ASDR0_ASER_DATA_SHIFT DSPI_ASDR0_ASER_DATA_SHIFT 3059 #define SPI_ASDR0_ASER_DATA_WIDTH DSPI_ASDR0_ASER_DATA_WIDTH 3060 #define SPI_ASDR0_ASER_DATA(x) DSPI_ASDR0_ASER_DATA(x) 3061 /*! @} */ 3062 3063 /*! @name COMPR0 - DSI Transmit Comparison Register 0 */ 3064 /*! @{ */ 3065 3066 #define SPI_COMPR0_COMP_DATA_MASK DSPI_COMPR0_COMP_DATA_MASK 3067 #define SPI_COMPR0_COMP_DATA_SHIFT DSPI_COMPR0_COMP_DATA_SHIFT 3068 #define SPI_COMPR0_COMP_DATA_WIDTH DSPI_COMPR0_COMP_DATA_WIDTH 3069 #define SPI_COMPR0_COMP_DATA(x) DSPI_COMPR0_COMP_DATA(x) 3070 /*! @} */ 3071 3072 /*! @name DDR0 - DSI Deserialization Data Register 0 */ 3073 /*! @{ */ 3074 3075 #define SPI_DDR0_DESER_DATA_MASK DSPI_DDR0_DESER_DATA_MASK 3076 #define SPI_DDR0_DESER_DATA_SHIFT DSPI_DDR0_DESER_DATA_SHIFT 3077 #define SPI_DDR0_DESER_DATA_WIDTH DSPI_DDR0_DESER_DATA_WIDTH 3078 #define SPI_DDR0_DESER_DATA(x) DSPI_DDR0_DESER_DATA(x) 3079 /*! @} */ 3080 3081 /*! @name DSICR1 - DSI Configuration Register 1 */ 3082 /*! @{ */ 3083 3084 #define SPI_DSICR1_DPCS1_x_MASK DSPI_DSICR1_DPCS1_x_MASK 3085 #define SPI_DSICR1_DPCS1_x_SHIFT DSPI_DSICR1_DPCS1_x_SHIFT 3086 #define SPI_DSICR1_DPCS1_x_WIDTH DSPI_DSICR1_DPCS1_x_WIDTH 3087 #define SPI_DSICR1_DPCS1_x(x) DSPI_DSICR1_DPCS1_x(x) 3088 3089 #define SPI_DSICR1_DSE0_MASK DSPI_DSICR1_DSE0_MASK 3090 #define SPI_DSICR1_DSE0_SHIFT DSPI_DSICR1_DSE0_SHIFT 3091 #define SPI_DSICR1_DSE0_WIDTH DSPI_DSICR1_DSE0_WIDTH 3092 #define SPI_DSICR1_DSE0(x) DSPI_DSICR1_DSE0(x) 3093 3094 #define SPI_DSICR1_DSE1_MASK DSPI_DSICR1_DSE1_MASK 3095 #define SPI_DSICR1_DSE1_SHIFT DSPI_DSICR1_DSE1_SHIFT 3096 #define SPI_DSICR1_DSE1_WIDTH DSPI_DSICR1_DSE1_WIDTH 3097 #define SPI_DSICR1_DSE1(x) DSPI_DSICR1_DSE1(x) 3098 3099 #define SPI_DSICR1_DSI64E_MASK DSPI_DSICR1_DSI64E_MASK 3100 #define SPI_DSICR1_DSI64E_SHIFT DSPI_DSICR1_DSI64E_SHIFT 3101 #define SPI_DSICR1_DSI64E_WIDTH DSPI_DSICR1_DSI64E_WIDTH 3102 #define SPI_DSICR1_DSI64E(x) DSPI_DSICR1_DSI64E(x) 3103 3104 #define SPI_DSICR1_CSE_MASK DSPI_DSICR1_CSE_MASK 3105 #define SPI_DSICR1_CSE_SHIFT DSPI_DSICR1_CSE_SHIFT 3106 #define SPI_DSICR1_CSE_WIDTH DSPI_DSICR1_CSE_WIDTH 3107 #define SPI_DSICR1_CSE(x) DSPI_DSICR1_CSE(x) 3108 3109 #define SPI_DSICR1_TSBCNT_MASK DSPI_DSICR1_TSBCNT_MASK 3110 #define SPI_DSICR1_TSBCNT_SHIFT DSPI_DSICR1_TSBCNT_SHIFT 3111 #define SPI_DSICR1_TSBCNT_WIDTH DSPI_DSICR1_TSBCNT_WIDTH 3112 #define SPI_DSICR1_TSBCNT(x) DSPI_DSICR1_TSBCNT(x) 3113 /*! @} */ 3114 3115 /*! @name SSR0 - DSI Serialization Source Select Register 0 */ 3116 /*! @{ */ 3117 3118 #define SPI_SSR0_SS_MASK DSPI_SSR0_SS_MASK 3119 #define SPI_SSR0_SS_SHIFT DSPI_SSR0_SS_SHIFT 3120 #define SPI_SSR0_SS_WIDTH DSPI_SSR0_SS_WIDTH 3121 #define SPI_SSR0_SS(x) DSPI_SSR0_SS(x) 3122 /*! @} */ 3123 3124 /*! @name DIMR0 - DSI Deserialized Data Interrupt Mask Register 0 */ 3125 /*! @{ */ 3126 3127 #define SPI_DIMR0_MASK_MASK DSPI_DIMR0_MASK_MASK 3128 #define SPI_DIMR0_MASK_SHIFT DSPI_DIMR0_MASK_SHIFT 3129 #define SPI_DIMR0_MASK_WIDTH DSPI_DIMR0_MASK_WIDTH 3130 #define SPI_DIMR0_MASK(x) DSPI_DIMR0_MASK(x) 3131 /*! @} */ 3132 3133 /*! @name DPIR0 - DSI Deserialized Data Polarity Interrupt Register 0 */ 3134 /*! @{ */ 3135 3136 #define SPI_DPIR0_DP_MASK DSPI_DPIR0_DP_MASK 3137 #define SPI_DPIR0_DP_SHIFT DSPI_DPIR0_DP_SHIFT 3138 #define SPI_DPIR0_DP_WIDTH DSPI_DPIR0_DP_WIDTH 3139 #define SPI_DPIR0_DP(x) DSPI_DPIR0_DP(x) 3140 /*! @} */ 3141 3142 /*! @name SDR1 - DSI Serialization Data Register 1 */ 3143 /*! @{ */ 3144 3145 #define SPI_SDR1_SER_DATA_MASK DSPI_SDR1_SER_DATA_MASK 3146 #define SPI_SDR1_SER_DATA_SHIFT DSPI_SDR1_SER_DATA_SHIFT 3147 #define SPI_SDR1_SER_DATA_WIDTH DSPI_SDR1_SER_DATA_WIDTH 3148 #define SPI_SDR1_SER_DATA(x) DSPI_SDR1_SER_DATA(x) 3149 /*! @} */ 3150 3151 /*! @name ASDR1 - DSI Alternate Serialization Data Register 1 */ 3152 /*! @{ */ 3153 3154 #define SPI_ASDR1_ASER_DATA_MASK DSPI_ASDR1_ASER_DATA_MASK 3155 #define SPI_ASDR1_ASER_DATA_SHIFT DSPI_ASDR1_ASER_DATA_SHIFT 3156 #define SPI_ASDR1_ASER_DATA_WIDTH DSPI_ASDR1_ASER_DATA_WIDTH 3157 #define SPI_ASDR1_ASER_DATA(x) DSPI_ASDR1_ASER_DATA(x) 3158 /*! @} */ 3159 3160 /*! @name COMPR1 - DSI Transmit Comparison Register 1 */ 3161 /*! @{ */ 3162 3163 #define SPI_COMPR1_COMP_DATA_MASK DSPI_COMPR1_COMP_DATA_MASK 3164 #define SPI_COMPR1_COMP_DATA_SHIFT DSPI_COMPR1_COMP_DATA_SHIFT 3165 #define SPI_COMPR1_COMP_DATA_WIDTH DSPI_COMPR1_COMP_DATA_WIDTH 3166 #define SPI_COMPR1_COMP_DATA(x) DSPI_COMPR1_COMP_DATA(x) 3167 /*! @} */ 3168 3169 /*! @name DDR1 - DSI Deserialization Data Register 1 */ 3170 /*! @{ */ 3171 3172 #define SPI_DDR1_DESER_DATA_MASK DSPI_DDR1_DESER_DATA_MASK 3173 #define SPI_DDR1_DESER_DATA_SHIFT DSPI_DDR1_DESER_DATA_SHIFT 3174 #define SPI_DDR1_DESER_DATA_WIDTH DSPI_DDR1_DESER_DATA_WIDTH 3175 #define SPI_DDR1_DESER_DATA(x) DSPI_DDR1_DESER_DATA(x) 3176 /*! @} */ 3177 3178 /*! @name SSR1 - DSI Serialization Source Select Register 1 */ 3179 /*! @{ */ 3180 3181 #define SPI_SSR1_SS_MASK DSPI_SSR1_SS_MASK 3182 #define SPI_SSR1_SS_SHIFT DSPI_SSR1_SS_SHIFT 3183 #define SPI_SSR1_SS_WIDTH DSPI_SSR1_SS_WIDTH 3184 #define SPI_SSR1_SS(x) DSPI_SSR1_SS(x) 3185 /*! @} */ 3186 3187 /*! @name DIMR1 - DSI Deserialized Data Interrupt Mask Register 1 */ 3188 /*! @{ */ 3189 3190 #define SPI_DIMR1_MASK_MASK DSPI_DIMR1_MASK_MASK 3191 #define SPI_DIMR1_MASK_SHIFT DSPI_DIMR1_MASK_SHIFT 3192 #define SPI_DIMR1_MASK_WIDTH DSPI_DIMR1_MASK_WIDTH 3193 #define SPI_DIMR1_MASK(x) DSPI_DIMR1_MASK(x) 3194 /*! @} */ 3195 3196 /*! @name DPIR1 - DSI Deserialized Data Polarity Interrupt Register 1 */ 3197 /*! @{ */ 3198 3199 #define SPI_DPIR1_DP_MASK DSPI_DPIR1_DP_MASK 3200 #define SPI_DPIR1_DP_SHIFT DSPI_DPIR1_DP_SHIFT 3201 #define SPI_DPIR1_DP_WIDTH DSPI_DPIR1_DP_WIDTH 3202 #define SPI_DPIR1_DP(x) DSPI_DPIR1_DP(x) 3203 /*! @} */ 3204 3205 /*! @name CTARE - Clock and Transfer Attributes Register Extended */ 3206 /*! @{ */ 3207 3208 #define SPI_CTARE_DTCP_MASK DSPI_CTARE_DTCP_MASK 3209 #define SPI_CTARE_DTCP_SHIFT DSPI_CTARE_DTCP_SHIFT 3210 #define SPI_CTARE_DTCP_WIDTH DSPI_CTARE_DTCP_WIDTH 3211 #define SPI_CTARE_DTCP(x) DSPI_CTARE_DTCP(x) 3212 3213 #define SPI_CTARE_FMSZE_MASK DSPI_CTARE_FMSZE_MASK 3214 #define SPI_CTARE_FMSZE_SHIFT DSPI_CTARE_FMSZE_SHIFT 3215 #define SPI_CTARE_FMSZE_WIDTH DSPI_CTARE_FMSZE_WIDTH 3216 #define SPI_CTARE_FMSZE(x) DSPI_CTARE_FMSZE(x) 3217 /*! @} */ 3218 3219 /*! @name SREX - Status Register Extended */ 3220 /*! @{ */ 3221 3222 #define SPI_SREX_CMDNXTPTR_MASK DSPI_SREX_CMDNXTPTR_MASK 3223 #define SPI_SREX_CMDNXTPTR_SHIFT DSPI_SREX_CMDNXTPTR_SHIFT 3224 #define SPI_SREX_CMDNXTPTR_WIDTH DSPI_SREX_CMDNXTPTR_WIDTH 3225 #define SPI_SREX_CMDNXTPTR(x) DSPI_SREX_CMDNXTPTR(x) 3226 3227 #define SPI_SREX_CMDCTR_MASK DSPI_SREX_CMDCTR_MASK 3228 #define SPI_SREX_CMDCTR_SHIFT DSPI_SREX_CMDCTR_SHIFT 3229 #define SPI_SREX_CMDCTR_WIDTH DSPI_SREX_CMDCTR_WIDTH 3230 #define SPI_SREX_CMDCTR(x) DSPI_SREX_CMDCTR(x) 3231 3232 #define SPI_SREX_RXCTR4_MASK DSPI_SREX_RXCTR4_MASK 3233 #define SPI_SREX_RXCTR4_SHIFT DSPI_SREX_RXCTR4_SHIFT 3234 #define SPI_SREX_RXCTR4_WIDTH DSPI_SREX_RXCTR4_WIDTH 3235 #define SPI_SREX_RXCTR4(x) DSPI_SREX_RXCTR4(x) 3236 3237 #define SPI_SREX_TXCTR4_MASK DSPI_SREX_TXCTR4_MASK 3238 #define SPI_SREX_TXCTR4_SHIFT DSPI_SREX_TXCTR4_SHIFT 3239 #define SPI_SREX_TXCTR4_WIDTH DSPI_SREX_TXCTR4_WIDTH 3240 #define SPI_SREX_TXCTR4(x) DSPI_SREX_TXCTR4(x) 3241 /*! @} */ 3242 3243 /*! @name TSL - Time Slot Length Register */ 3244 /*! @{ */ 3245 3246 #define SPI_TSL_TS0_LEN_MASK DSPI_TSL_TS0_LEN_MASK 3247 #define SPI_TSL_TS0_LEN_SHIFT DSPI_TSL_TS0_LEN_SHIFT 3248 #define SPI_TSL_TS0_LEN_WIDTH DSPI_TSL_TS0_LEN_WIDTH 3249 #define SPI_TSL_TS0_LEN(x) DSPI_TSL_TS0_LEN(x) 3250 3251 #define SPI_TSL_TS1_LEN_MASK DSPI_TSL_TS1_LEN_MASK 3252 #define SPI_TSL_TS1_LEN_SHIFT DSPI_TSL_TS1_LEN_SHIFT 3253 #define SPI_TSL_TS1_LEN_WIDTH DSPI_TSL_TS1_LEN_WIDTH 3254 #define SPI_TSL_TS1_LEN(x) DSPI_TSL_TS1_LEN(x) 3255 3256 #define SPI_TSL_TS2_LEN_MASK DSPI_TSL_TS2_LEN_MASK 3257 #define SPI_TSL_TS2_LEN_SHIFT DSPI_TSL_TS2_LEN_SHIFT 3258 #define SPI_TSL_TS2_LEN_WIDTH DSPI_TSL_TS2_LEN_WIDTH 3259 #define SPI_TSL_TS2_LEN(x) DSPI_TSL_TS2_LEN(x) 3260 3261 #define SPI_TSL_TS3_LEN_MASK DSPI_TSL_TS3_LEN_MASK 3262 #define SPI_TSL_TS3_LEN_SHIFT DSPI_TSL_TS3_LEN_SHIFT 3263 #define SPI_TSL_TS3_LEN_WIDTH DSPI_TSL_TS3_LEN_WIDTH 3264 #define SPI_TSL_TS3_LEN(x) DSPI_TSL_TS3_LEN(x) 3265 /*! @} */ 3266 3267 /*! @name TS_CONF - Time Slot Configuration Register */ 3268 /*! @{ */ 3269 3270 #define SPI_TS_CONF_TS0_MASK DSPI_TS_CONF_TS0_MASK 3271 #define SPI_TS_CONF_TS0_SHIFT DSPI_TS_CONF_TS0_SHIFT 3272 #define SPI_TS_CONF_TS0_WIDTH DSPI_TS_CONF_TS0_WIDTH 3273 #define SPI_TS_CONF_TS0(x) DSPI_TS_CONF_TS0(x) 3274 3275 #define SPI_TS_CONF_TS1_MASK DSPI_TS_CONF_TS1_MASK 3276 #define SPI_TS_CONF_TS1_SHIFT DSPI_TS_CONF_TS1_SHIFT 3277 #define SPI_TS_CONF_TS1_WIDTH DSPI_TS_CONF_TS1_WIDTH 3278 #define SPI_TS_CONF_TS1(x) DSPI_TS_CONF_TS1(x) 3279 3280 #define SPI_TS_CONF_TS2_MASK DSPI_TS_CONF_TS2_MASK 3281 #define SPI_TS_CONF_TS2_SHIFT DSPI_TS_CONF_TS2_SHIFT 3282 #define SPI_TS_CONF_TS2_WIDTH DSPI_TS_CONF_TS2_WIDTH 3283 #define SPI_TS_CONF_TS2(x) DSPI_TS_CONF_TS2(x) 3284 3285 #define SPI_TS_CONF_TS3_MASK DSPI_TS_CONF_TS3_MASK 3286 #define SPI_TS_CONF_TS3_SHIFT DSPI_TS_CONF_TS3_SHIFT 3287 #define SPI_TS_CONF_TS3_WIDTH DSPI_TS_CONF_TS3_WIDTH 3288 #define SPI_TS_CONF_TS3(x) DSPI_TS_CONF_TS3(x) 3289 /*! @} */ 3290 3291 /* end of group DSPI_Register_Masks */ 3292 3293 /*! 3294 * @} 3295 */ /* end of group DSPI_Peripheral_Access_Layer */ 3296 3297 #endif /* _S32Z270_DEVICE_H_ */ 3298
