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Searched refs:SPI_CTAR_PCSSCK_MASK (Results 1 – 25 of 36) sorted by relevance

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/hal_nxp-latest/s32/drivers/s32ze/BaseNXP/header/
DS32Z2_SPI.h302 #define SPI_CTAR_PCSSCK_MASK (0xC00000U) macro
305 … (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PCSSCK_SHIFT)) & SPI_CTAR_PCSSCK_MASK)
/hal_nxp-latest/mcux/mcux-sdk/drivers/dspi/
Dfsl_dspi.c539 …base->CTAR[whichCtar] = (base->CTAR[whichCtar] & (~SPI_CTAR_PCSSCK_MASK) & (~SPI_CTAR_CSSCK_MASK))… in DSPI_MasterSetDelayScaler()
/hal_nxp-latest/s32/mcux/devices/S32Z270/
DS32Z270_device.h2678 #define SPI_CTAR_PCSSCK_MASK DSPI_CTAR_PCSSCK_MASK macro
/hal_nxp-latest/mcux/mcux-sdk/devices/MK02F12810/
DMK02F12810.h9269 #define SPI_CTAR_PCSSCK_MASK (0xC00000U) macro
9277 … (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PCSSCK_SHIFT)) & SPI_CTAR_PCSSCK_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKV30F12810/
DMKV30F12810.h9302 #define SPI_CTAR_PCSSCK_MASK (0xC00000U) macro
9310 … (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PCSSCK_SHIFT)) & SPI_CTAR_PCSSCK_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKV10Z7/
DMKV10Z7.h9205 #define SPI_CTAR_PCSSCK_MASK (0xC00000U) macro
9213 … (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PCSSCK_SHIFT)) & SPI_CTAR_PCSSCK_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKV31F12810/
DMKV31F12810.h10088 #define SPI_CTAR_PCSSCK_MASK (0xC00000U) macro
10096 … (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PCSSCK_SHIFT)) & SPI_CTAR_PCSSCK_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKV10Z1287/
DMKV10Z1287.h10241 #define SPI_CTAR_PCSSCK_MASK (0xC00000U) macro
10249 … (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PCSSCK_SHIFT)) & SPI_CTAR_PCSSCK_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKV11Z7/
DMKV11Z7.h11029 #define SPI_CTAR_PCSSCK_MASK (0xC00000U) macro
11037 … (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PCSSCK_SHIFT)) & SPI_CTAR_PCSSCK_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKV31F25612/
DMKV31F25612.h11159 #define SPI_CTAR_PCSSCK_MASK (0xC00000U) macro
11167 … (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PCSSCK_SHIFT)) & SPI_CTAR_PCSSCK_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKV31F51212/
DMKV31F51212.h11547 #define SPI_CTAR_PCSSCK_MASK (0xC00000U) macro
11555 … (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PCSSCK_SHIFT)) & SPI_CTAR_PCSSCK_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MK22F12810/
DMK22F12810.h11354 #define SPI_CTAR_PCSSCK_MASK (0xC00000U) macro
11362 … (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PCSSCK_SHIFT)) & SPI_CTAR_PCSSCK_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKW22D5/
DMKW22D5.h6966 #define SPI_CTAR_PCSSCK_MASK (0xC00000U) macro
6968 … (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PCSSCK_SHIFT)) & SPI_CTAR_PCSSCK_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKW24D5/
DMKW24D5.h6966 #define SPI_CTAR_PCSSCK_MASK (0xC00000U) macro
6968 … (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PCSSCK_SHIFT)) & SPI_CTAR_PCSSCK_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MK22F25612/
DMK22F25612.h12474 #define SPI_CTAR_PCSSCK_MASK (0xC00000U) macro
12482 … (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PCSSCK_SHIFT)) & SPI_CTAR_PCSSCK_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MK22F51212/
DMK22F51212.h12872 #define SPI_CTAR_PCSSCK_MASK (0xC00000U) macro
12880 … (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PCSSCK_SHIFT)) & SPI_CTAR_PCSSCK_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MK22F12/
DMK22F12.h17141 #define SPI_CTAR_PCSSCK_MASK (0xC00000U) macro
17149 … (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PCSSCK_SHIFT)) & SPI_CTAR_PCSSCK_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MK24F12/
DMK24F12.h20797 #define SPI_CTAR_PCSSCK_MASK (0xC00000U) macro
20805 … (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PCSSCK_SHIFT)) & SPI_CTAR_PCSSCK_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKW31Z4/
DMKW31Z4.h6788 #define SPI_CTAR_PCSSCK_MASK (0xC00000U) macro
6790 … (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PCSSCK_SHIFT)) & SPI_CTAR_PCSSCK_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKW30Z4/
DMKW30Z4.h7515 #define SPI_CTAR_PCSSCK_MASK 0xC00000u macro
7518 …) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_PCSSCK_SHIFT))&SPI_CTAR_PCSSCK_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKW21Z4/
DMKW21Z4.h6717 #define SPI_CTAR_PCSSCK_MASK (0xC00000U) macro
6719 … (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PCSSCK_SHIFT)) & SPI_CTAR_PCSSCK_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKW20Z4/
DMKW20Z4.h7515 #define SPI_CTAR_PCSSCK_MASK 0xC00000u macro
7518 …) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_PCSSCK_SHIFT))&SPI_CTAR_PCSSCK_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MK64F12/
DMK64F12.h22654 #define SPI_CTAR_PCSSCK_MASK (0xC00000U) macro
22662 … (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PCSSCK_SHIFT)) & SPI_CTAR_PCSSCK_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MK63F12/
DMK63F12.h22608 #define SPI_CTAR_PCSSCK_MASK (0xC00000U) macro
22616 … (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PCSSCK_SHIFT)) & SPI_CTAR_PCSSCK_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKW41Z4/
DMKW41Z4.h6788 #define SPI_CTAR_PCSSCK_MASK (0xC00000U) macro
6790 … (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PCSSCK_SHIFT)) & SPI_CTAR_PCSSCK_MASK)

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