1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2024 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32Z2_SPFU.h 10 * @version 2.3 11 * @date 2024-05-03 12 * @brief Peripheral Access Layer for S32Z2_SPFU 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32Z2_SPFU_H_) /* Check if memory map has not been already included */ 58 #define S32Z2_SPFU_H_ 59 60 #include "S32Z2_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- SPFU Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup SPFU_Peripheral_Access_Layer SPFU Peripheral Access Layer 68 * @{ 69 */ 70 71 /** SPFU - Size of Registers Arrays */ 72 #define SPFU_PFN_COUNT 5u 73 74 /** SPFU - Register Layout Typedef */ 75 typedef struct { 76 struct SPFU_PFN { /* offset: 0x0, array step: 0x100 */ 77 __IO uint32_t PF_CFG; /**< Prefetch Configuration, array offset: 0x0, array step: 0x100 */ 78 uint8_t RESERVED_0[252]; 79 } PFN[SPFU_PFN_COUNT]; 80 } SPFU_Type, *SPFU_MemMapPtr; 81 82 /** Number of instances of the SPFU module. */ 83 #define SPFU_INSTANCE_COUNT (2u) 84 85 /* SPFU - Peripheral instance base addresses */ 86 /** Peripheral RTU0__SPFU base address */ 87 #define IP_RTU0__SPFU_BASE (0x76060000u) 88 /** Peripheral RTU0__SPFU base pointer */ 89 #define IP_RTU0__SPFU ((SPFU_Type *)IP_RTU0__SPFU_BASE) 90 /** Peripheral RTU1__SPFU base address */ 91 #define IP_RTU1__SPFU_BASE (0x76860000u) 92 /** Peripheral RTU1__SPFU base pointer */ 93 #define IP_RTU1__SPFU ((SPFU_Type *)IP_RTU1__SPFU_BASE) 94 /** Array initializer of SPFU peripheral base addresses */ 95 #define IP_SPFU_BASE_ADDRS { IP_RTU0__SPFU_BASE, IP_RTU1__SPFU_BASE } 96 /** Array initializer of SPFU peripheral base pointers */ 97 #define IP_SPFU_BASE_PTRS { IP_RTU0__SPFU, IP_RTU1__SPFU } 98 99 /* ---------------------------------------------------------------------------- 100 -- SPFU Register Masks 101 ---------------------------------------------------------------------------- */ 102 103 /*! 104 * @addtogroup SPFU_Register_Masks SPFU Register Masks 105 * @{ 106 */ 107 108 /*! @name PF_CFG - Prefetch Configuration */ 109 /*! @{ */ 110 111 #define SPFU_PF_CFG_PFEN_MASK (0x1U) 112 #define SPFU_PF_CFG_PFEN_SHIFT (0U) 113 #define SPFU_PF_CFG_PFEN_WIDTH (1U) 114 #define SPFU_PF_CFG_PFEN(x) (((uint32_t)(((uint32_t)(x)) << SPFU_PF_CFG_PFEN_SHIFT)) & SPFU_PF_CFG_PFEN_MASK) 115 116 #define SPFU_PF_CFG_DID_MASK (0xF00U) 117 #define SPFU_PF_CFG_DID_SHIFT (8U) 118 #define SPFU_PF_CFG_DID_WIDTH (4U) 119 #define SPFU_PF_CFG_DID(x) (((uint32_t)(((uint32_t)(x)) << SPFU_PF_CFG_DID_SHIFT)) & SPFU_PF_CFG_DID_MASK) 120 121 #define SPFU_PF_CFG_THRSHLD_MASK (0xF0000U) 122 #define SPFU_PF_CFG_THRSHLD_SHIFT (16U) 123 #define SPFU_PF_CFG_THRSHLD_WIDTH (4U) 124 #define SPFU_PF_CFG_THRSHLD(x) (((uint32_t)(((uint32_t)(x)) << SPFU_PF_CFG_THRSHLD_SHIFT)) & SPFU_PF_CFG_THRSHLD_MASK) 125 126 #define SPFU_PF_CFG_PF_SIZE_MASK (0xF000000U) 127 #define SPFU_PF_CFG_PF_SIZE_SHIFT (24U) 128 #define SPFU_PF_CFG_PF_SIZE_WIDTH (4U) 129 #define SPFU_PF_CFG_PF_SIZE(x) (((uint32_t)(((uint32_t)(x)) << SPFU_PF_CFG_PF_SIZE_SHIFT)) & SPFU_PF_CFG_PF_SIZE_MASK) 130 /*! @} */ 131 132 /*! 133 * @} 134 */ /* end of group SPFU_Register_Masks */ 135 136 /*! 137 * @} 138 */ /* end of group SPFU_Peripheral_Access_Layer */ 139 140 #endif /* #if !defined(S32Z2_SPFU_H_) */ 141
