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Searched refs:SOCCR (Results 1 – 25 of 27) sorted by relevance

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/hal_nxp-latest/mcux/mcux-sdk/drivers/qspi/
Dfsl_qspi.c131 base->SOCCR = config->clockSource; in QSPI_Init()
298 soccrVal = base->SOCCR; in QSPI_SetDqsConfig()
332 base->SOCCR = soccrVal; in QSPI_SetDqsConfig()
461 soccrVal = base->SOCCR; in QSPI_ClearCache()
463 base->SOCCR = (soccrVal | QuadSPI_SOCCR_CLR_LPCAC_MASK); in QSPI_ClearCache()
466 base->SOCCR = (soccrVal & (~QuadSPI_SOCCR_CLR_LPCAC_MASK)); in QSPI_ClearCache()
/hal_nxp-latest/s32/drivers/s32k3/Fls/src/
DQspi_Ip_Controller.c1958 BaseAddr->SOCCR = (uint32)0x00000000UL; in Qspi_Ip_ResetAllRegisters()
2025 BaseAddr->SOCCR = (uint32)0x00000000UL; in Qspi_Ip_ResetAllRegisters()
/hal_nxp-latest/s32/drivers/s32k1/BaseNXP/header/
DS32K148_QUADSPI.h86 __IO uint32_t SOCCR; /**< SOC Configuration Register, offset: 0x24 */ member
/hal_nxp-latest/s32/drivers/s32k3/BaseNXP/header/
DS32K344_QUADSPI.h86 __IO uint32_t SOCCR; /**< SOC Configuration Register, offset: 0x24 */ member
/hal_nxp-latest/s32/drivers/s32k3/Fls/include/
DQspi_Ip_HwAccess.h1011 BaseAddr->SOCCR = Option; in Qspi_Ip_SetChipOptions()
/hal_nxp-latest/s32/drivers/s32ze/Mem_EXFLS/include/
DQspi_Ip_HwAccess.h1425 BaseAddr->SOCCR = Option; in Qspi_Ip_SetChipOptions()
/hal_nxp-latest/s32/drivers/s32k1/Mcu/src/
DClock_Ip_Frequency.c1487 …DivConfig = (uint8)((IP_QuadSPI->SOCCR & QuadSPI_SOCCR_SOCCFG_DIV_MASK) >> QuadSPI_SOCCR_SOCCFG_DI… in get_QSPI_SFIF_CLK_HYP_PREMUX_CLK_Frequency()
/hal_nxp-latest/s32/drivers/s32ze/BaseNXP/header/
DS32Z2_QUADSPI.h88 __IO uint32_t SOCCR; /**< SOC Configuration Register, offset: 0x24 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MK80F25615/
DMK80F25615.h18264 __IO uint32_t SOCCR; /**< SOC Configuration Register, offset: 0x24 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MK82F25615/
DMK82F25615.h19237 __IO uint32_t SOCCR; /**< SOC Configuration Register, offset: 0x24 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MK28FA15/
DMK28FA15.h17768 __IO uint32_t SOCCR; /**< SOC Configuration Register, offset: 0x24 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MK27FA15/
DMK27FA15.h17766 __IO uint32_t SOCCR; /**< SOC Configuration Register, offset: 0x24 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MCIMX7U3/
DMCIMX7U3_cm4.h27213 __IO uint32_t SOCCR; /**< SOC Configuration Register, offset: 0x24 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MCIMX7U5/
DMCIMX7U5_cm4.h27214 __IO uint32_t SOCCR; /**< SOC Configuration Register, offset: 0x24 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT735S/
DMIMXRT735S_hifi1.h63472 __IO uint32_t SOCCR; /**< SOC Configuration, offset: 0x24 */ member
DMIMXRT735S_cm33_core1.h63541 __IO uint32_t SOCCR; /**< SOC Configuration, offset: 0x24 */ member
DMIMXRT735S_ezhv.h92326 __IO uint32_t SOCCR; /**< SOC Configuration, offset: 0x24 */ member
DMIMXRT735S_cm33_core0.h87700 __IO uint32_t SOCCR; /**< SOC Configuration, offset: 0x24 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT758S/
DMIMXRT758S_cm33_core1.h66764 __IO uint32_t SOCCR; /**< SOC Configuration, offset: 0x24 */ member
DMIMXRT758S_hifi1.h66693 __IO uint32_t SOCCR; /**< SOC Configuration, offset: 0x24 */ member
DMIMXRT758S_cm33_core0.h90925 __IO uint32_t SOCCR; /**< SOC Configuration, offset: 0x24 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT798S/
DMIMXRT798S_hifi1.h66693 __IO uint32_t SOCCR; /**< SOC Configuration, offset: 0x24 */ member
DMIMXRT798S_cm33_core1.h66764 __IO uint32_t SOCCR; /**< SOC Configuration, offset: 0x24 */ member
DMIMXRT798S_hifi4.h90824 __IO uint32_t SOCCR; /**< SOC Configuration, offset: 0x24 */ member
DMIMXRT798S_cm33_core0.h90925 __IO uint32_t SOCCR; /**< SOC Configuration, offset: 0x24 */ member

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