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Searched refs:SNVS_LPSR_VTD_MASK (Results 1 – 14 of 14) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/drivers/snvs_lp/
Dfsl_snvs_lp.c1261 … return ((SNVS->LPSR & SNVS_LPSR_VTD_MASK) != 0U) ? kSNVS_TamperDetected : kSNVS_TamperNotDetected; in SNVS_LP_CheckVoltageTamper()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1011/
DMIMXRT1011.h27730 #define SNVS_LPSR_VTD_MASK (0x40U) macro
27736 … (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_VTD_SHIFT)) & SNVS_LPSR_VTD_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1175/
DMIMXRT1175_cm4.h68059 #define SNVS_LPSR_VTD_MASK (0x40U) macro
68065 … (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_VTD_SHIFT)) & SNVS_LPSR_VTD_MASK)
DMIMXRT1175_cm7.h67157 #define SNVS_LPSR_VTD_MASK (0x40U) macro
67163 … (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_VTD_SHIFT)) & SNVS_LPSR_VTD_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1165/
DMIMXRT1165_cm7.h66655 #define SNVS_LPSR_VTD_MASK (0x40U) macro
66661 … (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_VTD_SHIFT)) & SNVS_LPSR_VTD_MASK)
DMIMXRT1165_cm4.h67557 #define SNVS_LPSR_VTD_MASK (0x40U) macro
67563 … (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_VTD_SHIFT)) & SNVS_LPSR_VTD_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1171/
DMIMXRT1171.h67157 #define SNVS_LPSR_VTD_MASK (0x40U) macro
67163 … (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_VTD_SHIFT)) & SNVS_LPSR_VTD_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1166/
DMIMXRT1166_cm4.h73020 #define SNVS_LPSR_VTD_MASK (0x40U) macro
73026 … (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_VTD_SHIFT)) & SNVS_LPSR_VTD_MASK)
DMIMXRT1166_cm7.h72118 #define SNVS_LPSR_VTD_MASK (0x40U) macro
72124 … (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_VTD_SHIFT)) & SNVS_LPSR_VTD_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1173/
DMIMXRT1173_cm4.h73519 #define SNVS_LPSR_VTD_MASK (0x40U) macro
73525 … (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_VTD_SHIFT)) & SNVS_LPSR_VTD_MASK)
DMIMXRT1173_cm7.h72617 #define SNVS_LPSR_VTD_MASK (0x40U) macro
72623 … (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_VTD_SHIFT)) & SNVS_LPSR_VTD_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1172/
DMIMXRT1172.h72620 #define SNVS_LPSR_VTD_MASK (0x40U) macro
72626 … (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_VTD_SHIFT)) & SNVS_LPSR_VTD_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1176/
DMIMXRT1176_cm7.h83287 #define SNVS_LPSR_VTD_MASK (0x40U) macro
83293 … (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_VTD_SHIFT)) & SNVS_LPSR_VTD_MASK)
DMIMXRT1176_cm4.h84189 #define SNVS_LPSR_VTD_MASK (0x40U) macro
84195 … (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_VTD_SHIFT)) & SNVS_LPSR_VTD_MASK)