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Searched refs:SNVS_LPSR_ET2D_MASK (Results 1 – 14 of 14) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/drivers/snvs_lp/
Dfsl_snvs_lp.c862 …status = (bool)(base->LPSR & SNVS_LPSR_ET2D_MASK) ? kSNVS_TamperDetected : kSNVS_TamperNotDetected; in SNVS_LP_GetExternalTamperStatus()
913 base->LPSR |= SNVS_LPSR_ET2D_MASK; in SNVS_LP_ClearExternalTamperStatus()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1011/
DMIMXRT1011.h27762 #define SNVS_LPSR_ET2D_MASK (0x400U) macro
27768 … (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_ET2D_SHIFT)) & SNVS_LPSR_ET2D_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1175/
DMIMXRT1175_cm4.h68091 #define SNVS_LPSR_ET2D_MASK (0x400U) macro
68097 … (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_ET2D_SHIFT)) & SNVS_LPSR_ET2D_MASK)
DMIMXRT1175_cm7.h67189 #define SNVS_LPSR_ET2D_MASK (0x400U) macro
67195 … (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_ET2D_SHIFT)) & SNVS_LPSR_ET2D_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1165/
DMIMXRT1165_cm7.h66687 #define SNVS_LPSR_ET2D_MASK (0x400U) macro
66693 … (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_ET2D_SHIFT)) & SNVS_LPSR_ET2D_MASK)
DMIMXRT1165_cm4.h67589 #define SNVS_LPSR_ET2D_MASK (0x400U) macro
67595 … (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_ET2D_SHIFT)) & SNVS_LPSR_ET2D_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1171/
DMIMXRT1171.h67189 #define SNVS_LPSR_ET2D_MASK (0x400U) macro
67195 … (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_ET2D_SHIFT)) & SNVS_LPSR_ET2D_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1166/
DMIMXRT1166_cm4.h73052 #define SNVS_LPSR_ET2D_MASK (0x400U) macro
73058 … (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_ET2D_SHIFT)) & SNVS_LPSR_ET2D_MASK)
DMIMXRT1166_cm7.h72150 #define SNVS_LPSR_ET2D_MASK (0x400U) macro
72156 … (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_ET2D_SHIFT)) & SNVS_LPSR_ET2D_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1173/
DMIMXRT1173_cm4.h73551 #define SNVS_LPSR_ET2D_MASK (0x400U) macro
73557 … (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_ET2D_SHIFT)) & SNVS_LPSR_ET2D_MASK)
DMIMXRT1173_cm7.h72649 #define SNVS_LPSR_ET2D_MASK (0x400U) macro
72655 … (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_ET2D_SHIFT)) & SNVS_LPSR_ET2D_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1172/
DMIMXRT1172.h72652 #define SNVS_LPSR_ET2D_MASK (0x400U) macro
72658 … (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_ET2D_SHIFT)) & SNVS_LPSR_ET2D_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1176/
DMIMXRT1176_cm7.h83319 #define SNVS_LPSR_ET2D_MASK (0x400U) macro
83325 … (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_ET2D_SHIFT)) & SNVS_LPSR_ET2D_MASK)
DMIMXRT1176_cm4.h84221 #define SNVS_LPSR_ET2D_MASK (0x400U) macro
84227 … (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_ET2D_SHIFT)) & SNVS_LPSR_ET2D_MASK)