Searched refs:SNVS_HPSVCR_WDOG2_CFG_MASK (Results 1 – 12 of 12) sorted by relevance
67302 #define SNVS_HPSVCR_WDOG2_CFG_MASK (0x4U) macro67308 … (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_WDOG2_CFG_SHIFT)) & SNVS_HPSVCR_WDOG2_CFG_MASK)
66400 #define SNVS_HPSVCR_WDOG2_CFG_MASK (0x4U) macro66406 … (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_WDOG2_CFG_SHIFT)) & SNVS_HPSVCR_WDOG2_CFG_MASK)
65898 #define SNVS_HPSVCR_WDOG2_CFG_MASK (0x4U) macro65904 … (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_WDOG2_CFG_SHIFT)) & SNVS_HPSVCR_WDOG2_CFG_MASK)
66800 #define SNVS_HPSVCR_WDOG2_CFG_MASK (0x4U) macro66806 … (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_WDOG2_CFG_SHIFT)) & SNVS_HPSVCR_WDOG2_CFG_MASK)
72263 #define SNVS_HPSVCR_WDOG2_CFG_MASK (0x4U) macro72269 … (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_WDOG2_CFG_SHIFT)) & SNVS_HPSVCR_WDOG2_CFG_MASK)
71361 #define SNVS_HPSVCR_WDOG2_CFG_MASK (0x4U) macro71367 … (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_WDOG2_CFG_SHIFT)) & SNVS_HPSVCR_WDOG2_CFG_MASK)
72762 #define SNVS_HPSVCR_WDOG2_CFG_MASK (0x4U) macro72768 … (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_WDOG2_CFG_SHIFT)) & SNVS_HPSVCR_WDOG2_CFG_MASK)
71860 #define SNVS_HPSVCR_WDOG2_CFG_MASK (0x4U) macro71866 … (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_WDOG2_CFG_SHIFT)) & SNVS_HPSVCR_WDOG2_CFG_MASK)
71863 #define SNVS_HPSVCR_WDOG2_CFG_MASK (0x4U) macro71869 … (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_WDOG2_CFG_SHIFT)) & SNVS_HPSVCR_WDOG2_CFG_MASK)
82530 #define SNVS_HPSVCR_WDOG2_CFG_MASK (0x4U) macro82536 … (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_WDOG2_CFG_SHIFT)) & SNVS_HPSVCR_WDOG2_CFG_MASK)
83432 #define SNVS_HPSVCR_WDOG2_CFG_MASK (0x4U) macro83438 … (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_WDOG2_CFG_SHIFT)) & SNVS_HPSVCR_WDOG2_CFG_MASK)
