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Searched refs:SNVS_HPCR_DIS_PI_MASK (Results 1 – 25 of 30) sorted by relevance

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/hal_nxp-latest/mcux/mcux-sdk/devices/MCIMX7U3/
DMCIMX7U3_cm4.h32467 #define SNVS_HPCR_DIS_PI_MASK (0x4U) macro
32473 … (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_DIS_PI_SHIFT)) & SNVS_HPCR_DIS_PI_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCIMX7U5/
DMCIMX7U5_cm4.h32468 #define SNVS_HPCR_DIS_PI_MASK (0x4U) macro
32474 … (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_DIS_PI_SHIFT)) & SNVS_HPCR_DIS_PI_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1011/
DMIMXRT1011.h26829 #define SNVS_HPCR_DIS_PI_MASK (0x4U) macro
26835 … (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_DIS_PI_SHIFT)) & SNVS_HPCR_DIS_PI_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1015/
DMIMXRT1015.h29431 #define SNVS_HPCR_DIS_PI_MASK (0x4U) macro
29437 … (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_DIS_PI_SHIFT)) & SNVS_HPCR_DIS_PI_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1024/
DMIMXRT1024.h34710 #define SNVS_HPCR_DIS_PI_MASK (0x4U) macro
34716 … (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_DIS_PI_SHIFT)) & SNVS_HPCR_DIS_PI_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1021/
DMIMXRT1021.h34731 #define SNVS_HPCR_DIS_PI_MASK (0x4U) macro
34737 … (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_DIS_PI_SHIFT)) & SNVS_HPCR_DIS_PI_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1051/
DMIMXRT1051.h36281 #define SNVS_HPCR_DIS_PI_MASK (0x4U) macro
36287 … (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_DIS_PI_SHIFT)) & SNVS_HPCR_DIS_PI_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1041/
DMIMXRT1041.h37723 #define SNVS_HPCR_DIS_PI_MASK (0x4U) macro
37729 … (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_DIS_PI_SHIFT)) & SNVS_HPCR_DIS_PI_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1052/
DMIMXRT1052.h40547 #define SNVS_HPCR_DIS_PI_MASK (0x4U) macro
40553 … (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_DIS_PI_SHIFT)) & SNVS_HPCR_DIS_PI_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1042/
DMIMXRT1042.h41133 #define SNVS_HPCR_DIS_PI_MASK (0x4U) macro
41139 … (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_DIS_PI_SHIFT)) & SNVS_HPCR_DIS_PI_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1061/
DMIMXRT1061.h38607 #define SNVS_HPCR_DIS_PI_MASK (0x4U) macro
38613 … (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_DIS_PI_SHIFT)) & SNVS_HPCR_DIS_PI_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1064/
DMIMXRT1064.h42808 #define SNVS_HPCR_DIS_PI_MASK (0x4U) macro
42814 … (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_DIS_PI_SHIFT)) & SNVS_HPCR_DIS_PI_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MQ5/
DMIMX8MQ5_cm4.h49238 #define SNVS_HPCR_DIS_PI_MASK (0x4U) macro
49244 … (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_DIS_PI_SHIFT)) & SNVS_HPCR_DIS_PI_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1062/
DMIMXRT1062.h42801 #define SNVS_HPCR_DIS_PI_MASK (0x4U) macro
42807 … (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_DIS_PI_SHIFT)) & SNVS_HPCR_DIS_PI_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MD7/
DMIMX8MD7_cm4.h51411 #define SNVS_HPCR_DIS_PI_MASK (0x4U) macro
51417 … (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_DIS_PI_SHIFT)) & SNVS_HPCR_DIS_PI_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MD6/
DMIMX8MD6_cm4.h51411 #define SNVS_HPCR_DIS_PI_MASK (0x4U) macro
51417 … (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_DIS_PI_SHIFT)) & SNVS_HPCR_DIS_PI_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MQ6/
DMIMX8MQ6_cm4.h51411 #define SNVS_HPCR_DIS_PI_MASK (0x4U) macro
51417 … (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_DIS_PI_SHIFT)) & SNVS_HPCR_DIS_PI_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MQ7/
DMIMX8MQ7_cm4.h51411 #define SNVS_HPCR_DIS_PI_MASK (0x4U) macro
51417 … (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_DIS_PI_SHIFT)) & SNVS_HPCR_DIS_PI_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1175/
DMIMXRT1175_cm4.h67154 #define SNVS_HPCR_DIS_PI_MASK (0x4U) macro
67160 … (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_DIS_PI_SHIFT)) & SNVS_HPCR_DIS_PI_MASK)
DMIMXRT1175_cm7.h66252 #define SNVS_HPCR_DIS_PI_MASK (0x4U) macro
66258 … (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_DIS_PI_SHIFT)) & SNVS_HPCR_DIS_PI_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1165/
DMIMXRT1165_cm7.h65750 #define SNVS_HPCR_DIS_PI_MASK (0x4U) macro
65756 … (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_DIS_PI_SHIFT)) & SNVS_HPCR_DIS_PI_MASK)
DMIMXRT1165_cm4.h66652 #define SNVS_HPCR_DIS_PI_MASK (0x4U) macro
66658 … (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_DIS_PI_SHIFT)) & SNVS_HPCR_DIS_PI_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1171/
DMIMXRT1171.h66252 #define SNVS_HPCR_DIS_PI_MASK (0x4U) macro
66258 … (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_DIS_PI_SHIFT)) & SNVS_HPCR_DIS_PI_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1166/
DMIMXRT1166_cm4.h72115 #define SNVS_HPCR_DIS_PI_MASK (0x4U) macro
72121 … (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_DIS_PI_SHIFT)) & SNVS_HPCR_DIS_PI_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1173/
DMIMXRT1173_cm4.h72614 #define SNVS_HPCR_DIS_PI_MASK (0x4U) macro
72620 … (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_DIS_PI_SHIFT)) & SNVS_HPCR_DIS_PI_MASK)

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