1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2024 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32Z2_MULTICORE_CONFIGURATION.h 10 * @version 2.3 11 * @date 2024-05-03 12 * @brief Peripheral Access Layer for S32Z2_MULTICORE_CONFIGURATION 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32Z2_MULTICORE_CONFIGURATION_H_) /* Check if memory map has not been already included */ 58 #define S32Z2_MULTICORE_CONFIGURATION_H_ 59 60 #include "S32Z2_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- MULTICORE_CONFIGURATION Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup MULTICORE_CONFIGURATION_Peripheral_Access_Layer MULTICORE_CONFIGURATION Peripheral Access Layer 68 * @{ 69 */ 70 71 /** MULTICORE_CONFIGURATION - Size of Registers Arrays */ 72 #define MULTICORE_CONFIGURATION_COM_REGX_COUNT 8u 73 74 /** MULTICORE_CONFIGURATION - Register Layout Typedef */ 75 typedef struct { 76 __IO uint32_t COM_REGX[MULTICORE_CONFIGURATION_COM_REGX_COUNT]; /**< MCCI Message Register, array offset: 0x0, array step: 0x4 */ 77 uint8_t RESERVED_0[96]; 78 __IO uint32_t COM_STS; /**< MCCI Status, offset: 0x80 */ 79 __IO uint32_t COM_INT_EN; /**< MCCI Interrupt Enable, offset: 0x84 */ 80 uint8_t RESERVED_1[8]; 81 __IO uint32_t START_ADDR0; /**< IDM Snoop Start Address 0, offset: 0x90 */ 82 __IO uint32_t TOP_ADDR0; /**< IDM Snoop End Address 0, offset: 0x94 */ 83 __IO uint32_t SNOOP_CSR0; /**< IDM Snoop Control 0, offset: 0x98 */ 84 __IO uint32_t START_ADDR1; /**< IDM Snoop Start Address 1, offset: 0x9C */ 85 __IO uint32_t TOP_ADDR1; /**< IDM Snoop End Address 1, offset: 0xA0 */ 86 __IO uint32_t SNOOP_CSR1; /**< IDM Snoop Control 1, offset: 0xA4 */ 87 } MULTICORE_CONFIGURATION_Type, *MULTICORE_CONFIGURATION_MemMapPtr; 88 89 /** Number of instances of the MULTICORE_CONFIGURATION module. */ 90 #define MULTICORE_CONFIGURATION_INSTANCE_COUNT (1u) 91 92 /* MULTICORE_CONFIGURATION - Peripheral instance base addresses */ 93 /** Peripheral CEVA_SPF2__MULTICORE_CONFIGURATION base address */ 94 #define IP_CEVA_SPF2__MULTICORE_CONFIGURATION_BASE (0x24400000u) 95 /** Peripheral CEVA_SPF2__MULTICORE_CONFIGURATION base pointer */ 96 #define IP_CEVA_SPF2__MULTICORE_CONFIGURATION ((MULTICORE_CONFIGURATION_Type *)IP_CEVA_SPF2__MULTICORE_CONFIGURATION_BASE) 97 /** Array initializer of MULTICORE_CONFIGURATION peripheral base addresses */ 98 #define IP_MULTICORE_CONFIGURATION_BASE_ADDRS { IP_CEVA_SPF2__MULTICORE_CONFIGURATION_BASE } 99 /** Array initializer of MULTICORE_CONFIGURATION peripheral base pointers */ 100 #define IP_MULTICORE_CONFIGURATION_BASE_PTRS { IP_CEVA_SPF2__MULTICORE_CONFIGURATION } 101 102 /* ---------------------------------------------------------------------------- 103 -- MULTICORE_CONFIGURATION Register Masks 104 ---------------------------------------------------------------------------- */ 105 106 /*! 107 * @addtogroup MULTICORE_CONFIGURATION_Register_Masks MULTICORE_CONFIGURATION Register Masks 108 * @{ 109 */ 110 111 /*! @name COM_REGX - MCCI Message Register */ 112 /*! @{ */ 113 114 #define MULTICORE_CONFIGURATION_COM_REGX_COM_REG_MASK (0xFFFFFFFFU) 115 #define MULTICORE_CONFIGURATION_COM_REGX_COM_REG_SHIFT (0U) 116 #define MULTICORE_CONFIGURATION_COM_REGX_COM_REG_WIDTH (32U) 117 #define MULTICORE_CONFIGURATION_COM_REGX_COM_REG(x) (((uint32_t)(((uint32_t)(x)) << MULTICORE_CONFIGURATION_COM_REGX_COM_REG_SHIFT)) & MULTICORE_CONFIGURATION_COM_REGX_COM_REG_MASK) 118 /*! @} */ 119 120 /*! @name COM_STS - MCCI Status */ 121 /*! @{ */ 122 123 #define MULTICORE_CONFIGURATION_COM_STS_COM_STS_MASK (0xFFU) 124 #define MULTICORE_CONFIGURATION_COM_STS_COM_STS_SHIFT (0U) 125 #define MULTICORE_CONFIGURATION_COM_STS_COM_STS_WIDTH (8U) 126 #define MULTICORE_CONFIGURATION_COM_STS_COM_STS(x) (((uint32_t)(((uint32_t)(x)) << MULTICORE_CONFIGURATION_COM_STS_COM_STS_SHIFT)) & MULTICORE_CONFIGURATION_COM_STS_COM_STS_MASK) 127 /*! @} */ 128 129 /*! @name COM_INT_EN - MCCI Interrupt Enable */ 130 /*! @{ */ 131 132 #define MULTICORE_CONFIGURATION_COM_INT_EN_COM_INT_EN_MASK (0xFFU) 133 #define MULTICORE_CONFIGURATION_COM_INT_EN_COM_INT_EN_SHIFT (0U) 134 #define MULTICORE_CONFIGURATION_COM_INT_EN_COM_INT_EN_WIDTH (8U) 135 #define MULTICORE_CONFIGURATION_COM_INT_EN_COM_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << MULTICORE_CONFIGURATION_COM_INT_EN_COM_INT_EN_SHIFT)) & MULTICORE_CONFIGURATION_COM_INT_EN_COM_INT_EN_MASK) 136 /*! @} */ 137 138 /*! @name START_ADDR0 - IDM Snoop Start Address 0 */ 139 /*! @{ */ 140 141 #define MULTICORE_CONFIGURATION_START_ADDR0_START_ADD_MASK (0x1FFFFFU) 142 #define MULTICORE_CONFIGURATION_START_ADDR0_START_ADD_SHIFT (0U) 143 #define MULTICORE_CONFIGURATION_START_ADDR0_START_ADD_WIDTH (21U) 144 #define MULTICORE_CONFIGURATION_START_ADDR0_START_ADD(x) (((uint32_t)(((uint32_t)(x)) << MULTICORE_CONFIGURATION_START_ADDR0_START_ADD_SHIFT)) & MULTICORE_CONFIGURATION_START_ADDR0_START_ADD_MASK) 145 /*! @} */ 146 147 /*! @name TOP_ADDR0 - IDM Snoop End Address 0 */ 148 /*! @{ */ 149 150 #define MULTICORE_CONFIGURATION_TOP_ADDR0_TOP_ADD_MASK (0x1FFFFFU) 151 #define MULTICORE_CONFIGURATION_TOP_ADDR0_TOP_ADD_SHIFT (0U) 152 #define MULTICORE_CONFIGURATION_TOP_ADDR0_TOP_ADD_WIDTH (21U) 153 #define MULTICORE_CONFIGURATION_TOP_ADDR0_TOP_ADD(x) (((uint32_t)(((uint32_t)(x)) << MULTICORE_CONFIGURATION_TOP_ADDR0_TOP_ADD_SHIFT)) & MULTICORE_CONFIGURATION_TOP_ADDR0_TOP_ADD_MASK) 154 /*! @} */ 155 156 /*! @name SNOOP_CSR0 - IDM Snoop Control 0 */ 157 /*! @{ */ 158 159 #define MULTICORE_CONFIGURATION_SNOOP_CSR0_SNOOP_RD_WR_MASK (0x3U) 160 #define MULTICORE_CONFIGURATION_SNOOP_CSR0_SNOOP_RD_WR_SHIFT (0U) 161 #define MULTICORE_CONFIGURATION_SNOOP_CSR0_SNOOP_RD_WR_WIDTH (2U) 162 #define MULTICORE_CONFIGURATION_SNOOP_CSR0_SNOOP_RD_WR(x) (((uint32_t)(((uint32_t)(x)) << MULTICORE_CONFIGURATION_SNOOP_CSR0_SNOOP_RD_WR_SHIFT)) & MULTICORE_CONFIGURATION_SNOOP_CSR0_SNOOP_RD_WR_MASK) 163 164 #define MULTICORE_CONFIGURATION_SNOOP_CSR0_SNOOP_EDAP_STS_MASK (0x4U) 165 #define MULTICORE_CONFIGURATION_SNOOP_CSR0_SNOOP_EDAP_STS_SHIFT (2U) 166 #define MULTICORE_CONFIGURATION_SNOOP_CSR0_SNOOP_EDAP_STS_WIDTH (1U) 167 #define MULTICORE_CONFIGURATION_SNOOP_CSR0_SNOOP_EDAP_STS(x) (((uint32_t)(((uint32_t)(x)) << MULTICORE_CONFIGURATION_SNOOP_CSR0_SNOOP_EDAP_STS_SHIFT)) & MULTICORE_CONFIGURATION_SNOOP_CSR0_SNOOP_EDAP_STS_MASK) 168 169 #define MULTICORE_CONFIGURATION_SNOOP_CSR0_SNOOP_EDAP_INT_EN_MASK (0x8U) 170 #define MULTICORE_CONFIGURATION_SNOOP_CSR0_SNOOP_EDAP_INT_EN_SHIFT (3U) 171 #define MULTICORE_CONFIGURATION_SNOOP_CSR0_SNOOP_EDAP_INT_EN_WIDTH (1U) 172 #define MULTICORE_CONFIGURATION_SNOOP_CSR0_SNOOP_EDAP_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << MULTICORE_CONFIGURATION_SNOOP_CSR0_SNOOP_EDAP_INT_EN_SHIFT)) & MULTICORE_CONFIGURATION_SNOOP_CSR0_SNOOP_EDAP_INT_EN_MASK) 173 /*! @} */ 174 175 /*! @name START_ADDR1 - IDM Snoop Start Address 1 */ 176 /*! @{ */ 177 178 #define MULTICORE_CONFIGURATION_START_ADDR1_START_ADD_MASK (0x1FFFFFU) 179 #define MULTICORE_CONFIGURATION_START_ADDR1_START_ADD_SHIFT (0U) 180 #define MULTICORE_CONFIGURATION_START_ADDR1_START_ADD_WIDTH (21U) 181 #define MULTICORE_CONFIGURATION_START_ADDR1_START_ADD(x) (((uint32_t)(((uint32_t)(x)) << MULTICORE_CONFIGURATION_START_ADDR1_START_ADD_SHIFT)) & MULTICORE_CONFIGURATION_START_ADDR1_START_ADD_MASK) 182 /*! @} */ 183 184 /*! @name TOP_ADDR1 - IDM Snoop End Address 1 */ 185 /*! @{ */ 186 187 #define MULTICORE_CONFIGURATION_TOP_ADDR1_TOP_ADD_MASK (0x1FFFFFU) 188 #define MULTICORE_CONFIGURATION_TOP_ADDR1_TOP_ADD_SHIFT (0U) 189 #define MULTICORE_CONFIGURATION_TOP_ADDR1_TOP_ADD_WIDTH (21U) 190 #define MULTICORE_CONFIGURATION_TOP_ADDR1_TOP_ADD(x) (((uint32_t)(((uint32_t)(x)) << MULTICORE_CONFIGURATION_TOP_ADDR1_TOP_ADD_SHIFT)) & MULTICORE_CONFIGURATION_TOP_ADDR1_TOP_ADD_MASK) 191 /*! @} */ 192 193 /*! @name SNOOP_CSR1 - IDM Snoop Control 1 */ 194 /*! @{ */ 195 196 #define MULTICORE_CONFIGURATION_SNOOP_CSR1_SNOOP_RD_WR_MASK (0x3U) 197 #define MULTICORE_CONFIGURATION_SNOOP_CSR1_SNOOP_RD_WR_SHIFT (0U) 198 #define MULTICORE_CONFIGURATION_SNOOP_CSR1_SNOOP_RD_WR_WIDTH (2U) 199 #define MULTICORE_CONFIGURATION_SNOOP_CSR1_SNOOP_RD_WR(x) (((uint32_t)(((uint32_t)(x)) << MULTICORE_CONFIGURATION_SNOOP_CSR1_SNOOP_RD_WR_SHIFT)) & MULTICORE_CONFIGURATION_SNOOP_CSR1_SNOOP_RD_WR_MASK) 200 201 #define MULTICORE_CONFIGURATION_SNOOP_CSR1_SNOOP_EDAP_STS_MASK (0x4U) 202 #define MULTICORE_CONFIGURATION_SNOOP_CSR1_SNOOP_EDAP_STS_SHIFT (2U) 203 #define MULTICORE_CONFIGURATION_SNOOP_CSR1_SNOOP_EDAP_STS_WIDTH (1U) 204 #define MULTICORE_CONFIGURATION_SNOOP_CSR1_SNOOP_EDAP_STS(x) (((uint32_t)(((uint32_t)(x)) << MULTICORE_CONFIGURATION_SNOOP_CSR1_SNOOP_EDAP_STS_SHIFT)) & MULTICORE_CONFIGURATION_SNOOP_CSR1_SNOOP_EDAP_STS_MASK) 205 206 #define MULTICORE_CONFIGURATION_SNOOP_CSR1_SNOOP_EDAP_INT_EN_MASK (0x8U) 207 #define MULTICORE_CONFIGURATION_SNOOP_CSR1_SNOOP_EDAP_INT_EN_SHIFT (3U) 208 #define MULTICORE_CONFIGURATION_SNOOP_CSR1_SNOOP_EDAP_INT_EN_WIDTH (1U) 209 #define MULTICORE_CONFIGURATION_SNOOP_CSR1_SNOOP_EDAP_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << MULTICORE_CONFIGURATION_SNOOP_CSR1_SNOOP_EDAP_INT_EN_SHIFT)) & MULTICORE_CONFIGURATION_SNOOP_CSR1_SNOOP_EDAP_INT_EN_MASK) 210 /*! @} */ 211 212 /*! 213 * @} 214 */ /* end of group MULTICORE_CONFIGURATION_Register_Masks */ 215 216 /*! 217 * @} 218 */ /* end of group MULTICORE_CONFIGURATION_Peripheral_Access_Layer */ 219 220 #endif /* #if !defined(S32Z2_MULTICORE_CONFIGURATION_H_) */ 221
