1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2024 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32Z2_SMU_XRDC.h 10 * @version 2.3 11 * @date 2024-05-03 12 * @brief Peripheral Access Layer for S32Z2_SMU_XRDC 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32Z2_SMU_XRDC_H_) /* Check if memory map has not been already included */ 58 #define S32Z2_SMU_XRDC_H_ 59 60 #include "S32Z2_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- SMU_XRDC Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup SMU_XRDC_Peripheral_Access_Layer SMU_XRDC Peripheral Access Layer 68 * @{ 69 */ 70 71 /** SMU_XRDC - Size of Registers Arrays */ 72 #define SMU_XRDC_MDAC_COUNT 2u 73 #define SMU_XRDC_MRC_COUNT 4u 74 #define SMU_XRDC_DERRLOC_COUNT 16u 75 #define SMU_XRDC_DERRW0_COUNT 18u 76 #define SMU_XRDC_PDAC_SLOT_PDACN_COUNT 113u 77 #define SMU_XRDC_PDAC_SLOT_COUNT 2u 78 #define SMU_XRDC_MRCN_COUNT 4u 79 #define SMU_XRDC_MRCN_MRGDN_COUNT 16u 80 81 /** SMU_XRDC - Register Layout Typedef */ 82 typedef struct { 83 __IO uint32_t CR; /**< Control, offset: 0x0 */ 84 uint8_t RESERVED_0[236]; 85 __I uint32_t HWCFG0; /**< Hardware Configuration 0, offset: 0xF0 */ 86 __I uint32_t HWCFG1; /**< Hardware Configuration 1, offset: 0xF4 */ 87 uint8_t RESERVED_1[8]; 88 __I uint8_t MDACFG[SMU_XRDC_MDAC_COUNT]; /**< Master Domain Assignment Configuration, array offset: 0x100, array step: 0x1 */ 89 uint8_t RESERVED_2[62]; 90 __I uint8_t MRCFG[SMU_XRDC_MRC_COUNT]; /**< Memory Region Configuration, array offset: 0x140, array step: 0x1 */ 91 uint8_t RESERVED_3[188]; 92 __I uint32_t DERRLOC[SMU_XRDC_DERRLOC_COUNT]; /**< Domain Error Location, array offset: 0x200, array step: 0x4 */ 93 uint8_t RESERVED_4[448]; 94 struct SMU_XRDC_DERRW0 { /* offset: 0x400, array step: 0x10 */ 95 __I uint32_t DERR_W0; /**< Domain Error Word 0, array offset: 0x400, array step: 0x10, valid indices: [0-3, 16-17] */ 96 __I uint32_t DERR_W1; /**< Domain Error Word 1, array offset: 0x404, array step: 0x10, valid indices: [0-3, 16-17] */ 97 uint8_t RESERVED_0[4]; 98 __O uint32_t DERR_W3; /**< Domain Error Word 3, array offset: 0x40C, array step: 0x10, valid indices: [0-3, 16-17] */ 99 } DERRW0[SMU_XRDC_DERRW0_COUNT]; 100 uint8_t RESERVED_5[736]; 101 __IO uint32_t MDA_W0_0_DFMT1; /**< Master Domain Assignment, offset: 0x800 */ 102 __IO uint32_t MDA_W1_0_DFMT1; /**< Master Domain Assignment, offset: 0x804 */ 103 __IO uint32_t MDA_W2_0_DFMT1; /**< Master Domain Assignment, offset: 0x808 */ 104 __IO uint32_t MDA_W3_0_DFMT1; /**< Master Domain Assignment, offset: 0x80C */ 105 __IO uint32_t MDA_W4_0_DFMT1; /**< Master Domain Assignment, offset: 0x810 */ 106 __IO uint32_t MDA_W5_0_DFMT1; /**< Master Domain Assignment, offset: 0x814 */ 107 __IO uint32_t MDA_W6_0_DFMT1; /**< Master Domain Assignment, offset: 0x818 */ 108 __IO uint32_t MDA_W7_0_DFMT1; /**< Master Domain Assignment, offset: 0x81C */ 109 __IO uint32_t MDA_W0_1_DFMT1; /**< Master Domain Assignment, offset: 0x820 */ 110 uint8_t RESERVED_6[2012]; 111 struct SMU_XRDC_PDAC_SLOT { /* offset: 0x1000, array step: 0x400 */ 112 struct SMU_XRDC_PDAC_SLOT_PDACN { /* offset: 0x1000, array step: index*0x400, index2*0x8 */ 113 __IO uint32_t PDAC_W0; /**< Peripheral Domain Access Control Word 0, array offset: 0x1000, array step: index*0x400, index2*0x8, valid indices: [0][0, 4-5, 8-9, 16-21, 24-25], [1][4, 12, 16, 24-27, 36, 64, 68, 72, 76, 80, 84, 88, 92, 96, 100, 104, 108, 112] */ 114 __IO uint32_t PDAC_W1; /**< Peripheral Domain Access Control Word 1, array offset: 0x1004, array step: index*0x400, index2*0x8, valid indices: [0][0, 4-5, 8-9, 16-21, 24-25], [1][4, 12, 16, 24-27, 36, 64, 68, 72, 76, 80, 84, 88, 92, 96, 100, 104, 108, 112] */ 115 } PDACN[SMU_XRDC_PDAC_SLOT_PDACN_COUNT]; 116 uint8_t RESERVED_0[120]; 117 } PDAC_SLOT[SMU_XRDC_PDAC_SLOT_COUNT]; 118 uint8_t RESERVED_7[2048]; 119 struct SMU_XRDC_MRGDN { /* offset: 0x2000, array step: index*0x200, index2*0x20 */ 120 __IO uint32_t XRDC_MRGD_W0; /**< Memory Region Descriptor Word 0, array offset: 0x2000, array step: index*0x200, index2*0x20 */ 121 __IO uint32_t XRDC_MRGD_W1; /**< Memory Region Descriptor Word 1, array offset: 0x2004, array step: index*0x200, index2*0x20 */ 122 __IO uint32_t XRDC_MRGD_W2; /**< Memory Region Descriptor Word 2, array offset: 0x2008, array step: index*0x200, index2*0x20 */ 123 __IO uint32_t XRDC_MRGD_W3; /**< Memory Region Descriptor Word 3, array offset: 0x200C, array step: index*0x200, index2*0x20 */ 124 uint8_t RESERVED_0[16]; 125 } MRGDN[SMU_XRDC_MRCN_COUNT][SMU_XRDC_MRCN_MRGDN_COUNT]; 126 } SMU_XRDC_Type, *SMU_XRDC_MemMapPtr; 127 128 /** Number of instances of the SMU_XRDC module. */ 129 #define SMU_XRDC_INSTANCE_COUNT (1u) 130 131 /* SMU_XRDC - Peripheral instance base addresses */ 132 /** Peripheral SMU__XRDC base address */ 133 #define IP_SMU__XRDC_BASE (0x45000000u) 134 /** Peripheral SMU__XRDC base pointer */ 135 #define IP_SMU__XRDC ((SMU_XRDC_Type *)IP_SMU__XRDC_BASE) 136 /** Array initializer of SMU_XRDC peripheral base addresses */ 137 #define IP_SMU_XRDC_BASE_ADDRS { IP_SMU__XRDC_BASE } 138 /** Array initializer of SMU_XRDC peripheral base pointers */ 139 #define IP_SMU_XRDC_BASE_PTRS { IP_SMU__XRDC } 140 141 /* ---------------------------------------------------------------------------- 142 -- SMU_XRDC Register Masks 143 ---------------------------------------------------------------------------- */ 144 145 /*! 146 * @addtogroup SMU_XRDC_Register_Masks SMU_XRDC Register Masks 147 * @{ 148 */ 149 150 /*! @name CR - Control */ 151 /*! @{ */ 152 153 #define SMU_XRDC_CR_GVLD_MASK (0x1U) 154 #define SMU_XRDC_CR_GVLD_SHIFT (0U) 155 #define SMU_XRDC_CR_GVLD_WIDTH (1U) 156 #define SMU_XRDC_CR_GVLD(x) (((uint32_t)(((uint32_t)(x)) << SMU_XRDC_CR_GVLD_SHIFT)) & SMU_XRDC_CR_GVLD_MASK) 157 158 #define SMU_XRDC_CR_HRL_MASK (0x1EU) 159 #define SMU_XRDC_CR_HRL_SHIFT (1U) 160 #define SMU_XRDC_CR_HRL_WIDTH (4U) 161 #define SMU_XRDC_CR_HRL(x) (((uint32_t)(((uint32_t)(x)) << SMU_XRDC_CR_HRL_SHIFT)) & SMU_XRDC_CR_HRL_MASK) 162 163 #define SMU_XRDC_CR_MRF_MASK (0x80U) 164 #define SMU_XRDC_CR_MRF_SHIFT (7U) 165 #define SMU_XRDC_CR_MRF_WIDTH (1U) 166 #define SMU_XRDC_CR_MRF(x) (((uint32_t)(((uint32_t)(x)) << SMU_XRDC_CR_MRF_SHIFT)) & SMU_XRDC_CR_MRF_MASK) 167 168 #define SMU_XRDC_CR_VAW_MASK (0x100U) 169 #define SMU_XRDC_CR_VAW_SHIFT (8U) 170 #define SMU_XRDC_CR_VAW_WIDTH (1U) 171 #define SMU_XRDC_CR_VAW(x) (((uint32_t)(((uint32_t)(x)) << SMU_XRDC_CR_VAW_SHIFT)) & SMU_XRDC_CR_VAW_MASK) 172 173 #define SMU_XRDC_CR_LK1_MASK (0x40000000U) 174 #define SMU_XRDC_CR_LK1_SHIFT (30U) 175 #define SMU_XRDC_CR_LK1_WIDTH (1U) 176 #define SMU_XRDC_CR_LK1(x) (((uint32_t)(((uint32_t)(x)) << SMU_XRDC_CR_LK1_SHIFT)) & SMU_XRDC_CR_LK1_MASK) 177 /*! @} */ 178 179 /*! @name HWCFG0 - Hardware Configuration 0 */ 180 /*! @{ */ 181 182 #define SMU_XRDC_HWCFG0_NDID_MASK (0xFFU) 183 #define SMU_XRDC_HWCFG0_NDID_SHIFT (0U) 184 #define SMU_XRDC_HWCFG0_NDID_WIDTH (8U) 185 #define SMU_XRDC_HWCFG0_NDID(x) (((uint32_t)(((uint32_t)(x)) << SMU_XRDC_HWCFG0_NDID_SHIFT)) & SMU_XRDC_HWCFG0_NDID_MASK) 186 187 #define SMU_XRDC_HWCFG0_NMSTR_MASK (0xFF00U) 188 #define SMU_XRDC_HWCFG0_NMSTR_SHIFT (8U) 189 #define SMU_XRDC_HWCFG0_NMSTR_WIDTH (8U) 190 #define SMU_XRDC_HWCFG0_NMSTR(x) (((uint32_t)(((uint32_t)(x)) << SMU_XRDC_HWCFG0_NMSTR_SHIFT)) & SMU_XRDC_HWCFG0_NMSTR_MASK) 191 192 #define SMU_XRDC_HWCFG0_NMRC_MASK (0xFF0000U) 193 #define SMU_XRDC_HWCFG0_NMRC_SHIFT (16U) 194 #define SMU_XRDC_HWCFG0_NMRC_WIDTH (8U) 195 #define SMU_XRDC_HWCFG0_NMRC(x) (((uint32_t)(((uint32_t)(x)) << SMU_XRDC_HWCFG0_NMRC_SHIFT)) & SMU_XRDC_HWCFG0_NMRC_MASK) 196 197 #define SMU_XRDC_HWCFG0_NPAC_MASK (0xF000000U) 198 #define SMU_XRDC_HWCFG0_NPAC_SHIFT (24U) 199 #define SMU_XRDC_HWCFG0_NPAC_WIDTH (4U) 200 #define SMU_XRDC_HWCFG0_NPAC(x) (((uint32_t)(((uint32_t)(x)) << SMU_XRDC_HWCFG0_NPAC_SHIFT)) & SMU_XRDC_HWCFG0_NPAC_MASK) 201 202 #define SMU_XRDC_HWCFG0_MID_MASK (0xF0000000U) 203 #define SMU_XRDC_HWCFG0_MID_SHIFT (28U) 204 #define SMU_XRDC_HWCFG0_MID_WIDTH (4U) 205 #define SMU_XRDC_HWCFG0_MID(x) (((uint32_t)(((uint32_t)(x)) << SMU_XRDC_HWCFG0_MID_SHIFT)) & SMU_XRDC_HWCFG0_MID_MASK) 206 /*! @} */ 207 208 /*! @name HWCFG1 - Hardware Configuration 1 */ 209 /*! @{ */ 210 211 #define SMU_XRDC_HWCFG1_DID_MASK (0xFU) 212 #define SMU_XRDC_HWCFG1_DID_SHIFT (0U) 213 #define SMU_XRDC_HWCFG1_DID_WIDTH (4U) 214 #define SMU_XRDC_HWCFG1_DID(x) (((uint32_t)(((uint32_t)(x)) << SMU_XRDC_HWCFG1_DID_SHIFT)) & SMU_XRDC_HWCFG1_DID_MASK) 215 /*! @} */ 216 217 /*! @name MDACFG - Master Domain Assignment Configuration */ 218 /*! @{ */ 219 220 #define SMU_XRDC_MDACFG_NMDAR_MASK (0xFU) 221 #define SMU_XRDC_MDACFG_NMDAR_SHIFT (0U) 222 #define SMU_XRDC_MDACFG_NMDAR_WIDTH (4U) 223 #define SMU_XRDC_MDACFG_NMDAR(x) (((uint8_t)(((uint8_t)(x)) << SMU_XRDC_MDACFG_NMDAR_SHIFT)) & SMU_XRDC_MDACFG_NMDAR_MASK) 224 225 #define SMU_XRDC_MDACFG_NCM_MASK (0x80U) 226 #define SMU_XRDC_MDACFG_NCM_SHIFT (7U) 227 #define SMU_XRDC_MDACFG_NCM_WIDTH (1U) 228 #define SMU_XRDC_MDACFG_NCM(x) (((uint8_t)(((uint8_t)(x)) << SMU_XRDC_MDACFG_NCM_SHIFT)) & SMU_XRDC_MDACFG_NCM_MASK) 229 /*! @} */ 230 231 /*! @name MRCFG - Memory Region Configuration */ 232 /*! @{ */ 233 234 #define SMU_XRDC_MRCFG_NMRGD_MASK (0x1FU) 235 #define SMU_XRDC_MRCFG_NMRGD_SHIFT (0U) 236 #define SMU_XRDC_MRCFG_NMRGD_WIDTH (5U) 237 #define SMU_XRDC_MRCFG_NMRGD(x) (((uint8_t)(((uint8_t)(x)) << SMU_XRDC_MRCFG_NMRGD_SHIFT)) & SMU_XRDC_MRCFG_NMRGD_MASK) 238 /*! @} */ 239 240 /*! @name DERRLOC - Domain Error Location */ 241 /*! @{ */ 242 243 #define SMU_XRDC_DERRLOC_MRCINST_MASK (0xFFFFU) 244 #define SMU_XRDC_DERRLOC_MRCINST_SHIFT (0U) 245 #define SMU_XRDC_DERRLOC_MRCINST_WIDTH (16U) 246 #define SMU_XRDC_DERRLOC_MRCINST(x) (((uint32_t)(((uint32_t)(x)) << SMU_XRDC_DERRLOC_MRCINST_SHIFT)) & SMU_XRDC_DERRLOC_MRCINST_MASK) 247 248 #define SMU_XRDC_DERRLOC_PACINST_MASK (0xF0000U) 249 #define SMU_XRDC_DERRLOC_PACINST_SHIFT (16U) 250 #define SMU_XRDC_DERRLOC_PACINST_WIDTH (4U) 251 #define SMU_XRDC_DERRLOC_PACINST(x) (((uint32_t)(((uint32_t)(x)) << SMU_XRDC_DERRLOC_PACINST_SHIFT)) & SMU_XRDC_DERRLOC_PACINST_MASK) 252 /*! @} */ 253 254 /*! @name DERR_W0 - Domain Error Word 0 */ 255 /*! @{ */ 256 257 #define SMU_XRDC_DERR_W0_EADDR_MASK (0xFFFFFFFFU) 258 #define SMU_XRDC_DERR_W0_EADDR_SHIFT (0U) 259 #define SMU_XRDC_DERR_W0_EADDR_WIDTH (32U) 260 #define SMU_XRDC_DERR_W0_EADDR(x) (((uint32_t)(((uint32_t)(x)) << SMU_XRDC_DERR_W0_EADDR_SHIFT)) & SMU_XRDC_DERR_W0_EADDR_MASK) 261 /*! @} */ 262 263 /*! @name DERR_W1 - Domain Error Word 1 */ 264 /*! @{ */ 265 266 #define SMU_XRDC_DERR_W1_EDID_MASK (0xFU) 267 #define SMU_XRDC_DERR_W1_EDID_SHIFT (0U) 268 #define SMU_XRDC_DERR_W1_EDID_WIDTH (4U) 269 #define SMU_XRDC_DERR_W1_EDID(x) (((uint32_t)(((uint32_t)(x)) << SMU_XRDC_DERR_W1_EDID_SHIFT)) & SMU_XRDC_DERR_W1_EDID_MASK) 270 271 #define SMU_XRDC_DERR_W1_EATR_MASK (0x700U) 272 #define SMU_XRDC_DERR_W1_EATR_SHIFT (8U) 273 #define SMU_XRDC_DERR_W1_EATR_WIDTH (3U) 274 #define SMU_XRDC_DERR_W1_EATR(x) (((uint32_t)(((uint32_t)(x)) << SMU_XRDC_DERR_W1_EATR_SHIFT)) & SMU_XRDC_DERR_W1_EATR_MASK) 275 276 #define SMU_XRDC_DERR_W1_ERW_MASK (0x800U) 277 #define SMU_XRDC_DERR_W1_ERW_SHIFT (11U) 278 #define SMU_XRDC_DERR_W1_ERW_WIDTH (1U) 279 #define SMU_XRDC_DERR_W1_ERW(x) (((uint32_t)(((uint32_t)(x)) << SMU_XRDC_DERR_W1_ERW_SHIFT)) & SMU_XRDC_DERR_W1_ERW_MASK) 280 281 #define SMU_XRDC_DERR_W1_EPORT_MASK (0x7000000U) 282 #define SMU_XRDC_DERR_W1_EPORT_SHIFT (24U) 283 #define SMU_XRDC_DERR_W1_EPORT_WIDTH (3U) 284 #define SMU_XRDC_DERR_W1_EPORT(x) (((uint32_t)(((uint32_t)(x)) << SMU_XRDC_DERR_W1_EPORT_SHIFT)) & SMU_XRDC_DERR_W1_EPORT_MASK) 285 286 #define SMU_XRDC_DERR_W1_EST_MASK (0xC0000000U) 287 #define SMU_XRDC_DERR_W1_EST_SHIFT (30U) 288 #define SMU_XRDC_DERR_W1_EST_WIDTH (2U) 289 #define SMU_XRDC_DERR_W1_EST(x) (((uint32_t)(((uint32_t)(x)) << SMU_XRDC_DERR_W1_EST_SHIFT)) & SMU_XRDC_DERR_W1_EST_MASK) 290 /*! @} */ 291 292 /*! @name DERR_W3 - Domain Error Word 3 */ 293 /*! @{ */ 294 295 #define SMU_XRDC_DERR_W3_RECR_MASK (0xC0000000U) 296 #define SMU_XRDC_DERR_W3_RECR_SHIFT (30U) 297 #define SMU_XRDC_DERR_W3_RECR_WIDTH (2U) 298 #define SMU_XRDC_DERR_W3_RECR(x) (((uint32_t)(((uint32_t)(x)) << SMU_XRDC_DERR_W3_RECR_SHIFT)) & SMU_XRDC_DERR_W3_RECR_MASK) 299 /*! @} */ 300 301 /*! @name MDA_W0_0_DFMT1 - Master Domain Assignment */ 302 /*! @{ */ 303 304 #define SMU_XRDC_MDA_W0_0_DFMT1_DID_MASK (0xFU) 305 #define SMU_XRDC_MDA_W0_0_DFMT1_DID_SHIFT (0U) 306 #define SMU_XRDC_MDA_W0_0_DFMT1_DID_WIDTH (4U) 307 #define SMU_XRDC_MDA_W0_0_DFMT1_DID(x) (((uint32_t)(((uint32_t)(x)) << SMU_XRDC_MDA_W0_0_DFMT1_DID_SHIFT)) & SMU_XRDC_MDA_W0_0_DFMT1_DID_MASK) 308 309 #define SMU_XRDC_MDA_W0_0_DFMT1_PA_MASK (0x30U) 310 #define SMU_XRDC_MDA_W0_0_DFMT1_PA_SHIFT (4U) 311 #define SMU_XRDC_MDA_W0_0_DFMT1_PA_WIDTH (2U) 312 #define SMU_XRDC_MDA_W0_0_DFMT1_PA(x) (((uint32_t)(((uint32_t)(x)) << SMU_XRDC_MDA_W0_0_DFMT1_PA_SHIFT)) & SMU_XRDC_MDA_W0_0_DFMT1_PA_MASK) 313 314 #define SMU_XRDC_MDA_W0_0_DFMT1_SA_MASK (0xC0U) 315 #define SMU_XRDC_MDA_W0_0_DFMT1_SA_SHIFT (6U) 316 #define SMU_XRDC_MDA_W0_0_DFMT1_SA_WIDTH (2U) 317 #define SMU_XRDC_MDA_W0_0_DFMT1_SA(x) (((uint32_t)(((uint32_t)(x)) << SMU_XRDC_MDA_W0_0_DFMT1_SA_SHIFT)) & SMU_XRDC_MDA_W0_0_DFMT1_SA_MASK) 318 319 #define SMU_XRDC_MDA_W0_0_DFMT1_DIDB_MASK (0x100U) 320 #define SMU_XRDC_MDA_W0_0_DFMT1_DIDB_SHIFT (8U) 321 #define SMU_XRDC_MDA_W0_0_DFMT1_DIDB_WIDTH (1U) 322 #define SMU_XRDC_MDA_W0_0_DFMT1_DIDB(x) (((uint32_t)(((uint32_t)(x)) << SMU_XRDC_MDA_W0_0_DFMT1_DIDB_SHIFT)) & SMU_XRDC_MDA_W0_0_DFMT1_DIDB_MASK) 323 324 #define SMU_XRDC_MDA_W0_0_DFMT1_LPID_MASK (0xF000000U) 325 #define SMU_XRDC_MDA_W0_0_DFMT1_LPID_SHIFT (24U) 326 #define SMU_XRDC_MDA_W0_0_DFMT1_LPID_WIDTH (4U) 327 #define SMU_XRDC_MDA_W0_0_DFMT1_LPID(x) (((uint32_t)(((uint32_t)(x)) << SMU_XRDC_MDA_W0_0_DFMT1_LPID_SHIFT)) & SMU_XRDC_MDA_W0_0_DFMT1_LPID_MASK) 328 329 #define SMU_XRDC_MDA_W0_0_DFMT1_LPE_MASK (0x10000000U) 330 #define SMU_XRDC_MDA_W0_0_DFMT1_LPE_SHIFT (28U) 331 #define SMU_XRDC_MDA_W0_0_DFMT1_LPE_WIDTH (1U) 332 #define SMU_XRDC_MDA_W0_0_DFMT1_LPE(x) (((uint32_t)(((uint32_t)(x)) << SMU_XRDC_MDA_W0_0_DFMT1_LPE_SHIFT)) & SMU_XRDC_MDA_W0_0_DFMT1_LPE_MASK) 333 334 #define SMU_XRDC_MDA_W0_0_DFMT1_DFMT_MASK (0x20000000U) 335 #define SMU_XRDC_MDA_W0_0_DFMT1_DFMT_SHIFT (29U) 336 #define SMU_XRDC_MDA_W0_0_DFMT1_DFMT_WIDTH (1U) 337 #define SMU_XRDC_MDA_W0_0_DFMT1_DFMT(x) (((uint32_t)(((uint32_t)(x)) << SMU_XRDC_MDA_W0_0_DFMT1_DFMT_SHIFT)) & SMU_XRDC_MDA_W0_0_DFMT1_DFMT_MASK) 338 339 #define SMU_XRDC_MDA_W0_0_DFMT1_LK1_MASK (0x40000000U) 340 #define SMU_XRDC_MDA_W0_0_DFMT1_LK1_SHIFT (30U) 341 #define SMU_XRDC_MDA_W0_0_DFMT1_LK1_WIDTH (1U) 342 #define SMU_XRDC_MDA_W0_0_DFMT1_LK1(x) (((uint32_t)(((uint32_t)(x)) << SMU_XRDC_MDA_W0_0_DFMT1_LK1_SHIFT)) & SMU_XRDC_MDA_W0_0_DFMT1_LK1_MASK) 343 344 #define SMU_XRDC_MDA_W0_0_DFMT1_VLD_MASK (0x80000000U) 345 #define SMU_XRDC_MDA_W0_0_DFMT1_VLD_SHIFT (31U) 346 #define SMU_XRDC_MDA_W0_0_DFMT1_VLD_WIDTH (1U) 347 #define SMU_XRDC_MDA_W0_0_DFMT1_VLD(x) (((uint32_t)(((uint32_t)(x)) << SMU_XRDC_MDA_W0_0_DFMT1_VLD_SHIFT)) & SMU_XRDC_MDA_W0_0_DFMT1_VLD_MASK) 348 /*! @} */ 349 350 /*! @name MDA_W1_0_DFMT1 - Master Domain Assignment */ 351 /*! @{ */ 352 353 #define SMU_XRDC_MDA_W1_0_DFMT1_DID_MASK (0xFU) 354 #define SMU_XRDC_MDA_W1_0_DFMT1_DID_SHIFT (0U) 355 #define SMU_XRDC_MDA_W1_0_DFMT1_DID_WIDTH (4U) 356 #define SMU_XRDC_MDA_W1_0_DFMT1_DID(x) (((uint32_t)(((uint32_t)(x)) << SMU_XRDC_MDA_W1_0_DFMT1_DID_SHIFT)) & SMU_XRDC_MDA_W1_0_DFMT1_DID_MASK) 357 358 #define SMU_XRDC_MDA_W1_0_DFMT1_PA_MASK (0x30U) 359 #define SMU_XRDC_MDA_W1_0_DFMT1_PA_SHIFT (4U) 360 #define SMU_XRDC_MDA_W1_0_DFMT1_PA_WIDTH (2U) 361 #define SMU_XRDC_MDA_W1_0_DFMT1_PA(x) (((uint32_t)(((uint32_t)(x)) << SMU_XRDC_MDA_W1_0_DFMT1_PA_SHIFT)) & SMU_XRDC_MDA_W1_0_DFMT1_PA_MASK) 362 363 #define SMU_XRDC_MDA_W1_0_DFMT1_SA_MASK (0xC0U) 364 #define SMU_XRDC_MDA_W1_0_DFMT1_SA_SHIFT (6U) 365 #define SMU_XRDC_MDA_W1_0_DFMT1_SA_WIDTH (2U) 366 #define SMU_XRDC_MDA_W1_0_DFMT1_SA(x) (((uint32_t)(((uint32_t)(x)) << SMU_XRDC_MDA_W1_0_DFMT1_SA_SHIFT)) & SMU_XRDC_MDA_W1_0_DFMT1_SA_MASK) 367 368 #define SMU_XRDC_MDA_W1_0_DFMT1_DIDB_MASK (0x100U) 369 #define SMU_XRDC_MDA_W1_0_DFMT1_DIDB_SHIFT (8U) 370 #define SMU_XRDC_MDA_W1_0_DFMT1_DIDB_WIDTH (1U) 371 #define SMU_XRDC_MDA_W1_0_DFMT1_DIDB(x) (((uint32_t)(((uint32_t)(x)) << SMU_XRDC_MDA_W1_0_DFMT1_DIDB_SHIFT)) & SMU_XRDC_MDA_W1_0_DFMT1_DIDB_MASK) 372 373 #define SMU_XRDC_MDA_W1_0_DFMT1_LPID_MASK (0xF000000U) 374 #define SMU_XRDC_MDA_W1_0_DFMT1_LPID_SHIFT (24U) 375 #define SMU_XRDC_MDA_W1_0_DFMT1_LPID_WIDTH (4U) 376 #define SMU_XRDC_MDA_W1_0_DFMT1_LPID(x) (((uint32_t)(((uint32_t)(x)) << SMU_XRDC_MDA_W1_0_DFMT1_LPID_SHIFT)) & SMU_XRDC_MDA_W1_0_DFMT1_LPID_MASK) 377 378 #define SMU_XRDC_MDA_W1_0_DFMT1_LPE_MASK (0x10000000U) 379 #define SMU_XRDC_MDA_W1_0_DFMT1_LPE_SHIFT (28U) 380 #define SMU_XRDC_MDA_W1_0_DFMT1_LPE_WIDTH (1U) 381 #define SMU_XRDC_MDA_W1_0_DFMT1_LPE(x) (((uint32_t)(((uint32_t)(x)) << SMU_XRDC_MDA_W1_0_DFMT1_LPE_SHIFT)) & SMU_XRDC_MDA_W1_0_DFMT1_LPE_MASK) 382 383 #define SMU_XRDC_MDA_W1_0_DFMT1_DFMT_MASK (0x20000000U) 384 #define SMU_XRDC_MDA_W1_0_DFMT1_DFMT_SHIFT (29U) 385 #define SMU_XRDC_MDA_W1_0_DFMT1_DFMT_WIDTH (1U) 386 #define SMU_XRDC_MDA_W1_0_DFMT1_DFMT(x) (((uint32_t)(((uint32_t)(x)) << SMU_XRDC_MDA_W1_0_DFMT1_DFMT_SHIFT)) & SMU_XRDC_MDA_W1_0_DFMT1_DFMT_MASK) 387 388 #define SMU_XRDC_MDA_W1_0_DFMT1_LK1_MASK (0x40000000U) 389 #define SMU_XRDC_MDA_W1_0_DFMT1_LK1_SHIFT (30U) 390 #define SMU_XRDC_MDA_W1_0_DFMT1_LK1_WIDTH (1U) 391 #define SMU_XRDC_MDA_W1_0_DFMT1_LK1(x) (((uint32_t)(((uint32_t)(x)) << SMU_XRDC_MDA_W1_0_DFMT1_LK1_SHIFT)) & SMU_XRDC_MDA_W1_0_DFMT1_LK1_MASK) 392 393 #define SMU_XRDC_MDA_W1_0_DFMT1_VLD_MASK (0x80000000U) 394 #define SMU_XRDC_MDA_W1_0_DFMT1_VLD_SHIFT (31U) 395 #define SMU_XRDC_MDA_W1_0_DFMT1_VLD_WIDTH (1U) 396 #define SMU_XRDC_MDA_W1_0_DFMT1_VLD(x) (((uint32_t)(((uint32_t)(x)) << SMU_XRDC_MDA_W1_0_DFMT1_VLD_SHIFT)) & SMU_XRDC_MDA_W1_0_DFMT1_VLD_MASK) 397 /*! @} */ 398 399 /*! @name MDA_W2_0_DFMT1 - Master Domain Assignment */ 400 /*! @{ */ 401 402 #define SMU_XRDC_MDA_W2_0_DFMT1_DID_MASK (0xFU) 403 #define SMU_XRDC_MDA_W2_0_DFMT1_DID_SHIFT (0U) 404 #define SMU_XRDC_MDA_W2_0_DFMT1_DID_WIDTH (4U) 405 #define SMU_XRDC_MDA_W2_0_DFMT1_DID(x) (((uint32_t)(((uint32_t)(x)) << SMU_XRDC_MDA_W2_0_DFMT1_DID_SHIFT)) & SMU_XRDC_MDA_W2_0_DFMT1_DID_MASK) 406 407 #define SMU_XRDC_MDA_W2_0_DFMT1_PA_MASK (0x30U) 408 #define SMU_XRDC_MDA_W2_0_DFMT1_PA_SHIFT (4U) 409 #define SMU_XRDC_MDA_W2_0_DFMT1_PA_WIDTH (2U) 410 #define SMU_XRDC_MDA_W2_0_DFMT1_PA(x) (((uint32_t)(((uint32_t)(x)) << SMU_XRDC_MDA_W2_0_DFMT1_PA_SHIFT)) & SMU_XRDC_MDA_W2_0_DFMT1_PA_MASK) 411 412 #define SMU_XRDC_MDA_W2_0_DFMT1_SA_MASK (0xC0U) 413 #define SMU_XRDC_MDA_W2_0_DFMT1_SA_SHIFT (6U) 414 #define SMU_XRDC_MDA_W2_0_DFMT1_SA_WIDTH (2U) 415 #define SMU_XRDC_MDA_W2_0_DFMT1_SA(x) (((uint32_t)(((uint32_t)(x)) << SMU_XRDC_MDA_W2_0_DFMT1_SA_SHIFT)) & SMU_XRDC_MDA_W2_0_DFMT1_SA_MASK) 416 417 #define SMU_XRDC_MDA_W2_0_DFMT1_DIDB_MASK (0x100U) 418 #define SMU_XRDC_MDA_W2_0_DFMT1_DIDB_SHIFT (8U) 419 #define SMU_XRDC_MDA_W2_0_DFMT1_DIDB_WIDTH (1U) 420 #define SMU_XRDC_MDA_W2_0_DFMT1_DIDB(x) (((uint32_t)(((uint32_t)(x)) << SMU_XRDC_MDA_W2_0_DFMT1_DIDB_SHIFT)) & SMU_XRDC_MDA_W2_0_DFMT1_DIDB_MASK) 421 422 #define SMU_XRDC_MDA_W2_0_DFMT1_LPID_MASK (0xF000000U) 423 #define SMU_XRDC_MDA_W2_0_DFMT1_LPID_SHIFT (24U) 424 #define SMU_XRDC_MDA_W2_0_DFMT1_LPID_WIDTH (4U) 425 #define SMU_XRDC_MDA_W2_0_DFMT1_LPID(x) (((uint32_t)(((uint32_t)(x)) << SMU_XRDC_MDA_W2_0_DFMT1_LPID_SHIFT)) & SMU_XRDC_MDA_W2_0_DFMT1_LPID_MASK) 426 427 #define SMU_XRDC_MDA_W2_0_DFMT1_LPE_MASK (0x10000000U) 428 #define SMU_XRDC_MDA_W2_0_DFMT1_LPE_SHIFT (28U) 429 #define SMU_XRDC_MDA_W2_0_DFMT1_LPE_WIDTH (1U) 430 #define SMU_XRDC_MDA_W2_0_DFMT1_LPE(x) (((uint32_t)(((uint32_t)(x)) << SMU_XRDC_MDA_W2_0_DFMT1_LPE_SHIFT)) & SMU_XRDC_MDA_W2_0_DFMT1_LPE_MASK) 431 432 #define SMU_XRDC_MDA_W2_0_DFMT1_DFMT_MASK (0x20000000U) 433 #define SMU_XRDC_MDA_W2_0_DFMT1_DFMT_SHIFT (29U) 434 #define SMU_XRDC_MDA_W2_0_DFMT1_DFMT_WIDTH (1U) 435 #define SMU_XRDC_MDA_W2_0_DFMT1_DFMT(x) (((uint32_t)(((uint32_t)(x)) << SMU_XRDC_MDA_W2_0_DFMT1_DFMT_SHIFT)) & SMU_XRDC_MDA_W2_0_DFMT1_DFMT_MASK) 436 437 #define SMU_XRDC_MDA_W2_0_DFMT1_LK1_MASK (0x40000000U) 438 #define SMU_XRDC_MDA_W2_0_DFMT1_LK1_SHIFT (30U) 439 #define SMU_XRDC_MDA_W2_0_DFMT1_LK1_WIDTH (1U) 440 #define SMU_XRDC_MDA_W2_0_DFMT1_LK1(x) (((uint32_t)(((uint32_t)(x)) << SMU_XRDC_MDA_W2_0_DFMT1_LK1_SHIFT)) & SMU_XRDC_MDA_W2_0_DFMT1_LK1_MASK) 441 442 #define SMU_XRDC_MDA_W2_0_DFMT1_VLD_MASK (0x80000000U) 443 #define SMU_XRDC_MDA_W2_0_DFMT1_VLD_SHIFT (31U) 444 #define SMU_XRDC_MDA_W2_0_DFMT1_VLD_WIDTH (1U) 445 #define SMU_XRDC_MDA_W2_0_DFMT1_VLD(x) (((uint32_t)(((uint32_t)(x)) << SMU_XRDC_MDA_W2_0_DFMT1_VLD_SHIFT)) & SMU_XRDC_MDA_W2_0_DFMT1_VLD_MASK) 446 /*! @} */ 447 448 /*! @name MDA_W3_0_DFMT1 - Master Domain Assignment */ 449 /*! @{ */ 450 451 #define SMU_XRDC_MDA_W3_0_DFMT1_DID_MASK (0xFU) 452 #define SMU_XRDC_MDA_W3_0_DFMT1_DID_SHIFT (0U) 453 #define SMU_XRDC_MDA_W3_0_DFMT1_DID_WIDTH (4U) 454 #define SMU_XRDC_MDA_W3_0_DFMT1_DID(x) (((uint32_t)(((uint32_t)(x)) << SMU_XRDC_MDA_W3_0_DFMT1_DID_SHIFT)) & SMU_XRDC_MDA_W3_0_DFMT1_DID_MASK) 455 456 #define SMU_XRDC_MDA_W3_0_DFMT1_PA_MASK (0x30U) 457 #define SMU_XRDC_MDA_W3_0_DFMT1_PA_SHIFT (4U) 458 #define SMU_XRDC_MDA_W3_0_DFMT1_PA_WIDTH (2U) 459 #define SMU_XRDC_MDA_W3_0_DFMT1_PA(x) (((uint32_t)(((uint32_t)(x)) << SMU_XRDC_MDA_W3_0_DFMT1_PA_SHIFT)) & SMU_XRDC_MDA_W3_0_DFMT1_PA_MASK) 460 461 #define SMU_XRDC_MDA_W3_0_DFMT1_SA_MASK (0xC0U) 462 #define SMU_XRDC_MDA_W3_0_DFMT1_SA_SHIFT (6U) 463 #define SMU_XRDC_MDA_W3_0_DFMT1_SA_WIDTH (2U) 464 #define SMU_XRDC_MDA_W3_0_DFMT1_SA(x) (((uint32_t)(((uint32_t)(x)) << SMU_XRDC_MDA_W3_0_DFMT1_SA_SHIFT)) & SMU_XRDC_MDA_W3_0_DFMT1_SA_MASK) 465 466 #define SMU_XRDC_MDA_W3_0_DFMT1_DIDB_MASK (0x100U) 467 #define SMU_XRDC_MDA_W3_0_DFMT1_DIDB_SHIFT (8U) 468 #define SMU_XRDC_MDA_W3_0_DFMT1_DIDB_WIDTH (1U) 469 #define SMU_XRDC_MDA_W3_0_DFMT1_DIDB(x) (((uint32_t)(((uint32_t)(x)) << SMU_XRDC_MDA_W3_0_DFMT1_DIDB_SHIFT)) & SMU_XRDC_MDA_W3_0_DFMT1_DIDB_MASK) 470 471 #define SMU_XRDC_MDA_W3_0_DFMT1_LPID_MASK (0xF000000U) 472 #define SMU_XRDC_MDA_W3_0_DFMT1_LPID_SHIFT (24U) 473 #define SMU_XRDC_MDA_W3_0_DFMT1_LPID_WIDTH (4U) 474 #define SMU_XRDC_MDA_W3_0_DFMT1_LPID(x) (((uint32_t)(((uint32_t)(x)) << SMU_XRDC_MDA_W3_0_DFMT1_LPID_SHIFT)) & SMU_XRDC_MDA_W3_0_DFMT1_LPID_MASK) 475 476 #define SMU_XRDC_MDA_W3_0_DFMT1_LPE_MASK (0x10000000U) 477 #define SMU_XRDC_MDA_W3_0_DFMT1_LPE_SHIFT (28U) 478 #define SMU_XRDC_MDA_W3_0_DFMT1_LPE_WIDTH (1U) 479 #define SMU_XRDC_MDA_W3_0_DFMT1_LPE(x) (((uint32_t)(((uint32_t)(x)) << SMU_XRDC_MDA_W3_0_DFMT1_LPE_SHIFT)) & SMU_XRDC_MDA_W3_0_DFMT1_LPE_MASK) 480 481 #define SMU_XRDC_MDA_W3_0_DFMT1_DFMT_MASK (0x20000000U) 482 #define SMU_XRDC_MDA_W3_0_DFMT1_DFMT_SHIFT (29U) 483 #define SMU_XRDC_MDA_W3_0_DFMT1_DFMT_WIDTH (1U) 484 #define SMU_XRDC_MDA_W3_0_DFMT1_DFMT(x) (((uint32_t)(((uint32_t)(x)) << SMU_XRDC_MDA_W3_0_DFMT1_DFMT_SHIFT)) & SMU_XRDC_MDA_W3_0_DFMT1_DFMT_MASK) 485 486 #define SMU_XRDC_MDA_W3_0_DFMT1_LK1_MASK (0x40000000U) 487 #define SMU_XRDC_MDA_W3_0_DFMT1_LK1_SHIFT (30U) 488 #define SMU_XRDC_MDA_W3_0_DFMT1_LK1_WIDTH (1U) 489 #define SMU_XRDC_MDA_W3_0_DFMT1_LK1(x) (((uint32_t)(((uint32_t)(x)) << SMU_XRDC_MDA_W3_0_DFMT1_LK1_SHIFT)) & SMU_XRDC_MDA_W3_0_DFMT1_LK1_MASK) 490 491 #define SMU_XRDC_MDA_W3_0_DFMT1_VLD_MASK (0x80000000U) 492 #define SMU_XRDC_MDA_W3_0_DFMT1_VLD_SHIFT (31U) 493 #define SMU_XRDC_MDA_W3_0_DFMT1_VLD_WIDTH (1U) 494 #define SMU_XRDC_MDA_W3_0_DFMT1_VLD(x) (((uint32_t)(((uint32_t)(x)) << SMU_XRDC_MDA_W3_0_DFMT1_VLD_SHIFT)) & SMU_XRDC_MDA_W3_0_DFMT1_VLD_MASK) 495 /*! @} */ 496 497 /*! @name MDA_W4_0_DFMT1 - Master Domain Assignment */ 498 /*! @{ */ 499 500 #define SMU_XRDC_MDA_W4_0_DFMT1_DID_MASK (0xFU) 501 #define SMU_XRDC_MDA_W4_0_DFMT1_DID_SHIFT (0U) 502 #define SMU_XRDC_MDA_W4_0_DFMT1_DID_WIDTH (4U) 503 #define SMU_XRDC_MDA_W4_0_DFMT1_DID(x) (((uint32_t)(((uint32_t)(x)) << SMU_XRDC_MDA_W4_0_DFMT1_DID_SHIFT)) & SMU_XRDC_MDA_W4_0_DFMT1_DID_MASK) 504 505 #define SMU_XRDC_MDA_W4_0_DFMT1_PA_MASK (0x30U) 506 #define SMU_XRDC_MDA_W4_0_DFMT1_PA_SHIFT (4U) 507 #define SMU_XRDC_MDA_W4_0_DFMT1_PA_WIDTH (2U) 508 #define SMU_XRDC_MDA_W4_0_DFMT1_PA(x) (((uint32_t)(((uint32_t)(x)) << SMU_XRDC_MDA_W4_0_DFMT1_PA_SHIFT)) & SMU_XRDC_MDA_W4_0_DFMT1_PA_MASK) 509 510 #define SMU_XRDC_MDA_W4_0_DFMT1_SA_MASK (0xC0U) 511 #define SMU_XRDC_MDA_W4_0_DFMT1_SA_SHIFT (6U) 512 #define SMU_XRDC_MDA_W4_0_DFMT1_SA_WIDTH (2U) 513 #define SMU_XRDC_MDA_W4_0_DFMT1_SA(x) (((uint32_t)(((uint32_t)(x)) << SMU_XRDC_MDA_W4_0_DFMT1_SA_SHIFT)) & SMU_XRDC_MDA_W4_0_DFMT1_SA_MASK) 514 515 #define SMU_XRDC_MDA_W4_0_DFMT1_DIDB_MASK (0x100U) 516 #define SMU_XRDC_MDA_W4_0_DFMT1_DIDB_SHIFT (8U) 517 #define SMU_XRDC_MDA_W4_0_DFMT1_DIDB_WIDTH (1U) 518 #define SMU_XRDC_MDA_W4_0_DFMT1_DIDB(x) (((uint32_t)(((uint32_t)(x)) << SMU_XRDC_MDA_W4_0_DFMT1_DIDB_SHIFT)) & SMU_XRDC_MDA_W4_0_DFMT1_DIDB_MASK) 519 520 #define SMU_XRDC_MDA_W4_0_DFMT1_LPID_MASK (0xF000000U) 521 #define SMU_XRDC_MDA_W4_0_DFMT1_LPID_SHIFT (24U) 522 #define SMU_XRDC_MDA_W4_0_DFMT1_LPID_WIDTH (4U) 523 #define SMU_XRDC_MDA_W4_0_DFMT1_LPID(x) (((uint32_t)(((uint32_t)(x)) << SMU_XRDC_MDA_W4_0_DFMT1_LPID_SHIFT)) & SMU_XRDC_MDA_W4_0_DFMT1_LPID_MASK) 524 525 #define SMU_XRDC_MDA_W4_0_DFMT1_LPE_MASK (0x10000000U) 526 #define SMU_XRDC_MDA_W4_0_DFMT1_LPE_SHIFT (28U) 527 #define SMU_XRDC_MDA_W4_0_DFMT1_LPE_WIDTH (1U) 528 #define SMU_XRDC_MDA_W4_0_DFMT1_LPE(x) (((uint32_t)(((uint32_t)(x)) << SMU_XRDC_MDA_W4_0_DFMT1_LPE_SHIFT)) & SMU_XRDC_MDA_W4_0_DFMT1_LPE_MASK) 529 530 #define SMU_XRDC_MDA_W4_0_DFMT1_DFMT_MASK (0x20000000U) 531 #define SMU_XRDC_MDA_W4_0_DFMT1_DFMT_SHIFT (29U) 532 #define SMU_XRDC_MDA_W4_0_DFMT1_DFMT_WIDTH (1U) 533 #define SMU_XRDC_MDA_W4_0_DFMT1_DFMT(x) (((uint32_t)(((uint32_t)(x)) << SMU_XRDC_MDA_W4_0_DFMT1_DFMT_SHIFT)) & SMU_XRDC_MDA_W4_0_DFMT1_DFMT_MASK) 534 535 #define SMU_XRDC_MDA_W4_0_DFMT1_LK1_MASK (0x40000000U) 536 #define SMU_XRDC_MDA_W4_0_DFMT1_LK1_SHIFT (30U) 537 #define SMU_XRDC_MDA_W4_0_DFMT1_LK1_WIDTH (1U) 538 #define SMU_XRDC_MDA_W4_0_DFMT1_LK1(x) (((uint32_t)(((uint32_t)(x)) << SMU_XRDC_MDA_W4_0_DFMT1_LK1_SHIFT)) & SMU_XRDC_MDA_W4_0_DFMT1_LK1_MASK) 539 540 #define SMU_XRDC_MDA_W4_0_DFMT1_VLD_MASK (0x80000000U) 541 #define SMU_XRDC_MDA_W4_0_DFMT1_VLD_SHIFT (31U) 542 #define SMU_XRDC_MDA_W4_0_DFMT1_VLD_WIDTH (1U) 543 #define SMU_XRDC_MDA_W4_0_DFMT1_VLD(x) (((uint32_t)(((uint32_t)(x)) << SMU_XRDC_MDA_W4_0_DFMT1_VLD_SHIFT)) & SMU_XRDC_MDA_W4_0_DFMT1_VLD_MASK) 544 /*! @} */ 545 546 /*! @name MDA_W5_0_DFMT1 - Master Domain Assignment */ 547 /*! @{ */ 548 549 #define SMU_XRDC_MDA_W5_0_DFMT1_DID_MASK (0xFU) 550 #define SMU_XRDC_MDA_W5_0_DFMT1_DID_SHIFT (0U) 551 #define SMU_XRDC_MDA_W5_0_DFMT1_DID_WIDTH (4U) 552 #define SMU_XRDC_MDA_W5_0_DFMT1_DID(x) (((uint32_t)(((uint32_t)(x)) << SMU_XRDC_MDA_W5_0_DFMT1_DID_SHIFT)) & SMU_XRDC_MDA_W5_0_DFMT1_DID_MASK) 553 554 #define SMU_XRDC_MDA_W5_0_DFMT1_PA_MASK (0x30U) 555 #define SMU_XRDC_MDA_W5_0_DFMT1_PA_SHIFT (4U) 556 #define SMU_XRDC_MDA_W5_0_DFMT1_PA_WIDTH (2U) 557 #define SMU_XRDC_MDA_W5_0_DFMT1_PA(x) (((uint32_t)(((uint32_t)(x)) << SMU_XRDC_MDA_W5_0_DFMT1_PA_SHIFT)) & SMU_XRDC_MDA_W5_0_DFMT1_PA_MASK) 558 559 #define SMU_XRDC_MDA_W5_0_DFMT1_SA_MASK (0xC0U) 560 #define SMU_XRDC_MDA_W5_0_DFMT1_SA_SHIFT (6U) 561 #define SMU_XRDC_MDA_W5_0_DFMT1_SA_WIDTH (2U) 562 #define SMU_XRDC_MDA_W5_0_DFMT1_SA(x) (((uint32_t)(((uint32_t)(x)) << SMU_XRDC_MDA_W5_0_DFMT1_SA_SHIFT)) & SMU_XRDC_MDA_W5_0_DFMT1_SA_MASK) 563 564 #define SMU_XRDC_MDA_W5_0_DFMT1_DIDB_MASK (0x100U) 565 #define SMU_XRDC_MDA_W5_0_DFMT1_DIDB_SHIFT (8U) 566 #define SMU_XRDC_MDA_W5_0_DFMT1_DIDB_WIDTH (1U) 567 #define SMU_XRDC_MDA_W5_0_DFMT1_DIDB(x) (((uint32_t)(((uint32_t)(x)) << SMU_XRDC_MDA_W5_0_DFMT1_DIDB_SHIFT)) & SMU_XRDC_MDA_W5_0_DFMT1_DIDB_MASK) 568 569 #define SMU_XRDC_MDA_W5_0_DFMT1_LPID_MASK (0xF000000U) 570 #define SMU_XRDC_MDA_W5_0_DFMT1_LPID_SHIFT (24U) 571 #define SMU_XRDC_MDA_W5_0_DFMT1_LPID_WIDTH (4U) 572 #define SMU_XRDC_MDA_W5_0_DFMT1_LPID(x) (((uint32_t)(((uint32_t)(x)) << SMU_XRDC_MDA_W5_0_DFMT1_LPID_SHIFT)) & SMU_XRDC_MDA_W5_0_DFMT1_LPID_MASK) 573 574 #define SMU_XRDC_MDA_W5_0_DFMT1_LPE_MASK (0x10000000U) 575 #define SMU_XRDC_MDA_W5_0_DFMT1_LPE_SHIFT (28U) 576 #define SMU_XRDC_MDA_W5_0_DFMT1_LPE_WIDTH (1U) 577 #define SMU_XRDC_MDA_W5_0_DFMT1_LPE(x) (((uint32_t)(((uint32_t)(x)) << SMU_XRDC_MDA_W5_0_DFMT1_LPE_SHIFT)) & SMU_XRDC_MDA_W5_0_DFMT1_LPE_MASK) 578 579 #define SMU_XRDC_MDA_W5_0_DFMT1_DFMT_MASK (0x20000000U) 580 #define SMU_XRDC_MDA_W5_0_DFMT1_DFMT_SHIFT (29U) 581 #define SMU_XRDC_MDA_W5_0_DFMT1_DFMT_WIDTH (1U) 582 #define SMU_XRDC_MDA_W5_0_DFMT1_DFMT(x) (((uint32_t)(((uint32_t)(x)) << SMU_XRDC_MDA_W5_0_DFMT1_DFMT_SHIFT)) & SMU_XRDC_MDA_W5_0_DFMT1_DFMT_MASK) 583 584 #define SMU_XRDC_MDA_W5_0_DFMT1_LK1_MASK (0x40000000U) 585 #define SMU_XRDC_MDA_W5_0_DFMT1_LK1_SHIFT (30U) 586 #define SMU_XRDC_MDA_W5_0_DFMT1_LK1_WIDTH (1U) 587 #define SMU_XRDC_MDA_W5_0_DFMT1_LK1(x) (((uint32_t)(((uint32_t)(x)) << SMU_XRDC_MDA_W5_0_DFMT1_LK1_SHIFT)) & SMU_XRDC_MDA_W5_0_DFMT1_LK1_MASK) 588 589 #define SMU_XRDC_MDA_W5_0_DFMT1_VLD_MASK (0x80000000U) 590 #define SMU_XRDC_MDA_W5_0_DFMT1_VLD_SHIFT (31U) 591 #define SMU_XRDC_MDA_W5_0_DFMT1_VLD_WIDTH (1U) 592 #define SMU_XRDC_MDA_W5_0_DFMT1_VLD(x) (((uint32_t)(((uint32_t)(x)) << SMU_XRDC_MDA_W5_0_DFMT1_VLD_SHIFT)) & SMU_XRDC_MDA_W5_0_DFMT1_VLD_MASK) 593 /*! @} */ 594 595 /*! @name MDA_W6_0_DFMT1 - Master Domain Assignment */ 596 /*! @{ */ 597 598 #define SMU_XRDC_MDA_W6_0_DFMT1_DID_MASK (0xFU) 599 #define SMU_XRDC_MDA_W6_0_DFMT1_DID_SHIFT (0U) 600 #define SMU_XRDC_MDA_W6_0_DFMT1_DID_WIDTH (4U) 601 #define SMU_XRDC_MDA_W6_0_DFMT1_DID(x) (((uint32_t)(((uint32_t)(x)) << SMU_XRDC_MDA_W6_0_DFMT1_DID_SHIFT)) & SMU_XRDC_MDA_W6_0_DFMT1_DID_MASK) 602 603 #define SMU_XRDC_MDA_W6_0_DFMT1_PA_MASK (0x30U) 604 #define SMU_XRDC_MDA_W6_0_DFMT1_PA_SHIFT (4U) 605 #define SMU_XRDC_MDA_W6_0_DFMT1_PA_WIDTH (2U) 606 #define SMU_XRDC_MDA_W6_0_DFMT1_PA(x) (((uint32_t)(((uint32_t)(x)) << SMU_XRDC_MDA_W6_0_DFMT1_PA_SHIFT)) & SMU_XRDC_MDA_W6_0_DFMT1_PA_MASK) 607 608 #define SMU_XRDC_MDA_W6_0_DFMT1_SA_MASK (0xC0U) 609 #define SMU_XRDC_MDA_W6_0_DFMT1_SA_SHIFT (6U) 610 #define SMU_XRDC_MDA_W6_0_DFMT1_SA_WIDTH (2U) 611 #define SMU_XRDC_MDA_W6_0_DFMT1_SA(x) (((uint32_t)(((uint32_t)(x)) << SMU_XRDC_MDA_W6_0_DFMT1_SA_SHIFT)) & SMU_XRDC_MDA_W6_0_DFMT1_SA_MASK) 612 613 #define SMU_XRDC_MDA_W6_0_DFMT1_DIDB_MASK (0x100U) 614 #define SMU_XRDC_MDA_W6_0_DFMT1_DIDB_SHIFT (8U) 615 #define SMU_XRDC_MDA_W6_0_DFMT1_DIDB_WIDTH (1U) 616 #define SMU_XRDC_MDA_W6_0_DFMT1_DIDB(x) (((uint32_t)(((uint32_t)(x)) << SMU_XRDC_MDA_W6_0_DFMT1_DIDB_SHIFT)) & SMU_XRDC_MDA_W6_0_DFMT1_DIDB_MASK) 617 618 #define SMU_XRDC_MDA_W6_0_DFMT1_LPID_MASK (0xF000000U) 619 #define SMU_XRDC_MDA_W6_0_DFMT1_LPID_SHIFT (24U) 620 #define SMU_XRDC_MDA_W6_0_DFMT1_LPID_WIDTH (4U) 621 #define SMU_XRDC_MDA_W6_0_DFMT1_LPID(x) (((uint32_t)(((uint32_t)(x)) << SMU_XRDC_MDA_W6_0_DFMT1_LPID_SHIFT)) & SMU_XRDC_MDA_W6_0_DFMT1_LPID_MASK) 622 623 #define SMU_XRDC_MDA_W6_0_DFMT1_LPE_MASK (0x10000000U) 624 #define SMU_XRDC_MDA_W6_0_DFMT1_LPE_SHIFT (28U) 625 #define SMU_XRDC_MDA_W6_0_DFMT1_LPE_WIDTH (1U) 626 #define SMU_XRDC_MDA_W6_0_DFMT1_LPE(x) (((uint32_t)(((uint32_t)(x)) << SMU_XRDC_MDA_W6_0_DFMT1_LPE_SHIFT)) & SMU_XRDC_MDA_W6_0_DFMT1_LPE_MASK) 627 628 #define SMU_XRDC_MDA_W6_0_DFMT1_DFMT_MASK (0x20000000U) 629 #define SMU_XRDC_MDA_W6_0_DFMT1_DFMT_SHIFT (29U) 630 #define SMU_XRDC_MDA_W6_0_DFMT1_DFMT_WIDTH (1U) 631 #define SMU_XRDC_MDA_W6_0_DFMT1_DFMT(x) (((uint32_t)(((uint32_t)(x)) << SMU_XRDC_MDA_W6_0_DFMT1_DFMT_SHIFT)) & SMU_XRDC_MDA_W6_0_DFMT1_DFMT_MASK) 632 633 #define SMU_XRDC_MDA_W6_0_DFMT1_LK1_MASK (0x40000000U) 634 #define SMU_XRDC_MDA_W6_0_DFMT1_LK1_SHIFT (30U) 635 #define SMU_XRDC_MDA_W6_0_DFMT1_LK1_WIDTH (1U) 636 #define SMU_XRDC_MDA_W6_0_DFMT1_LK1(x) (((uint32_t)(((uint32_t)(x)) << SMU_XRDC_MDA_W6_0_DFMT1_LK1_SHIFT)) & SMU_XRDC_MDA_W6_0_DFMT1_LK1_MASK) 637 638 #define SMU_XRDC_MDA_W6_0_DFMT1_VLD_MASK (0x80000000U) 639 #define SMU_XRDC_MDA_W6_0_DFMT1_VLD_SHIFT (31U) 640 #define SMU_XRDC_MDA_W6_0_DFMT1_VLD_WIDTH (1U) 641 #define SMU_XRDC_MDA_W6_0_DFMT1_VLD(x) (((uint32_t)(((uint32_t)(x)) << SMU_XRDC_MDA_W6_0_DFMT1_VLD_SHIFT)) & SMU_XRDC_MDA_W6_0_DFMT1_VLD_MASK) 642 /*! @} */ 643 644 /*! @name MDA_W7_0_DFMT1 - Master Domain Assignment */ 645 /*! @{ */ 646 647 #define SMU_XRDC_MDA_W7_0_DFMT1_DID_MASK (0xFU) 648 #define SMU_XRDC_MDA_W7_0_DFMT1_DID_SHIFT (0U) 649 #define SMU_XRDC_MDA_W7_0_DFMT1_DID_WIDTH (4U) 650 #define SMU_XRDC_MDA_W7_0_DFMT1_DID(x) (((uint32_t)(((uint32_t)(x)) << SMU_XRDC_MDA_W7_0_DFMT1_DID_SHIFT)) & SMU_XRDC_MDA_W7_0_DFMT1_DID_MASK) 651 652 #define SMU_XRDC_MDA_W7_0_DFMT1_PA_MASK (0x30U) 653 #define SMU_XRDC_MDA_W7_0_DFMT1_PA_SHIFT (4U) 654 #define SMU_XRDC_MDA_W7_0_DFMT1_PA_WIDTH (2U) 655 #define SMU_XRDC_MDA_W7_0_DFMT1_PA(x) (((uint32_t)(((uint32_t)(x)) << SMU_XRDC_MDA_W7_0_DFMT1_PA_SHIFT)) & SMU_XRDC_MDA_W7_0_DFMT1_PA_MASK) 656 657 #define SMU_XRDC_MDA_W7_0_DFMT1_SA_MASK (0xC0U) 658 #define SMU_XRDC_MDA_W7_0_DFMT1_SA_SHIFT (6U) 659 #define SMU_XRDC_MDA_W7_0_DFMT1_SA_WIDTH (2U) 660 #define SMU_XRDC_MDA_W7_0_DFMT1_SA(x) (((uint32_t)(((uint32_t)(x)) << SMU_XRDC_MDA_W7_0_DFMT1_SA_SHIFT)) & SMU_XRDC_MDA_W7_0_DFMT1_SA_MASK) 661 662 #define SMU_XRDC_MDA_W7_0_DFMT1_DIDB_MASK (0x100U) 663 #define SMU_XRDC_MDA_W7_0_DFMT1_DIDB_SHIFT (8U) 664 #define SMU_XRDC_MDA_W7_0_DFMT1_DIDB_WIDTH (1U) 665 #define SMU_XRDC_MDA_W7_0_DFMT1_DIDB(x) (((uint32_t)(((uint32_t)(x)) << SMU_XRDC_MDA_W7_0_DFMT1_DIDB_SHIFT)) & SMU_XRDC_MDA_W7_0_DFMT1_DIDB_MASK) 666 667 #define SMU_XRDC_MDA_W7_0_DFMT1_LPID_MASK (0xF000000U) 668 #define SMU_XRDC_MDA_W7_0_DFMT1_LPID_SHIFT (24U) 669 #define SMU_XRDC_MDA_W7_0_DFMT1_LPID_WIDTH (4U) 670 #define SMU_XRDC_MDA_W7_0_DFMT1_LPID(x) (((uint32_t)(((uint32_t)(x)) << SMU_XRDC_MDA_W7_0_DFMT1_LPID_SHIFT)) & SMU_XRDC_MDA_W7_0_DFMT1_LPID_MASK) 671 672 #define SMU_XRDC_MDA_W7_0_DFMT1_LPE_MASK (0x10000000U) 673 #define SMU_XRDC_MDA_W7_0_DFMT1_LPE_SHIFT (28U) 674 #define SMU_XRDC_MDA_W7_0_DFMT1_LPE_WIDTH (1U) 675 #define SMU_XRDC_MDA_W7_0_DFMT1_LPE(x) (((uint32_t)(((uint32_t)(x)) << SMU_XRDC_MDA_W7_0_DFMT1_LPE_SHIFT)) & SMU_XRDC_MDA_W7_0_DFMT1_LPE_MASK) 676 677 #define SMU_XRDC_MDA_W7_0_DFMT1_DFMT_MASK (0x20000000U) 678 #define SMU_XRDC_MDA_W7_0_DFMT1_DFMT_SHIFT (29U) 679 #define SMU_XRDC_MDA_W7_0_DFMT1_DFMT_WIDTH (1U) 680 #define SMU_XRDC_MDA_W7_0_DFMT1_DFMT(x) (((uint32_t)(((uint32_t)(x)) << SMU_XRDC_MDA_W7_0_DFMT1_DFMT_SHIFT)) & SMU_XRDC_MDA_W7_0_DFMT1_DFMT_MASK) 681 682 #define SMU_XRDC_MDA_W7_0_DFMT1_LK1_MASK (0x40000000U) 683 #define SMU_XRDC_MDA_W7_0_DFMT1_LK1_SHIFT (30U) 684 #define SMU_XRDC_MDA_W7_0_DFMT1_LK1_WIDTH (1U) 685 #define SMU_XRDC_MDA_W7_0_DFMT1_LK1(x) (((uint32_t)(((uint32_t)(x)) << SMU_XRDC_MDA_W7_0_DFMT1_LK1_SHIFT)) & SMU_XRDC_MDA_W7_0_DFMT1_LK1_MASK) 686 687 #define SMU_XRDC_MDA_W7_0_DFMT1_VLD_MASK (0x80000000U) 688 #define SMU_XRDC_MDA_W7_0_DFMT1_VLD_SHIFT (31U) 689 #define SMU_XRDC_MDA_W7_0_DFMT1_VLD_WIDTH (1U) 690 #define SMU_XRDC_MDA_W7_0_DFMT1_VLD(x) (((uint32_t)(((uint32_t)(x)) << SMU_XRDC_MDA_W7_0_DFMT1_VLD_SHIFT)) & SMU_XRDC_MDA_W7_0_DFMT1_VLD_MASK) 691 /*! @} */ 692 693 /*! @name MDA_W0_1_DFMT1 - Master Domain Assignment */ 694 /*! @{ */ 695 696 #define SMU_XRDC_MDA_W0_1_DFMT1_DID_MASK (0xFU) 697 #define SMU_XRDC_MDA_W0_1_DFMT1_DID_SHIFT (0U) 698 #define SMU_XRDC_MDA_W0_1_DFMT1_DID_WIDTH (4U) 699 #define SMU_XRDC_MDA_W0_1_DFMT1_DID(x) (((uint32_t)(((uint32_t)(x)) << SMU_XRDC_MDA_W0_1_DFMT1_DID_SHIFT)) & SMU_XRDC_MDA_W0_1_DFMT1_DID_MASK) 700 701 #define SMU_XRDC_MDA_W0_1_DFMT1_PA_MASK (0x30U) 702 #define SMU_XRDC_MDA_W0_1_DFMT1_PA_SHIFT (4U) 703 #define SMU_XRDC_MDA_W0_1_DFMT1_PA_WIDTH (2U) 704 #define SMU_XRDC_MDA_W0_1_DFMT1_PA(x) (((uint32_t)(((uint32_t)(x)) << SMU_XRDC_MDA_W0_1_DFMT1_PA_SHIFT)) & SMU_XRDC_MDA_W0_1_DFMT1_PA_MASK) 705 706 #define SMU_XRDC_MDA_W0_1_DFMT1_SA_MASK (0xC0U) 707 #define SMU_XRDC_MDA_W0_1_DFMT1_SA_SHIFT (6U) 708 #define SMU_XRDC_MDA_W0_1_DFMT1_SA_WIDTH (2U) 709 #define SMU_XRDC_MDA_W0_1_DFMT1_SA(x) (((uint32_t)(((uint32_t)(x)) << SMU_XRDC_MDA_W0_1_DFMT1_SA_SHIFT)) & SMU_XRDC_MDA_W0_1_DFMT1_SA_MASK) 710 711 #define SMU_XRDC_MDA_W0_1_DFMT1_DIDB_MASK (0x100U) 712 #define SMU_XRDC_MDA_W0_1_DFMT1_DIDB_SHIFT (8U) 713 #define SMU_XRDC_MDA_W0_1_DFMT1_DIDB_WIDTH (1U) 714 #define SMU_XRDC_MDA_W0_1_DFMT1_DIDB(x) (((uint32_t)(((uint32_t)(x)) << SMU_XRDC_MDA_W0_1_DFMT1_DIDB_SHIFT)) & SMU_XRDC_MDA_W0_1_DFMT1_DIDB_MASK) 715 716 #define SMU_XRDC_MDA_W0_1_DFMT1_DFMT_MASK (0x20000000U) 717 #define SMU_XRDC_MDA_W0_1_DFMT1_DFMT_SHIFT (29U) 718 #define SMU_XRDC_MDA_W0_1_DFMT1_DFMT_WIDTH (1U) 719 #define SMU_XRDC_MDA_W0_1_DFMT1_DFMT(x) (((uint32_t)(((uint32_t)(x)) << SMU_XRDC_MDA_W0_1_DFMT1_DFMT_SHIFT)) & SMU_XRDC_MDA_W0_1_DFMT1_DFMT_MASK) 720 721 #define SMU_XRDC_MDA_W0_1_DFMT1_LK1_MASK (0x40000000U) 722 #define SMU_XRDC_MDA_W0_1_DFMT1_LK1_SHIFT (30U) 723 #define SMU_XRDC_MDA_W0_1_DFMT1_LK1_WIDTH (1U) 724 #define SMU_XRDC_MDA_W0_1_DFMT1_LK1(x) (((uint32_t)(((uint32_t)(x)) << SMU_XRDC_MDA_W0_1_DFMT1_LK1_SHIFT)) & SMU_XRDC_MDA_W0_1_DFMT1_LK1_MASK) 725 726 #define SMU_XRDC_MDA_W0_1_DFMT1_VLD_MASK (0x80000000U) 727 #define SMU_XRDC_MDA_W0_1_DFMT1_VLD_SHIFT (31U) 728 #define SMU_XRDC_MDA_W0_1_DFMT1_VLD_WIDTH (1U) 729 #define SMU_XRDC_MDA_W0_1_DFMT1_VLD(x) (((uint32_t)(((uint32_t)(x)) << SMU_XRDC_MDA_W0_1_DFMT1_VLD_SHIFT)) & SMU_XRDC_MDA_W0_1_DFMT1_VLD_MASK) 730 /*! @} */ 731 732 /*! @name PDAC_W0 - Peripheral Domain Access Control Word 0 */ 733 /*! @{ */ 734 735 #define SMU_XRDC_PDAC_W0_D0ACP_MASK (0x7U) 736 #define SMU_XRDC_PDAC_W0_D0ACP_SHIFT (0U) 737 #define SMU_XRDC_PDAC_W0_D0ACP_WIDTH (3U) 738 #define SMU_XRDC_PDAC_W0_D0ACP(x) (((uint32_t)(((uint32_t)(x)) << SMU_XRDC_PDAC_W0_D0ACP_SHIFT)) & SMU_XRDC_PDAC_W0_D0ACP_MASK) 739 740 #define SMU_XRDC_PDAC_W0_D1ACP_MASK (0x38U) 741 #define SMU_XRDC_PDAC_W0_D1ACP_SHIFT (3U) 742 #define SMU_XRDC_PDAC_W0_D1ACP_WIDTH (3U) 743 #define SMU_XRDC_PDAC_W0_D1ACP(x) (((uint32_t)(((uint32_t)(x)) << SMU_XRDC_PDAC_W0_D1ACP_SHIFT)) & SMU_XRDC_PDAC_W0_D1ACP_MASK) 744 745 #define SMU_XRDC_PDAC_W0_D2ACP_MASK (0x1C0U) 746 #define SMU_XRDC_PDAC_W0_D2ACP_SHIFT (6U) 747 #define SMU_XRDC_PDAC_W0_D2ACP_WIDTH (3U) 748 #define SMU_XRDC_PDAC_W0_D2ACP(x) (((uint32_t)(((uint32_t)(x)) << SMU_XRDC_PDAC_W0_D2ACP_SHIFT)) & SMU_XRDC_PDAC_W0_D2ACP_MASK) 749 750 #define SMU_XRDC_PDAC_W0_D3ACP_MASK (0xE00U) 751 #define SMU_XRDC_PDAC_W0_D3ACP_SHIFT (9U) 752 #define SMU_XRDC_PDAC_W0_D3ACP_WIDTH (3U) 753 #define SMU_XRDC_PDAC_W0_D3ACP(x) (((uint32_t)(((uint32_t)(x)) << SMU_XRDC_PDAC_W0_D3ACP_SHIFT)) & SMU_XRDC_PDAC_W0_D3ACP_MASK) 754 755 #define SMU_XRDC_PDAC_W0_D4ACP_MASK (0x7000U) 756 #define SMU_XRDC_PDAC_W0_D4ACP_SHIFT (12U) 757 #define SMU_XRDC_PDAC_W0_D4ACP_WIDTH (3U) 758 #define SMU_XRDC_PDAC_W0_D4ACP(x) (((uint32_t)(((uint32_t)(x)) << SMU_XRDC_PDAC_W0_D4ACP_SHIFT)) & SMU_XRDC_PDAC_W0_D4ACP_MASK) 759 760 #define SMU_XRDC_PDAC_W0_D5ACP_MASK (0x38000U) 761 #define SMU_XRDC_PDAC_W0_D5ACP_SHIFT (15U) 762 #define SMU_XRDC_PDAC_W0_D5ACP_WIDTH (3U) 763 #define SMU_XRDC_PDAC_W0_D5ACP(x) (((uint32_t)(((uint32_t)(x)) << SMU_XRDC_PDAC_W0_D5ACP_SHIFT)) & SMU_XRDC_PDAC_W0_D5ACP_MASK) 764 765 #define SMU_XRDC_PDAC_W0_D6ACP_MASK (0x1C0000U) 766 #define SMU_XRDC_PDAC_W0_D6ACP_SHIFT (18U) 767 #define SMU_XRDC_PDAC_W0_D6ACP_WIDTH (3U) 768 #define SMU_XRDC_PDAC_W0_D6ACP(x) (((uint32_t)(((uint32_t)(x)) << SMU_XRDC_PDAC_W0_D6ACP_SHIFT)) & SMU_XRDC_PDAC_W0_D6ACP_MASK) 769 770 #define SMU_XRDC_PDAC_W0_D7ACP_MASK (0xE00000U) 771 #define SMU_XRDC_PDAC_W0_D7ACP_SHIFT (21U) 772 #define SMU_XRDC_PDAC_W0_D7ACP_WIDTH (3U) 773 #define SMU_XRDC_PDAC_W0_D7ACP(x) (((uint32_t)(((uint32_t)(x)) << SMU_XRDC_PDAC_W0_D7ACP_SHIFT)) & SMU_XRDC_PDAC_W0_D7ACP_MASK) 774 775 #define SMU_XRDC_PDAC_W0_SNUM_MASK (0xF000000U) 776 #define SMU_XRDC_PDAC_W0_SNUM_SHIFT (24U) 777 #define SMU_XRDC_PDAC_W0_SNUM_WIDTH (4U) 778 #define SMU_XRDC_PDAC_W0_SNUM(x) (((uint32_t)(((uint32_t)(x)) << SMU_XRDC_PDAC_W0_SNUM_SHIFT)) & SMU_XRDC_PDAC_W0_SNUM_MASK) 779 780 #define SMU_XRDC_PDAC_W0_SE_MASK (0x40000000U) 781 #define SMU_XRDC_PDAC_W0_SE_SHIFT (30U) 782 #define SMU_XRDC_PDAC_W0_SE_WIDTH (1U) 783 #define SMU_XRDC_PDAC_W0_SE(x) (((uint32_t)(((uint32_t)(x)) << SMU_XRDC_PDAC_W0_SE_SHIFT)) & SMU_XRDC_PDAC_W0_SE_MASK) 784 /*! @} */ 785 786 /*! @name PDAC_W1 - Peripheral Domain Access Control Word 1 */ 787 /*! @{ */ 788 789 #define SMU_XRDC_PDAC_W1_D8ACP_MASK (0x7U) 790 #define SMU_XRDC_PDAC_W1_D8ACP_SHIFT (0U) 791 #define SMU_XRDC_PDAC_W1_D8ACP_WIDTH (3U) 792 #define SMU_XRDC_PDAC_W1_D8ACP(x) (((uint32_t)(((uint32_t)(x)) << SMU_XRDC_PDAC_W1_D8ACP_SHIFT)) & SMU_XRDC_PDAC_W1_D8ACP_MASK) 793 794 #define SMU_XRDC_PDAC_W1_D9ACP_MASK (0x38U) 795 #define SMU_XRDC_PDAC_W1_D9ACP_SHIFT (3U) 796 #define SMU_XRDC_PDAC_W1_D9ACP_WIDTH (3U) 797 #define SMU_XRDC_PDAC_W1_D9ACP(x) (((uint32_t)(((uint32_t)(x)) << SMU_XRDC_PDAC_W1_D9ACP_SHIFT)) & SMU_XRDC_PDAC_W1_D9ACP_MASK) 798 799 #define SMU_XRDC_PDAC_W1_D10ACP_MASK (0x1C0U) 800 #define SMU_XRDC_PDAC_W1_D10ACP_SHIFT (6U) 801 #define SMU_XRDC_PDAC_W1_D10ACP_WIDTH (3U) 802 #define SMU_XRDC_PDAC_W1_D10ACP(x) (((uint32_t)(((uint32_t)(x)) << SMU_XRDC_PDAC_W1_D10ACP_SHIFT)) & SMU_XRDC_PDAC_W1_D10ACP_MASK) 803 804 #define SMU_XRDC_PDAC_W1_D11ACP_MASK (0xE00U) 805 #define SMU_XRDC_PDAC_W1_D11ACP_SHIFT (9U) 806 #define SMU_XRDC_PDAC_W1_D11ACP_WIDTH (3U) 807 #define SMU_XRDC_PDAC_W1_D11ACP(x) (((uint32_t)(((uint32_t)(x)) << SMU_XRDC_PDAC_W1_D11ACP_SHIFT)) & SMU_XRDC_PDAC_W1_D11ACP_MASK) 808 809 #define SMU_XRDC_PDAC_W1_D12ACP_MASK (0x7000U) 810 #define SMU_XRDC_PDAC_W1_D12ACP_SHIFT (12U) 811 #define SMU_XRDC_PDAC_W1_D12ACP_WIDTH (3U) 812 #define SMU_XRDC_PDAC_W1_D12ACP(x) (((uint32_t)(((uint32_t)(x)) << SMU_XRDC_PDAC_W1_D12ACP_SHIFT)) & SMU_XRDC_PDAC_W1_D12ACP_MASK) 813 814 #define SMU_XRDC_PDAC_W1_D13ACP_MASK (0x38000U) 815 #define SMU_XRDC_PDAC_W1_D13ACP_SHIFT (15U) 816 #define SMU_XRDC_PDAC_W1_D13ACP_WIDTH (3U) 817 #define SMU_XRDC_PDAC_W1_D13ACP(x) (((uint32_t)(((uint32_t)(x)) << SMU_XRDC_PDAC_W1_D13ACP_SHIFT)) & SMU_XRDC_PDAC_W1_D13ACP_MASK) 818 819 #define SMU_XRDC_PDAC_W1_D14ACP_MASK (0x1C0000U) 820 #define SMU_XRDC_PDAC_W1_D14ACP_SHIFT (18U) 821 #define SMU_XRDC_PDAC_W1_D14ACP_WIDTH (3U) 822 #define SMU_XRDC_PDAC_W1_D14ACP(x) (((uint32_t)(((uint32_t)(x)) << SMU_XRDC_PDAC_W1_D14ACP_SHIFT)) & SMU_XRDC_PDAC_W1_D14ACP_MASK) 823 824 #define SMU_XRDC_PDAC_W1_D15ACP_MASK (0xE00000U) 825 #define SMU_XRDC_PDAC_W1_D15ACP_SHIFT (21U) 826 #define SMU_XRDC_PDAC_W1_D15ACP_WIDTH (3U) 827 #define SMU_XRDC_PDAC_W1_D15ACP(x) (((uint32_t)(((uint32_t)(x)) << SMU_XRDC_PDAC_W1_D15ACP_SHIFT)) & SMU_XRDC_PDAC_W1_D15ACP_MASK) 828 829 #define SMU_XRDC_PDAC_W1_LK2_MASK (0x60000000U) 830 #define SMU_XRDC_PDAC_W1_LK2_SHIFT (29U) 831 #define SMU_XRDC_PDAC_W1_LK2_WIDTH (2U) 832 #define SMU_XRDC_PDAC_W1_LK2(x) (((uint32_t)(((uint32_t)(x)) << SMU_XRDC_PDAC_W1_LK2_SHIFT)) & SMU_XRDC_PDAC_W1_LK2_MASK) 833 834 #define SMU_XRDC_PDAC_W1_VLD_MASK (0x80000000U) 835 #define SMU_XRDC_PDAC_W1_VLD_SHIFT (31U) 836 #define SMU_XRDC_PDAC_W1_VLD_WIDTH (1U) 837 #define SMU_XRDC_PDAC_W1_VLD(x) (((uint32_t)(((uint32_t)(x)) << SMU_XRDC_PDAC_W1_VLD_SHIFT)) & SMU_XRDC_PDAC_W1_VLD_MASK) 838 /*! @} */ 839 840 /*! @name XRDC_MRGD_W0 - Memory Region Descriptor Word 0 */ 841 /*! @{ */ 842 843 #define SMU_XRDC_XRDC_MRGD_W0_SRTADDR_MASK (0xFFFFFFE0U) 844 #define SMU_XRDC_XRDC_MRGD_W0_SRTADDR_SHIFT (5U) 845 #define SMU_XRDC_XRDC_MRGD_W0_SRTADDR_WIDTH (27U) 846 #define SMU_XRDC_XRDC_MRGD_W0_SRTADDR(x) (((uint32_t)(((uint32_t)(x)) << SMU_XRDC_XRDC_MRGD_W0_SRTADDR_SHIFT)) & SMU_XRDC_XRDC_MRGD_W0_SRTADDR_MASK) 847 /*! @} */ 848 849 /*! @name XRDC_MRGD_W1 - Memory Region Descriptor Word 1 */ 850 /*! @{ */ 851 852 #define SMU_XRDC_XRDC_MRGD_W1_ENDADDR_MASK (0xFFFFFFE0U) 853 #define SMU_XRDC_XRDC_MRGD_W1_ENDADDR_SHIFT (5U) 854 #define SMU_XRDC_XRDC_MRGD_W1_ENDADDR_WIDTH (27U) 855 #define SMU_XRDC_XRDC_MRGD_W1_ENDADDR(x) (((uint32_t)(((uint32_t)(x)) << SMU_XRDC_XRDC_MRGD_W1_ENDADDR_SHIFT)) & SMU_XRDC_XRDC_MRGD_W1_ENDADDR_MASK) 856 /*! @} */ 857 858 /*! @name XRDC_MRGD_W2 - Memory Region Descriptor Word 2 */ 859 /*! @{ */ 860 861 #define SMU_XRDC_XRDC_MRGD_W2_D0ACP_MASK (0x7U) 862 #define SMU_XRDC_XRDC_MRGD_W2_D0ACP_SHIFT (0U) 863 #define SMU_XRDC_XRDC_MRGD_W2_D0ACP_WIDTH (3U) 864 #define SMU_XRDC_XRDC_MRGD_W2_D0ACP(x) (((uint32_t)(((uint32_t)(x)) << SMU_XRDC_XRDC_MRGD_W2_D0ACP_SHIFT)) & SMU_XRDC_XRDC_MRGD_W2_D0ACP_MASK) 865 866 #define SMU_XRDC_XRDC_MRGD_W2_D1ACP_MASK (0x38U) 867 #define SMU_XRDC_XRDC_MRGD_W2_D1ACP_SHIFT (3U) 868 #define SMU_XRDC_XRDC_MRGD_W2_D1ACP_WIDTH (3U) 869 #define SMU_XRDC_XRDC_MRGD_W2_D1ACP(x) (((uint32_t)(((uint32_t)(x)) << SMU_XRDC_XRDC_MRGD_W2_D1ACP_SHIFT)) & SMU_XRDC_XRDC_MRGD_W2_D1ACP_MASK) 870 871 #define SMU_XRDC_XRDC_MRGD_W2_D2ACP_MASK (0x1C0U) 872 #define SMU_XRDC_XRDC_MRGD_W2_D2ACP_SHIFT (6U) 873 #define SMU_XRDC_XRDC_MRGD_W2_D2ACP_WIDTH (3U) 874 #define SMU_XRDC_XRDC_MRGD_W2_D2ACP(x) (((uint32_t)(((uint32_t)(x)) << SMU_XRDC_XRDC_MRGD_W2_D2ACP_SHIFT)) & SMU_XRDC_XRDC_MRGD_W2_D2ACP_MASK) 875 876 #define SMU_XRDC_XRDC_MRGD_W2_D3ACP_MASK (0xE00U) 877 #define SMU_XRDC_XRDC_MRGD_W2_D3ACP_SHIFT (9U) 878 #define SMU_XRDC_XRDC_MRGD_W2_D3ACP_WIDTH (3U) 879 #define SMU_XRDC_XRDC_MRGD_W2_D3ACP(x) (((uint32_t)(((uint32_t)(x)) << SMU_XRDC_XRDC_MRGD_W2_D3ACP_SHIFT)) & SMU_XRDC_XRDC_MRGD_W2_D3ACP_MASK) 880 881 #define SMU_XRDC_XRDC_MRGD_W2_D4ACP_MASK (0x7000U) 882 #define SMU_XRDC_XRDC_MRGD_W2_D4ACP_SHIFT (12U) 883 #define SMU_XRDC_XRDC_MRGD_W2_D4ACP_WIDTH (3U) 884 #define SMU_XRDC_XRDC_MRGD_W2_D4ACP(x) (((uint32_t)(((uint32_t)(x)) << SMU_XRDC_XRDC_MRGD_W2_D4ACP_SHIFT)) & SMU_XRDC_XRDC_MRGD_W2_D4ACP_MASK) 885 886 #define SMU_XRDC_XRDC_MRGD_W2_D5ACP_MASK (0x38000U) 887 #define SMU_XRDC_XRDC_MRGD_W2_D5ACP_SHIFT (15U) 888 #define SMU_XRDC_XRDC_MRGD_W2_D5ACP_WIDTH (3U) 889 #define SMU_XRDC_XRDC_MRGD_W2_D5ACP(x) (((uint32_t)(((uint32_t)(x)) << SMU_XRDC_XRDC_MRGD_W2_D5ACP_SHIFT)) & SMU_XRDC_XRDC_MRGD_W2_D5ACP_MASK) 890 891 #define SMU_XRDC_XRDC_MRGD_W2_D6ACP_MASK (0x1C0000U) 892 #define SMU_XRDC_XRDC_MRGD_W2_D6ACP_SHIFT (18U) 893 #define SMU_XRDC_XRDC_MRGD_W2_D6ACP_WIDTH (3U) 894 #define SMU_XRDC_XRDC_MRGD_W2_D6ACP(x) (((uint32_t)(((uint32_t)(x)) << SMU_XRDC_XRDC_MRGD_W2_D6ACP_SHIFT)) & SMU_XRDC_XRDC_MRGD_W2_D6ACP_MASK) 895 896 #define SMU_XRDC_XRDC_MRGD_W2_D7ACP_MASK (0xE00000U) 897 #define SMU_XRDC_XRDC_MRGD_W2_D7ACP_SHIFT (21U) 898 #define SMU_XRDC_XRDC_MRGD_W2_D7ACP_WIDTH (3U) 899 #define SMU_XRDC_XRDC_MRGD_W2_D7ACP(x) (((uint32_t)(((uint32_t)(x)) << SMU_XRDC_XRDC_MRGD_W2_D7ACP_SHIFT)) & SMU_XRDC_XRDC_MRGD_W2_D7ACP_MASK) 900 901 #define SMU_XRDC_XRDC_MRGD_W2_SNUM_MASK (0xF000000U) 902 #define SMU_XRDC_XRDC_MRGD_W2_SNUM_SHIFT (24U) 903 #define SMU_XRDC_XRDC_MRGD_W2_SNUM_WIDTH (4U) 904 #define SMU_XRDC_XRDC_MRGD_W2_SNUM(x) (((uint32_t)(((uint32_t)(x)) << SMU_XRDC_XRDC_MRGD_W2_SNUM_SHIFT)) & SMU_XRDC_XRDC_MRGD_W2_SNUM_MASK) 905 906 #define SMU_XRDC_XRDC_MRGD_W2_SE_MASK (0x40000000U) 907 #define SMU_XRDC_XRDC_MRGD_W2_SE_SHIFT (30U) 908 #define SMU_XRDC_XRDC_MRGD_W2_SE_WIDTH (1U) 909 #define SMU_XRDC_XRDC_MRGD_W2_SE(x) (((uint32_t)(((uint32_t)(x)) << SMU_XRDC_XRDC_MRGD_W2_SE_SHIFT)) & SMU_XRDC_XRDC_MRGD_W2_SE_MASK) 910 /*! @} */ 911 912 /*! @name XRDC_MRGD_W3 - Memory Region Descriptor Word 3 */ 913 /*! @{ */ 914 915 #define SMU_XRDC_XRDC_MRGD_W3_D8ACP_MASK (0x7U) 916 #define SMU_XRDC_XRDC_MRGD_W3_D8ACP_SHIFT (0U) 917 #define SMU_XRDC_XRDC_MRGD_W3_D8ACP_WIDTH (3U) 918 #define SMU_XRDC_XRDC_MRGD_W3_D8ACP(x) (((uint32_t)(((uint32_t)(x)) << SMU_XRDC_XRDC_MRGD_W3_D8ACP_SHIFT)) & SMU_XRDC_XRDC_MRGD_W3_D8ACP_MASK) 919 920 #define SMU_XRDC_XRDC_MRGD_W3_D9ACP_MASK (0x38U) 921 #define SMU_XRDC_XRDC_MRGD_W3_D9ACP_SHIFT (3U) 922 #define SMU_XRDC_XRDC_MRGD_W3_D9ACP_WIDTH (3U) 923 #define SMU_XRDC_XRDC_MRGD_W3_D9ACP(x) (((uint32_t)(((uint32_t)(x)) << SMU_XRDC_XRDC_MRGD_W3_D9ACP_SHIFT)) & SMU_XRDC_XRDC_MRGD_W3_D9ACP_MASK) 924 925 #define SMU_XRDC_XRDC_MRGD_W3_D10ACP_MASK (0x1C0U) 926 #define SMU_XRDC_XRDC_MRGD_W3_D10ACP_SHIFT (6U) 927 #define SMU_XRDC_XRDC_MRGD_W3_D10ACP_WIDTH (3U) 928 #define SMU_XRDC_XRDC_MRGD_W3_D10ACP(x) (((uint32_t)(((uint32_t)(x)) << SMU_XRDC_XRDC_MRGD_W3_D10ACP_SHIFT)) & SMU_XRDC_XRDC_MRGD_W3_D10ACP_MASK) 929 930 #define SMU_XRDC_XRDC_MRGD_W3_D11ACP_MASK (0xE00U) 931 #define SMU_XRDC_XRDC_MRGD_W3_D11ACP_SHIFT (9U) 932 #define SMU_XRDC_XRDC_MRGD_W3_D11ACP_WIDTH (3U) 933 #define SMU_XRDC_XRDC_MRGD_W3_D11ACP(x) (((uint32_t)(((uint32_t)(x)) << SMU_XRDC_XRDC_MRGD_W3_D11ACP_SHIFT)) & SMU_XRDC_XRDC_MRGD_W3_D11ACP_MASK) 934 935 #define SMU_XRDC_XRDC_MRGD_W3_D12ACP_MASK (0x7000U) 936 #define SMU_XRDC_XRDC_MRGD_W3_D12ACP_SHIFT (12U) 937 #define SMU_XRDC_XRDC_MRGD_W3_D12ACP_WIDTH (3U) 938 #define SMU_XRDC_XRDC_MRGD_W3_D12ACP(x) (((uint32_t)(((uint32_t)(x)) << SMU_XRDC_XRDC_MRGD_W3_D12ACP_SHIFT)) & SMU_XRDC_XRDC_MRGD_W3_D12ACP_MASK) 939 940 #define SMU_XRDC_XRDC_MRGD_W3_D13ACP_MASK (0x38000U) 941 #define SMU_XRDC_XRDC_MRGD_W3_D13ACP_SHIFT (15U) 942 #define SMU_XRDC_XRDC_MRGD_W3_D13ACP_WIDTH (3U) 943 #define SMU_XRDC_XRDC_MRGD_W3_D13ACP(x) (((uint32_t)(((uint32_t)(x)) << SMU_XRDC_XRDC_MRGD_W3_D13ACP_SHIFT)) & SMU_XRDC_XRDC_MRGD_W3_D13ACP_MASK) 944 945 #define SMU_XRDC_XRDC_MRGD_W3_D14ACP_MASK (0x1C0000U) 946 #define SMU_XRDC_XRDC_MRGD_W3_D14ACP_SHIFT (18U) 947 #define SMU_XRDC_XRDC_MRGD_W3_D14ACP_WIDTH (3U) 948 #define SMU_XRDC_XRDC_MRGD_W3_D14ACP(x) (((uint32_t)(((uint32_t)(x)) << SMU_XRDC_XRDC_MRGD_W3_D14ACP_SHIFT)) & SMU_XRDC_XRDC_MRGD_W3_D14ACP_MASK) 949 950 #define SMU_XRDC_XRDC_MRGD_W3_D15ACP_MASK (0xE00000U) 951 #define SMU_XRDC_XRDC_MRGD_W3_D15ACP_SHIFT (21U) 952 #define SMU_XRDC_XRDC_MRGD_W3_D15ACP_WIDTH (3U) 953 #define SMU_XRDC_XRDC_MRGD_W3_D15ACP(x) (((uint32_t)(((uint32_t)(x)) << SMU_XRDC_XRDC_MRGD_W3_D15ACP_SHIFT)) & SMU_XRDC_XRDC_MRGD_W3_D15ACP_MASK) 954 955 #define SMU_XRDC_XRDC_MRGD_W3_LK2_MASK (0x60000000U) 956 #define SMU_XRDC_XRDC_MRGD_W3_LK2_SHIFT (29U) 957 #define SMU_XRDC_XRDC_MRGD_W3_LK2_WIDTH (2U) 958 #define SMU_XRDC_XRDC_MRGD_W3_LK2(x) (((uint32_t)(((uint32_t)(x)) << SMU_XRDC_XRDC_MRGD_W3_LK2_SHIFT)) & SMU_XRDC_XRDC_MRGD_W3_LK2_MASK) 959 960 #define SMU_XRDC_XRDC_MRGD_W3_VLD_MASK (0x80000000U) 961 #define SMU_XRDC_XRDC_MRGD_W3_VLD_SHIFT (31U) 962 #define SMU_XRDC_XRDC_MRGD_W3_VLD_WIDTH (1U) 963 #define SMU_XRDC_XRDC_MRGD_W3_VLD(x) (((uint32_t)(((uint32_t)(x)) << SMU_XRDC_XRDC_MRGD_W3_VLD_SHIFT)) & SMU_XRDC_XRDC_MRGD_W3_VLD_MASK) 964 /*! @} */ 965 966 /*! 967 * @} 968 */ /* end of group SMU_XRDC_Register_Masks */ 969 970 /*! 971 * @} 972 */ /* end of group SMU_XRDC_Peripheral_Access_Layer */ 973 974 #endif /* #if !defined(S32Z2_SMU_XRDC_H_) */ 975
