1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2024 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32Z2_SMU_SRG_S.h 10 * @version 2.3 11 * @date 2024-05-03 12 * @brief Peripheral Access Layer for S32Z2_SMU_SRG_S 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32Z2_SMU_SRG_S_H_) /* Check if memory map has not been already included */ 58 #define S32Z2_SMU_SRG_S_H_ 59 60 #include "S32Z2_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- SMU_SRG_S Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup SMU_SRG_S_Peripheral_Access_Layer SMU_SRG_S Peripheral Access Layer 68 * @{ 69 */ 70 71 /** SMU_SRG_S - Register Layout Typedef */ 72 typedef struct { 73 __IO uint32_t CR0; /**< Control 0, offset: 0x0 */ 74 uint8_t RESERVED_0[252]; 75 __IO uint32_t LCR0; /**< Lock Control 0, offset: 0x100 */ 76 uint8_t RESERVED_1[4]; 77 __IO uint32_t LCR2; /**< Lock Control 2, offset: 0x108 */ 78 __IO uint32_t LCR3; /**< Lock Control 3, offset: 0x10C */ 79 __IO uint32_t LCR4; /**< Lock Control 4, offset: 0x110 */ 80 uint8_t RESERVED_2[8]; 81 __IO uint32_t LCR7; /**< Lock Control 7, offset: 0x11C */ 82 uint8_t RESERVED_3[224]; 83 __IO uint32_t SR0; /**< Status 0, offset: 0x200 */ 84 } SMU_SRG_S_Type, *SMU_SRG_S_MemMapPtr; 85 86 /** Number of instances of the SMU_SRG_S module. */ 87 #define SMU_SRG_S_INSTANCE_COUNT (1u) 88 89 /* SMU_SRG_S - Peripheral instance base addresses */ 90 /** Peripheral SMU__SRG_S base address */ 91 #define IP_SMU__SRG_S_BASE (0x45064000u) 92 /** Peripheral SMU__SRG_S base pointer */ 93 #define IP_SMU__SRG_S ((SMU_SRG_S_Type *)IP_SMU__SRG_S_BASE) 94 /** Array initializer of SMU_SRG_S peripheral base addresses */ 95 #define IP_SMU_SRG_S_BASE_ADDRS { IP_SMU__SRG_S_BASE } 96 /** Array initializer of SMU_SRG_S peripheral base pointers */ 97 #define IP_SMU_SRG_S_BASE_PTRS { IP_SMU__SRG_S } 98 99 /* ---------------------------------------------------------------------------- 100 -- SMU_SRG_S Register Masks 101 ---------------------------------------------------------------------------- */ 102 103 /*! 104 * @addtogroup SMU_SRG_S_Register_Masks SMU_SRG_S Register Masks 105 * @{ 106 */ 107 108 /*! @name CR0 - Control 0 */ 109 /*! @{ */ 110 111 #define SMU_SRG_S_CR0_MSTR0DOW_MASK (0x1U) 112 #define SMU_SRG_S_CR0_MSTR0DOW_SHIFT (0U) 113 #define SMU_SRG_S_CR0_MSTR0DOW_WIDTH (1U) 114 #define SMU_SRG_S_CR0_MSTR0DOW(x) (((uint32_t)(((uint32_t)(x)) << SMU_SRG_S_CR0_MSTR0DOW_SHIFT)) & SMU_SRG_S_CR0_MSTR0DOW_MASK) 115 116 #define SMU_SRG_S_CR0_CCMDOW_MASK (0x2U) 117 #define SMU_SRG_S_CR0_CCMDOW_SHIFT (1U) 118 #define SMU_SRG_S_CR0_CCMDOW_WIDTH (1U) 119 #define SMU_SRG_S_CR0_CCMDOW(x) (((uint32_t)(((uint32_t)(x)) << SMU_SRG_S_CR0_CCMDOW_SHIFT)) & SMU_SRG_S_CR0_CCMDOW_MASK) 120 121 #define SMU_SRG_S_CR0_CSMDOW_MASK (0x4U) 122 #define SMU_SRG_S_CR0_CSMDOW_SHIFT (2U) 123 #define SMU_SRG_S_CR0_CSMDOW_WIDTH (1U) 124 #define SMU_SRG_S_CR0_CSMDOW(x) (((uint32_t)(((uint32_t)(x)) << SMU_SRG_S_CR0_CSMDOW_SHIFT)) & SMU_SRG_S_CR0_CSMDOW_MASK) 125 126 #define SMU_SRG_S_CR0_DEDOW_MASK (0x8U) 127 #define SMU_SRG_S_CR0_DEDOW_SHIFT (3U) 128 #define SMU_SRG_S_CR0_DEDOW_WIDTH (1U) 129 #define SMU_SRG_S_CR0_DEDOW(x) (((uint32_t)(((uint32_t)(x)) << SMU_SRG_S_CR0_DEDOW_SHIFT)) & SMU_SRG_S_CR0_DEDOW_MASK) 130 131 #define SMU_SRG_S_CR0_MSTR0HPE_MASK (0x100U) 132 #define SMU_SRG_S_CR0_MSTR0HPE_SHIFT (8U) 133 #define SMU_SRG_S_CR0_MSTR0HPE_WIDTH (1U) 134 #define SMU_SRG_S_CR0_MSTR0HPE(x) (((uint32_t)(((uint32_t)(x)) << SMU_SRG_S_CR0_MSTR0HPE_SHIFT)) & SMU_SRG_S_CR0_MSTR0HPE_MASK) 135 136 #define SMU_SRG_S_CR0_CCMHPE_MASK (0x200U) 137 #define SMU_SRG_S_CR0_CCMHPE_SHIFT (9U) 138 #define SMU_SRG_S_CR0_CCMHPE_WIDTH (1U) 139 #define SMU_SRG_S_CR0_CCMHPE(x) (((uint32_t)(((uint32_t)(x)) << SMU_SRG_S_CR0_CCMHPE_SHIFT)) & SMU_SRG_S_CR0_CCMHPE_MASK) 140 141 #define SMU_SRG_S_CR0_CSMHPE_MASK (0x400U) 142 #define SMU_SRG_S_CR0_CSMHPE_SHIFT (10U) 143 #define SMU_SRG_S_CR0_CSMHPE_WIDTH (1U) 144 #define SMU_SRG_S_CR0_CSMHPE(x) (((uint32_t)(((uint32_t)(x)) << SMU_SRG_S_CR0_CSMHPE_SHIFT)) & SMU_SRG_S_CR0_CSMHPE_MASK) 145 146 #define SMU_SRG_S_CR0_SLV0SBE_MASK (0x10000U) 147 #define SMU_SRG_S_CR0_SLV0SBE_SHIFT (16U) 148 #define SMU_SRG_S_CR0_SLV0SBE_WIDTH (1U) 149 #define SMU_SRG_S_CR0_SLV0SBE(x) (((uint32_t)(((uint32_t)(x)) << SMU_SRG_S_CR0_SLV0SBE_SHIFT)) & SMU_SRG_S_CR0_SLV0SBE_MASK) 150 151 #define SMU_SRG_S_CR0_AIPS0SBE_MASK (0x20000U) 152 #define SMU_SRG_S_CR0_AIPS0SBE_SHIFT (17U) 153 #define SMU_SRG_S_CR0_AIPS0SBE_WIDTH (1U) 154 #define SMU_SRG_S_CR0_AIPS0SBE(x) (((uint32_t)(((uint32_t)(x)) << SMU_SRG_S_CR0_AIPS0SBE_SHIFT)) & SMU_SRG_S_CR0_AIPS0SBE_MASK) 155 156 #define SMU_SRG_S_CR0_AIPS1SBE_MASK (0x40000U) 157 #define SMU_SRG_S_CR0_AIPS1SBE_SHIFT (18U) 158 #define SMU_SRG_S_CR0_AIPS1SBE_WIDTH (1U) 159 #define SMU_SRG_S_CR0_AIPS1SBE(x) (((uint32_t)(((uint32_t)(x)) << SMU_SRG_S_CR0_AIPS1SBE_SHIFT)) & SMU_SRG_S_CR0_AIPS1SBE_MASK) 160 /*! @} */ 161 162 /*! @name LCR0 - Lock Control 0 */ 163 /*! @{ */ 164 165 #define SMU_SRG_S_LCR0_LNSMPU_MASK (0x10000U) 166 #define SMU_SRG_S_LCR0_LNSMPU_SHIFT (16U) 167 #define SMU_SRG_S_LCR0_LNSMPU_WIDTH (1U) 168 #define SMU_SRG_S_LCR0_LNSMPU(x) (((uint32_t)(((uint32_t)(x)) << SMU_SRG_S_LCR0_LNSMPU_SHIFT)) & SMU_SRG_S_LCR0_LNSMPU_MASK) 169 170 #define SMU_SRG_S_LCR0_LNSVTOR_MASK (0x40000U) 171 #define SMU_SRG_S_LCR0_LNSVTOR_SHIFT (18U) 172 #define SMU_SRG_S_LCR0_LNSVTOR_WIDTH (1U) 173 #define SMU_SRG_S_LCR0_LNSVTOR(x) (((uint32_t)(((uint32_t)(x)) << SMU_SRG_S_LCR0_LNSVTOR_SHIFT)) & SMU_SRG_S_LCR0_LNSVTOR_MASK) 174 175 #define SMU_SRG_S_LCR0_DID_MASK (0xF000000U) 176 #define SMU_SRG_S_LCR0_DID_SHIFT (24U) 177 #define SMU_SRG_S_LCR0_DID_WIDTH (4U) 178 #define SMU_SRG_S_LCR0_DID(x) (((uint32_t)(((uint32_t)(x)) << SMU_SRG_S_LCR0_DID_SHIFT)) & SMU_SRG_S_LCR0_DID_MASK) 179 180 #define SMU_SRG_S_LCR0_LKR_MASK (0xC0000000U) 181 #define SMU_SRG_S_LCR0_LKR_SHIFT (30U) 182 #define SMU_SRG_S_LCR0_LKR_WIDTH (2U) 183 #define SMU_SRG_S_LCR0_LKR(x) (((uint32_t)(((uint32_t)(x)) << SMU_SRG_S_LCR0_LKR_SHIFT)) & SMU_SRG_S_LCR0_LKR_MASK) 184 /*! @} */ 185 186 /*! @name LCR2 - Lock Control 2 */ 187 /*! @{ */ 188 189 #define SMU_SRG_S_LCR2_REMAP_EN_MASK (0x1U) 190 #define SMU_SRG_S_LCR2_REMAP_EN_SHIFT (0U) 191 #define SMU_SRG_S_LCR2_REMAP_EN_WIDTH (1U) 192 #define SMU_SRG_S_LCR2_REMAP_EN(x) (((uint32_t)(((uint32_t)(x)) << SMU_SRG_S_LCR2_REMAP_EN_SHIFT)) & SMU_SRG_S_LCR2_REMAP_EN_MASK) 193 194 #define SMU_SRG_S_LCR2_REMAP0_MASK (0x100U) 195 #define SMU_SRG_S_LCR2_REMAP0_SHIFT (8U) 196 #define SMU_SRG_S_LCR2_REMAP0_WIDTH (1U) 197 #define SMU_SRG_S_LCR2_REMAP0(x) (((uint32_t)(((uint32_t)(x)) << SMU_SRG_S_LCR2_REMAP0_SHIFT)) & SMU_SRG_S_LCR2_REMAP0_MASK) 198 199 #define SMU_SRG_S_LCR2_REMAP1_MASK (0x200U) 200 #define SMU_SRG_S_LCR2_REMAP1_SHIFT (9U) 201 #define SMU_SRG_S_LCR2_REMAP1_WIDTH (1U) 202 #define SMU_SRG_S_LCR2_REMAP1(x) (((uint32_t)(((uint32_t)(x)) << SMU_SRG_S_LCR2_REMAP1_SHIFT)) & SMU_SRG_S_LCR2_REMAP1_MASK) 203 204 #define SMU_SRG_S_LCR2_REMAP2_MASK (0x400U) 205 #define SMU_SRG_S_LCR2_REMAP2_SHIFT (10U) 206 #define SMU_SRG_S_LCR2_REMAP2_WIDTH (1U) 207 #define SMU_SRG_S_LCR2_REMAP2(x) (((uint32_t)(((uint32_t)(x)) << SMU_SRG_S_LCR2_REMAP2_SHIFT)) & SMU_SRG_S_LCR2_REMAP2_MASK) 208 209 #define SMU_SRG_S_LCR2_REMAP3_MASK (0x800U) 210 #define SMU_SRG_S_LCR2_REMAP3_SHIFT (11U) 211 #define SMU_SRG_S_LCR2_REMAP3_WIDTH (1U) 212 #define SMU_SRG_S_LCR2_REMAP3(x) (((uint32_t)(((uint32_t)(x)) << SMU_SRG_S_LCR2_REMAP3_SHIFT)) & SMU_SRG_S_LCR2_REMAP3_MASK) 213 214 #define SMU_SRG_S_LCR2_DID_MASK (0xF000000U) 215 #define SMU_SRG_S_LCR2_DID_SHIFT (24U) 216 #define SMU_SRG_S_LCR2_DID_WIDTH (4U) 217 #define SMU_SRG_S_LCR2_DID(x) (((uint32_t)(((uint32_t)(x)) << SMU_SRG_S_LCR2_DID_SHIFT)) & SMU_SRG_S_LCR2_DID_MASK) 218 219 #define SMU_SRG_S_LCR2_LKR_MASK (0xC0000000U) 220 #define SMU_SRG_S_LCR2_LKR_SHIFT (30U) 221 #define SMU_SRG_S_LCR2_LKR_WIDTH (2U) 222 #define SMU_SRG_S_LCR2_LKR(x) (((uint32_t)(((uint32_t)(x)) << SMU_SRG_S_LCR2_LKR_SHIFT)) & SMU_SRG_S_LCR2_LKR_MASK) 223 /*! @} */ 224 225 /*! @name LCR3 - Lock Control 3 */ 226 /*! @{ */ 227 228 #define SMU_SRG_S_LCR3_R0RO_MASK (0xF8U) 229 #define SMU_SRG_S_LCR3_R0RO_SHIFT (3U) 230 #define SMU_SRG_S_LCR3_R0RO_WIDTH (5U) 231 #define SMU_SRG_S_LCR3_R0RO(x) (((uint32_t)(((uint32_t)(x)) << SMU_SRG_S_LCR3_R0RO_SHIFT)) & SMU_SRG_S_LCR3_R0RO_MASK) 232 233 #define SMU_SRG_S_LCR3_R1RO_MASK (0xF800U) 234 #define SMU_SRG_S_LCR3_R1RO_SHIFT (11U) 235 #define SMU_SRG_S_LCR3_R1RO_WIDTH (5U) 236 #define SMU_SRG_S_LCR3_R1RO(x) (((uint32_t)(((uint32_t)(x)) << SMU_SRG_S_LCR3_R1RO_SHIFT)) & SMU_SRG_S_LCR3_R1RO_MASK) 237 238 #define SMU_SRG_S_LCR3_DID_MASK (0xF000000U) 239 #define SMU_SRG_S_LCR3_DID_SHIFT (24U) 240 #define SMU_SRG_S_LCR3_DID_WIDTH (4U) 241 #define SMU_SRG_S_LCR3_DID(x) (((uint32_t)(((uint32_t)(x)) << SMU_SRG_S_LCR3_DID_SHIFT)) & SMU_SRG_S_LCR3_DID_MASK) 242 243 #define SMU_SRG_S_LCR3_LKR_MASK (0xC0000000U) 244 #define SMU_SRG_S_LCR3_LKR_SHIFT (30U) 245 #define SMU_SRG_S_LCR3_LKR_WIDTH (2U) 246 #define SMU_SRG_S_LCR3_LKR(x) (((uint32_t)(((uint32_t)(x)) << SMU_SRG_S_LCR3_LKR_SHIFT)) & SMU_SRG_S_LCR3_LKR_MASK) 247 /*! @} */ 248 249 /*! @name LCR4 - Lock Control 4 */ 250 /*! @{ */ 251 252 #define SMU_SRG_S_LCR4_R2RO_MASK (0xF8U) 253 #define SMU_SRG_S_LCR4_R2RO_SHIFT (3U) 254 #define SMU_SRG_S_LCR4_R2RO_WIDTH (5U) 255 #define SMU_SRG_S_LCR4_R2RO(x) (((uint32_t)(((uint32_t)(x)) << SMU_SRG_S_LCR4_R2RO_SHIFT)) & SMU_SRG_S_LCR4_R2RO_MASK) 256 257 #define SMU_SRG_S_LCR4_R3RO_MASK (0xF800U) 258 #define SMU_SRG_S_LCR4_R3RO_SHIFT (11U) 259 #define SMU_SRG_S_LCR4_R3RO_WIDTH (5U) 260 #define SMU_SRG_S_LCR4_R3RO(x) (((uint32_t)(((uint32_t)(x)) << SMU_SRG_S_LCR4_R3RO_SHIFT)) & SMU_SRG_S_LCR4_R3RO_MASK) 261 262 #define SMU_SRG_S_LCR4_DID_MASK (0xF000000U) 263 #define SMU_SRG_S_LCR4_DID_SHIFT (24U) 264 #define SMU_SRG_S_LCR4_DID_WIDTH (4U) 265 #define SMU_SRG_S_LCR4_DID(x) (((uint32_t)(((uint32_t)(x)) << SMU_SRG_S_LCR4_DID_SHIFT)) & SMU_SRG_S_LCR4_DID_MASK) 266 267 #define SMU_SRG_S_LCR4_LKR_MASK (0xC0000000U) 268 #define SMU_SRG_S_LCR4_LKR_SHIFT (30U) 269 #define SMU_SRG_S_LCR4_LKR_WIDTH (2U) 270 #define SMU_SRG_S_LCR4_LKR(x) (((uint32_t)(((uint32_t)(x)) << SMU_SRG_S_LCR4_LKR_SHIFT)) & SMU_SRG_S_LCR4_LKR_MASK) 271 /*! @} */ 272 273 /*! @name LCR7 - Lock Control 7 */ 274 /*! @{ */ 275 276 #define SMU_SRG_S_LCR7_DBGSA_MASK (0x10000U) 277 #define SMU_SRG_S_LCR7_DBGSA_SHIFT (16U) 278 #define SMU_SRG_S_LCR7_DBGSA_WIDTH (1U) 279 #define SMU_SRG_S_LCR7_DBGSA(x) (((uint32_t)(((uint32_t)(x)) << SMU_SRG_S_LCR7_DBGSA_SHIFT)) & SMU_SRG_S_LCR7_DBGSA_MASK) 280 281 #define SMU_SRG_S_LCR7_DID_MASK (0xF000000U) 282 #define SMU_SRG_S_LCR7_DID_SHIFT (24U) 283 #define SMU_SRG_S_LCR7_DID_WIDTH (4U) 284 #define SMU_SRG_S_LCR7_DID(x) (((uint32_t)(((uint32_t)(x)) << SMU_SRG_S_LCR7_DID_SHIFT)) & SMU_SRG_S_LCR7_DID_MASK) 285 286 #define SMU_SRG_S_LCR7_LKR_MASK (0xC0000000U) 287 #define SMU_SRG_S_LCR7_LKR_SHIFT (30U) 288 #define SMU_SRG_S_LCR7_LKR_WIDTH (2U) 289 #define SMU_SRG_S_LCR7_LKR(x) (((uint32_t)(((uint32_t)(x)) << SMU_SRG_S_LCR7_LKR_SHIFT)) & SMU_SRG_S_LCR7_LKR_MASK) 290 /*! @} */ 291 292 /*! @name SR0 - Status 0 */ 293 /*! @{ */ 294 295 #define SMU_SRG_S_SR0_R0EA_MASK (0x1U) 296 #define SMU_SRG_S_SR0_R0EA_SHIFT (0U) 297 #define SMU_SRG_S_SR0_R0EA_WIDTH (1U) 298 #define SMU_SRG_S_SR0_R0EA(x) (((uint32_t)(((uint32_t)(x)) << SMU_SRG_S_SR0_R0EA_SHIFT)) & SMU_SRG_S_SR0_R0EA_MASK) 299 300 #define SMU_SRG_S_SR0_R1EA_MASK (0x2U) 301 #define SMU_SRG_S_SR0_R1EA_SHIFT (1U) 302 #define SMU_SRG_S_SR0_R1EA_WIDTH (1U) 303 #define SMU_SRG_S_SR0_R1EA(x) (((uint32_t)(((uint32_t)(x)) << SMU_SRG_S_SR0_R1EA_SHIFT)) & SMU_SRG_S_SR0_R1EA_MASK) 304 305 #define SMU_SRG_S_SR0_R2EA_MASK (0x4U) 306 #define SMU_SRG_S_SR0_R2EA_SHIFT (2U) 307 #define SMU_SRG_S_SR0_R2EA_WIDTH (1U) 308 #define SMU_SRG_S_SR0_R2EA(x) (((uint32_t)(((uint32_t)(x)) << SMU_SRG_S_SR0_R2EA_SHIFT)) & SMU_SRG_S_SR0_R2EA_MASK) 309 310 #define SMU_SRG_S_SR0_R3EA_MASK (0x8U) 311 #define SMU_SRG_S_SR0_R3EA_SHIFT (3U) 312 #define SMU_SRG_S_SR0_R3EA_WIDTH (1U) 313 #define SMU_SRG_S_SR0_R3EA(x) (((uint32_t)(((uint32_t)(x)) << SMU_SRG_S_SR0_R3EA_SHIFT)) & SMU_SRG_S_SR0_R3EA_MASK) 314 315 #define SMU_SRG_S_SR0_R0WEA_MASK (0x10U) 316 #define SMU_SRG_S_SR0_R0WEA_SHIFT (4U) 317 #define SMU_SRG_S_SR0_R0WEA_WIDTH (1U) 318 #define SMU_SRG_S_SR0_R0WEA(x) (((uint32_t)(((uint32_t)(x)) << SMU_SRG_S_SR0_R0WEA_SHIFT)) & SMU_SRG_S_SR0_R0WEA_MASK) 319 320 #define SMU_SRG_S_SR0_R1WEA_MASK (0x20U) 321 #define SMU_SRG_S_SR0_R1WEA_SHIFT (5U) 322 #define SMU_SRG_S_SR0_R1WEA_WIDTH (1U) 323 #define SMU_SRG_S_SR0_R1WEA(x) (((uint32_t)(((uint32_t)(x)) << SMU_SRG_S_SR0_R1WEA_SHIFT)) & SMU_SRG_S_SR0_R1WEA_MASK) 324 325 #define SMU_SRG_S_SR0_R2WEA_MASK (0x40U) 326 #define SMU_SRG_S_SR0_R2WEA_SHIFT (6U) 327 #define SMU_SRG_S_SR0_R2WEA_WIDTH (1U) 328 #define SMU_SRG_S_SR0_R2WEA(x) (((uint32_t)(((uint32_t)(x)) << SMU_SRG_S_SR0_R2WEA_SHIFT)) & SMU_SRG_S_SR0_R2WEA_MASK) 329 330 #define SMU_SRG_S_SR0_R3WEA_MASK (0x80U) 331 #define SMU_SRG_S_SR0_R3WEA_SHIFT (7U) 332 #define SMU_SRG_S_SR0_R3WEA_WIDTH (1U) 333 #define SMU_SRG_S_SR0_R3WEA(x) (((uint32_t)(((uint32_t)(x)) << SMU_SRG_S_SR0_R3WEA_SHIFT)) & SMU_SRG_S_SR0_R3WEA_MASK) 334 335 #define SMU_SRG_S_SR0_CTRE_MASK (0x100U) 336 #define SMU_SRG_S_SR0_CTRE_SHIFT (8U) 337 #define SMU_SRG_S_SR0_CTRE_WIDTH (1U) 338 #define SMU_SRG_S_SR0_CTRE(x) (((uint32_t)(((uint32_t)(x)) << SMU_SRG_S_SR0_CTRE_SHIFT)) & SMU_SRG_S_SR0_CTRE_MASK) 339 340 #define SMU_SRG_S_SR0_CDRE_MASK (0x200U) 341 #define SMU_SRG_S_SR0_CDRE_SHIFT (9U) 342 #define SMU_SRG_S_SR0_CDRE_WIDTH (1U) 343 #define SMU_SRG_S_SR0_CDRE(x) (((uint32_t)(((uint32_t)(x)) << SMU_SRG_S_SR0_CDRE_SHIFT)) & SMU_SRG_S_SR0_CDRE_MASK) 344 345 #define SMU_SRG_S_SR0_STRE_MASK (0x400U) 346 #define SMU_SRG_S_SR0_STRE_SHIFT (10U) 347 #define SMU_SRG_S_SR0_STRE_WIDTH (1U) 348 #define SMU_SRG_S_SR0_STRE(x) (((uint32_t)(((uint32_t)(x)) << SMU_SRG_S_SR0_STRE_SHIFT)) & SMU_SRG_S_SR0_STRE_MASK) 349 350 #define SMU_SRG_S_SR0_SDRE_MASK (0x800U) 351 #define SMU_SRG_S_SR0_SDRE_SHIFT (11U) 352 #define SMU_SRG_S_SR0_SDRE_WIDTH (1U) 353 #define SMU_SRG_S_SR0_SDRE(x) (((uint32_t)(((uint32_t)(x)) << SMU_SRG_S_SR0_SDRE_SHIFT)) & SMU_SRG_S_SR0_SDRE_MASK) 354 355 #define SMU_SRG_S_SR0_CCCMCRE_MASK (0x10000U) 356 #define SMU_SRG_S_SR0_CCCMCRE_SHIFT (16U) 357 #define SMU_SRG_S_SR0_CCCMCRE_WIDTH (1U) 358 #define SMU_SRG_S_SR0_CCCMCRE(x) (((uint32_t)(((uint32_t)(x)) << SMU_SRG_S_SR0_CCCMCRE_SHIFT)) & SMU_SRG_S_SR0_CCCMCRE_MASK) 359 360 #define SMU_SRG_S_SR0_SCCMCRE_MASK (0x20000U) 361 #define SMU_SRG_S_SR0_SCCMCRE_SHIFT (17U) 362 #define SMU_SRG_S_SR0_SCCMCRE_WIDTH (1U) 363 #define SMU_SRG_S_SR0_SCCMCRE(x) (((uint32_t)(((uint32_t)(x)) << SMU_SRG_S_SR0_SCCMCRE_SHIFT)) & SMU_SRG_S_SR0_SCCMCRE_MASK) 364 365 #define SMU_SRG_S_SR0_COREH_MASK (0x100000U) 366 #define SMU_SRG_S_SR0_COREH_SHIFT (20U) 367 #define SMU_SRG_S_SR0_COREH_WIDTH (1U) 368 #define SMU_SRG_S_SR0_COREH(x) (((uint32_t)(((uint32_t)(x)) << SMU_SRG_S_SR0_COREH_SHIFT)) & SMU_SRG_S_SR0_COREH_MASK) 369 370 #define SMU_SRG_S_SR0_CORETU_MASK (0x200000U) 371 #define SMU_SRG_S_SR0_CORETU_SHIFT (21U) 372 #define SMU_SRG_S_SR0_CORETU_WIDTH (1U) 373 #define SMU_SRG_S_SR0_CORETU(x) (((uint32_t)(((uint32_t)(x)) << SMU_SRG_S_SR0_CORETU_SHIFT)) & SMU_SRG_S_SR0_CORETU_MASK) 374 /*! @} */ 375 376 /*! 377 * @} 378 */ /* end of group SMU_SRG_S_Register_Masks */ 379 380 /*! 381 * @} 382 */ /* end of group SMU_SRG_S_Peripheral_Access_Layer */ 383 384 #endif /* #if !defined(S32Z2_SMU_SRG_S_H_) */ 385
