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Searched refs:SLEEPCON1_WAKEUPEN2_CLR_GPIO10_CH1_MASK (Results 1 – 9 of 9) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT735S/
DMIMXRT735S_hifi1.h50279 #define SLEEPCON1_WAKEUPEN2_CLR_GPIO10_CH1_MASK (0x4U) macro
50285 …t32_t)(x)) << SLEEPCON1_WAKEUPEN2_CLR_GPIO10_CH1_SHIFT)) & SLEEPCON1_WAKEUPEN2_CLR_GPIO10_CH1_MASK)
DMIMXRT735S_cm33_core1.h50339 #define SLEEPCON1_WAKEUPEN2_CLR_GPIO10_CH1_MASK (0x4U) macro
50345 …t32_t)(x)) << SLEEPCON1_WAKEUPEN2_CLR_GPIO10_CH1_SHIFT)) & SLEEPCON1_WAKEUPEN2_CLR_GPIO10_CH1_MASK)
DMIMXRT735S_ezhv.h74092 #define SLEEPCON1_WAKEUPEN2_CLR_GPIO10_CH1_MASK (0x4U) macro
74098 …t32_t)(x)) << SLEEPCON1_WAKEUPEN2_CLR_GPIO10_CH1_SHIFT)) & SLEEPCON1_WAKEUPEN2_CLR_GPIO10_CH1_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT758S/
DMIMXRT758S_cm33_core1.h53562 #define SLEEPCON1_WAKEUPEN2_CLR_GPIO10_CH1_MASK (0x4U) macro
53568 …t32_t)(x)) << SLEEPCON1_WAKEUPEN2_CLR_GPIO10_CH1_SHIFT)) & SLEEPCON1_WAKEUPEN2_CLR_GPIO10_CH1_MASK)
DMIMXRT758S_hifi1.h53500 #define SLEEPCON1_WAKEUPEN2_CLR_GPIO10_CH1_MASK (0x4U) macro
53506 …t32_t)(x)) << SLEEPCON1_WAKEUPEN2_CLR_GPIO10_CH1_SHIFT)) & SLEEPCON1_WAKEUPEN2_CLR_GPIO10_CH1_MASK)
DMIMXRT758S_ezhv.h77237 #define SLEEPCON1_WAKEUPEN2_CLR_GPIO10_CH1_MASK (0x4U) macro
77243 …t32_t)(x)) << SLEEPCON1_WAKEUPEN2_CLR_GPIO10_CH1_SHIFT)) & SLEEPCON1_WAKEUPEN2_CLR_GPIO10_CH1_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT798S/
DMIMXRT798S_hifi1.h53500 #define SLEEPCON1_WAKEUPEN2_CLR_GPIO10_CH1_MASK (0x4U) macro
53506 …t32_t)(x)) << SLEEPCON1_WAKEUPEN2_CLR_GPIO10_CH1_SHIFT)) & SLEEPCON1_WAKEUPEN2_CLR_GPIO10_CH1_MASK)
DMIMXRT798S_cm33_core1.h53562 #define SLEEPCON1_WAKEUPEN2_CLR_GPIO10_CH1_MASK (0x4U) macro
53568 …t32_t)(x)) << SLEEPCON1_WAKEUPEN2_CLR_GPIO10_CH1_SHIFT)) & SLEEPCON1_WAKEUPEN2_CLR_GPIO10_CH1_MASK)
DMIMXRT798S_ezhv.h77261 #define SLEEPCON1_WAKEUPEN2_CLR_GPIO10_CH1_MASK (0x4U) macro
77267 …t32_t)(x)) << SLEEPCON1_WAKEUPEN2_CLR_GPIO10_CH1_SHIFT)) & SLEEPCON1_WAKEUPEN2_CLR_GPIO10_CH1_MASK)