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Searched refs:SLEEPCON1_SLEEPCFG_RAM0_CLK_SHUTOFF_MASK (Results 1 – 15 of 15) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/components/power_manager/devices/MIMXRT735S/
Dfsl_pm_device.c277 …sc_RAM0CLK - RESC_GROUP_PERIPHERALS_START] = {0U, SLEEPCON1_SLEEPCFG_RAM0_CLK_SHUTOFF_MASK},
/hal_nxp-latest/mcux/mcux-sdk/components/power_manager/devices/MIMXRT758S/
Dfsl_pm_device.c277 …sc_RAM0CLK - RESC_GROUP_PERIPHERALS_START] = {0U, SLEEPCON1_SLEEPCFG_RAM0_CLK_SHUTOFF_MASK},
/hal_nxp-latest/mcux/mcux-sdk/components/power_manager/devices/MIMXRT798S/
Dfsl_pm_device.c277 …sc_RAM0CLK - RESC_GROUP_PERIPHERALS_START] = {0U, SLEEPCON1_SLEEPCFG_RAM0_CLK_SHUTOFF_MASK},
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT798S/drivers/
Dfsl_power.c98SLEEPCON1_SLEEPCFG_RAM0_CLK_SHUTOFF_MASK | SLEEPCON1_SLEEPCFG_RAM1_CLK_SHUTOFF_MASK | …
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT735S/drivers/
Dfsl_power.c98SLEEPCON1_SLEEPCFG_RAM0_CLK_SHUTOFF_MASK | SLEEPCON1_SLEEPCFG_RAM1_CLK_SHUTOFF_MASK | …
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT758S/drivers/
Dfsl_power.c98SLEEPCON1_SLEEPCFG_RAM0_CLK_SHUTOFF_MASK | SLEEPCON1_SLEEPCFG_RAM1_CLK_SHUTOFF_MASK | …
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT735S/
DMIMXRT735S_hifi1.h48399 #define SLEEPCON1_SLEEPCFG_RAM0_CLK_SHUTOFF_MASK (0x8U) macro
48405 …2_t)(x)) << SLEEPCON1_SLEEPCFG_RAM0_CLK_SHUTOFF_SHIFT)) & SLEEPCON1_SLEEPCFG_RAM0_CLK_SHUTOFF_MASK)
DMIMXRT735S_cm33_core1.h48459 #define SLEEPCON1_SLEEPCFG_RAM0_CLK_SHUTOFF_MASK (0x8U) macro
48465 …2_t)(x)) << SLEEPCON1_SLEEPCFG_RAM0_CLK_SHUTOFF_SHIFT)) & SLEEPCON1_SLEEPCFG_RAM0_CLK_SHUTOFF_MASK)
DMIMXRT735S_ezhv.h72212 #define SLEEPCON1_SLEEPCFG_RAM0_CLK_SHUTOFF_MASK (0x8U) macro
72218 …2_t)(x)) << SLEEPCON1_SLEEPCFG_RAM0_CLK_SHUTOFF_SHIFT)) & SLEEPCON1_SLEEPCFG_RAM0_CLK_SHUTOFF_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT758S/
DMIMXRT758S_cm33_core1.h51682 #define SLEEPCON1_SLEEPCFG_RAM0_CLK_SHUTOFF_MASK (0x8U) macro
51688 …2_t)(x)) << SLEEPCON1_SLEEPCFG_RAM0_CLK_SHUTOFF_SHIFT)) & SLEEPCON1_SLEEPCFG_RAM0_CLK_SHUTOFF_MASK)
DMIMXRT758S_hifi1.h51620 #define SLEEPCON1_SLEEPCFG_RAM0_CLK_SHUTOFF_MASK (0x8U) macro
51626 …2_t)(x)) << SLEEPCON1_SLEEPCFG_RAM0_CLK_SHUTOFF_SHIFT)) & SLEEPCON1_SLEEPCFG_RAM0_CLK_SHUTOFF_MASK)
DMIMXRT758S_ezhv.h75357 #define SLEEPCON1_SLEEPCFG_RAM0_CLK_SHUTOFF_MASK (0x8U) macro
75363 …2_t)(x)) << SLEEPCON1_SLEEPCFG_RAM0_CLK_SHUTOFF_SHIFT)) & SLEEPCON1_SLEEPCFG_RAM0_CLK_SHUTOFF_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT798S/
DMIMXRT798S_hifi1.h51620 #define SLEEPCON1_SLEEPCFG_RAM0_CLK_SHUTOFF_MASK (0x8U) macro
51626 …2_t)(x)) << SLEEPCON1_SLEEPCFG_RAM0_CLK_SHUTOFF_SHIFT)) & SLEEPCON1_SLEEPCFG_RAM0_CLK_SHUTOFF_MASK)
DMIMXRT798S_cm33_core1.h51682 #define SLEEPCON1_SLEEPCFG_RAM0_CLK_SHUTOFF_MASK (0x8U) macro
51688 …2_t)(x)) << SLEEPCON1_SLEEPCFG_RAM0_CLK_SHUTOFF_SHIFT)) & SLEEPCON1_SLEEPCFG_RAM0_CLK_SHUTOFF_MASK)
DMIMXRT798S_ezhv.h75381 #define SLEEPCON1_SLEEPCFG_RAM0_CLK_SHUTOFF_MASK (0x8U) macro
75387 …2_t)(x)) << SLEEPCON1_SLEEPCFG_RAM0_CLK_SHUTOFF_SHIFT)) & SLEEPCON1_SLEEPCFG_RAM0_CLK_SHUTOFF_MASK)