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Searched refs:SLEEPCON1_RUNCFG_CLR_AUDPLLANA_PD_MASK (Results 1 – 9 of 9) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT735S/
DMIMXRT735S_hifi1.h48843 #define SLEEPCON1_RUNCFG_CLR_AUDPLLANA_PD_MASK (0x4000U) macro
48849 …int32_t)(x)) << SLEEPCON1_RUNCFG_CLR_AUDPLLANA_PD_SHIFT)) & SLEEPCON1_RUNCFG_CLR_AUDPLLANA_PD_MASK)
DMIMXRT735S_cm33_core1.h48903 #define SLEEPCON1_RUNCFG_CLR_AUDPLLANA_PD_MASK (0x4000U) macro
48909 …int32_t)(x)) << SLEEPCON1_RUNCFG_CLR_AUDPLLANA_PD_SHIFT)) & SLEEPCON1_RUNCFG_CLR_AUDPLLANA_PD_MASK)
DMIMXRT735S_ezhv.h72656 #define SLEEPCON1_RUNCFG_CLR_AUDPLLANA_PD_MASK (0x4000U) macro
72662 …int32_t)(x)) << SLEEPCON1_RUNCFG_CLR_AUDPLLANA_PD_SHIFT)) & SLEEPCON1_RUNCFG_CLR_AUDPLLANA_PD_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT758S/
DMIMXRT758S_cm33_core1.h52126 #define SLEEPCON1_RUNCFG_CLR_AUDPLLANA_PD_MASK (0x4000U) macro
52132 …int32_t)(x)) << SLEEPCON1_RUNCFG_CLR_AUDPLLANA_PD_SHIFT)) & SLEEPCON1_RUNCFG_CLR_AUDPLLANA_PD_MASK)
DMIMXRT758S_hifi1.h52064 #define SLEEPCON1_RUNCFG_CLR_AUDPLLANA_PD_MASK (0x4000U) macro
52070 …int32_t)(x)) << SLEEPCON1_RUNCFG_CLR_AUDPLLANA_PD_SHIFT)) & SLEEPCON1_RUNCFG_CLR_AUDPLLANA_PD_MASK)
DMIMXRT758S_ezhv.h75801 #define SLEEPCON1_RUNCFG_CLR_AUDPLLANA_PD_MASK (0x4000U) macro
75807 …int32_t)(x)) << SLEEPCON1_RUNCFG_CLR_AUDPLLANA_PD_SHIFT)) & SLEEPCON1_RUNCFG_CLR_AUDPLLANA_PD_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT798S/
DMIMXRT798S_hifi1.h52064 #define SLEEPCON1_RUNCFG_CLR_AUDPLLANA_PD_MASK (0x4000U) macro
52070 …int32_t)(x)) << SLEEPCON1_RUNCFG_CLR_AUDPLLANA_PD_SHIFT)) & SLEEPCON1_RUNCFG_CLR_AUDPLLANA_PD_MASK)
DMIMXRT798S_cm33_core1.h52126 #define SLEEPCON1_RUNCFG_CLR_AUDPLLANA_PD_MASK (0x4000U) macro
52132 …int32_t)(x)) << SLEEPCON1_RUNCFG_CLR_AUDPLLANA_PD_SHIFT)) & SLEEPCON1_RUNCFG_CLR_AUDPLLANA_PD_MASK)
DMIMXRT798S_ezhv.h75825 #define SLEEPCON1_RUNCFG_CLR_AUDPLLANA_PD_MASK (0x4000U) macro
75831 …int32_t)(x)) << SLEEPCON1_RUNCFG_CLR_AUDPLLANA_PD_SHIFT)) & SLEEPCON1_RUNCFG_CLR_AUDPLLANA_PD_MASK)