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Searched refs:SLEEPCON1_RUNCFG_CLR_ADC0_PD_MASK (Results 1 – 9 of 9) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT735S/
DMIMXRT735S_hifi1.h48859 #define SLEEPCON1_RUNCFG_CLR_ADC0_PD_MASK (0x10000U) macro
48865 …t32_t)(((uint32_t)(x)) << SLEEPCON1_RUNCFG_CLR_ADC0_PD_SHIFT)) & SLEEPCON1_RUNCFG_CLR_ADC0_PD_MASK)
DMIMXRT735S_cm33_core1.h48919 #define SLEEPCON1_RUNCFG_CLR_ADC0_PD_MASK (0x10000U) macro
48925 …t32_t)(((uint32_t)(x)) << SLEEPCON1_RUNCFG_CLR_ADC0_PD_SHIFT)) & SLEEPCON1_RUNCFG_CLR_ADC0_PD_MASK)
DMIMXRT735S_ezhv.h72672 #define SLEEPCON1_RUNCFG_CLR_ADC0_PD_MASK (0x10000U) macro
72678 …t32_t)(((uint32_t)(x)) << SLEEPCON1_RUNCFG_CLR_ADC0_PD_SHIFT)) & SLEEPCON1_RUNCFG_CLR_ADC0_PD_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT758S/
DMIMXRT758S_cm33_core1.h52142 #define SLEEPCON1_RUNCFG_CLR_ADC0_PD_MASK (0x10000U) macro
52148 …t32_t)(((uint32_t)(x)) << SLEEPCON1_RUNCFG_CLR_ADC0_PD_SHIFT)) & SLEEPCON1_RUNCFG_CLR_ADC0_PD_MASK)
DMIMXRT758S_hifi1.h52080 #define SLEEPCON1_RUNCFG_CLR_ADC0_PD_MASK (0x10000U) macro
52086 …t32_t)(((uint32_t)(x)) << SLEEPCON1_RUNCFG_CLR_ADC0_PD_SHIFT)) & SLEEPCON1_RUNCFG_CLR_ADC0_PD_MASK)
DMIMXRT758S_ezhv.h75817 #define SLEEPCON1_RUNCFG_CLR_ADC0_PD_MASK (0x10000U) macro
75823 …t32_t)(((uint32_t)(x)) << SLEEPCON1_RUNCFG_CLR_ADC0_PD_SHIFT)) & SLEEPCON1_RUNCFG_CLR_ADC0_PD_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT798S/
DMIMXRT798S_hifi1.h52080 #define SLEEPCON1_RUNCFG_CLR_ADC0_PD_MASK (0x10000U) macro
52086 …t32_t)(((uint32_t)(x)) << SLEEPCON1_RUNCFG_CLR_ADC0_PD_SHIFT)) & SLEEPCON1_RUNCFG_CLR_ADC0_PD_MASK)
DMIMXRT798S_cm33_core1.h52142 #define SLEEPCON1_RUNCFG_CLR_ADC0_PD_MASK (0x10000U) macro
52148 …t32_t)(((uint32_t)(x)) << SLEEPCON1_RUNCFG_CLR_ADC0_PD_SHIFT)) & SLEEPCON1_RUNCFG_CLR_ADC0_PD_MASK)
DMIMXRT798S_ezhv.h75841 #define SLEEPCON1_RUNCFG_CLR_ADC0_PD_MASK (0x10000U) macro
75847 …t32_t)(((uint32_t)(x)) << SLEEPCON1_RUNCFG_CLR_ADC0_PD_SHIFT)) & SLEEPCON1_RUNCFG_CLR_ADC0_PD_MASK)