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Searched refs:SLEEPCON0_SLEEPCFG_RAM1_CLK_SHUTOFF_MASK (Results 1 – 13 of 13) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/components/power_manager/devices/MIMXRT735S/
Dfsl_pm_device.c262 …sc_RAM1CLK - RESC_GROUP_PERIPHERALS_START] = {0U, SLEEPCON0_SLEEPCFG_RAM1_CLK_SHUTOFF_MASK},
/hal_nxp-latest/mcux/mcux-sdk/components/power_manager/devices/MIMXRT758S/
Dfsl_pm_device.c262 …sc_RAM1CLK - RESC_GROUP_PERIPHERALS_START] = {0U, SLEEPCON0_SLEEPCFG_RAM1_CLK_SHUTOFF_MASK},
/hal_nxp-latest/mcux/mcux-sdk/components/power_manager/devices/MIMXRT798S/
Dfsl_pm_device.c262 …sc_RAM1CLK - RESC_GROUP_PERIPHERALS_START] = {0U, SLEEPCON0_SLEEPCFG_RAM1_CLK_SHUTOFF_MASK},
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT798S/drivers/
Dfsl_power.c66SLEEPCON0_SLEEPCFG_RAM1_CLK_SHUTOFF_MASK | SLEEPCON0_SLEEPCFG_COMN_MAINCLK_SHUTOFF_MASK | …
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT735S/drivers/
Dfsl_power.c66SLEEPCON0_SLEEPCFG_RAM1_CLK_SHUTOFF_MASK | SLEEPCON0_SLEEPCFG_COMN_MAINCLK_SHUTOFF_MASK | …
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT758S/drivers/
Dfsl_power.c66SLEEPCON0_SLEEPCFG_RAM1_CLK_SHUTOFF_MASK | SLEEPCON0_SLEEPCFG_COMN_MAINCLK_SHUTOFF_MASK | …
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT798S/
DMIMXRT798S_hifi4.h69498 #define SLEEPCON0_SLEEPCFG_RAM1_CLK_SHUTOFF_MASK (0x10U) macro
69504 …2_t)(x)) << SLEEPCON0_SLEEPCFG_RAM1_CLK_SHUTOFF_SHIFT)) & SLEEPCON0_SLEEPCFG_RAM1_CLK_SHUTOFF_MASK)
DMIMXRT798S_cm33_core0.h69585 #define SLEEPCON0_SLEEPCFG_RAM1_CLK_SHUTOFF_MASK (0x10U) macro
69591 …2_t)(x)) << SLEEPCON0_SLEEPCFG_RAM1_CLK_SHUTOFF_SHIFT)) & SLEEPCON0_SLEEPCFG_RAM1_CLK_SHUTOFF_MASK)
DMIMXRT798S_ezhv.h69782 #define SLEEPCON0_SLEEPCFG_RAM1_CLK_SHUTOFF_MASK (0x10U) macro
69788 …2_t)(x)) << SLEEPCON0_SLEEPCFG_RAM1_CLK_SHUTOFF_SHIFT)) & SLEEPCON0_SLEEPCFG_RAM1_CLK_SHUTOFF_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT735S/
DMIMXRT735S_ezhv.h66613 #define SLEEPCON0_SLEEPCFG_RAM1_CLK_SHUTOFF_MASK (0x10U) macro
66619 …2_t)(x)) << SLEEPCON0_SLEEPCFG_RAM1_CLK_SHUTOFF_SHIFT)) & SLEEPCON0_SLEEPCFG_RAM1_CLK_SHUTOFF_MASK)
DMIMXRT735S_cm33_core0.h66360 #define SLEEPCON0_SLEEPCFG_RAM1_CLK_SHUTOFF_MASK (0x10U) macro
66366 …2_t)(x)) << SLEEPCON0_SLEEPCFG_RAM1_CLK_SHUTOFF_SHIFT)) & SLEEPCON0_SLEEPCFG_RAM1_CLK_SHUTOFF_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT758S/
DMIMXRT758S_cm33_core0.h69585 #define SLEEPCON0_SLEEPCFG_RAM1_CLK_SHUTOFF_MASK (0x10U) macro
69591 …2_t)(x)) << SLEEPCON0_SLEEPCFG_RAM1_CLK_SHUTOFF_SHIFT)) & SLEEPCON0_SLEEPCFG_RAM1_CLK_SHUTOFF_MASK)
DMIMXRT758S_ezhv.h69758 #define SLEEPCON0_SLEEPCFG_RAM1_CLK_SHUTOFF_MASK (0x10U) macro
69764 …2_t)(x)) << SLEEPCON0_SLEEPCFG_RAM1_CLK_SHUTOFF_SHIFT)) & SLEEPCON0_SLEEPCFG_RAM1_CLK_SHUTOFF_MASK)