Home
last modified time | relevance | path

Searched refs:SLEEPCON0_SLEEPCFG_ADC0_PD_MASK (Results 1 – 13 of 13) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/components/power_manager/devices/MIMXRT735S/
Dfsl_pm_device.c273 [kResc_ADC0 - RESC_GROUP_PERIPHERALS_START] = {0U, SLEEPCON0_SLEEPCFG_ADC0_PD_MASK},
/hal_nxp-latest/mcux/mcux-sdk/components/power_manager/devices/MIMXRT758S/
Dfsl_pm_device.c273 [kResc_ADC0 - RESC_GROUP_PERIPHERALS_START] = {0U, SLEEPCON0_SLEEPCFG_ADC0_PD_MASK},
/hal_nxp-latest/mcux/mcux-sdk/components/power_manager/devices/MIMXRT798S/
Dfsl_pm_device.c273 [kResc_ADC0 - RESC_GROUP_PERIPHERALS_START] = {0U, SLEEPCON0_SLEEPCFG_ADC0_PD_MASK},
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT798S/drivers/
Dfsl_power.c70 …PCFG_AUDPLLANA_PD_MASK | SLEEPCON0_SLEEPCFG_AUDPLLLDO_PD_MASK | SLEEPCON0_SLEEPCFG_ADC0_PD_MASK | \
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT735S/drivers/
Dfsl_power.c70 …PCFG_AUDPLLANA_PD_MASK | SLEEPCON0_SLEEPCFG_AUDPLLLDO_PD_MASK | SLEEPCON0_SLEEPCFG_ADC0_PD_MASK | \
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT758S/drivers/
Dfsl_power.c70 …PCFG_AUDPLLANA_PD_MASK | SLEEPCON0_SLEEPCFG_AUDPLLLDO_PD_MASK | SLEEPCON0_SLEEPCFG_ADC0_PD_MASK | \
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT798S/
DMIMXRT798S_hifi4.h69594 #define SLEEPCON0_SLEEPCFG_ADC0_PD_MASK (0x10000U) macro
69600 …(uint32_t)(((uint32_t)(x)) << SLEEPCON0_SLEEPCFG_ADC0_PD_SHIFT)) & SLEEPCON0_SLEEPCFG_ADC0_PD_MASK)
DMIMXRT798S_cm33_core0.h69681 #define SLEEPCON0_SLEEPCFG_ADC0_PD_MASK (0x10000U) macro
69687 …(uint32_t)(((uint32_t)(x)) << SLEEPCON0_SLEEPCFG_ADC0_PD_SHIFT)) & SLEEPCON0_SLEEPCFG_ADC0_PD_MASK)
DMIMXRT798S_ezhv.h69878 #define SLEEPCON0_SLEEPCFG_ADC0_PD_MASK (0x10000U) macro
69884 …(uint32_t)(((uint32_t)(x)) << SLEEPCON0_SLEEPCFG_ADC0_PD_SHIFT)) & SLEEPCON0_SLEEPCFG_ADC0_PD_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT735S/
DMIMXRT735S_ezhv.h66709 #define SLEEPCON0_SLEEPCFG_ADC0_PD_MASK (0x10000U) macro
66715 …(uint32_t)(((uint32_t)(x)) << SLEEPCON0_SLEEPCFG_ADC0_PD_SHIFT)) & SLEEPCON0_SLEEPCFG_ADC0_PD_MASK)
DMIMXRT735S_cm33_core0.h66456 #define SLEEPCON0_SLEEPCFG_ADC0_PD_MASK (0x10000U) macro
66462 …(uint32_t)(((uint32_t)(x)) << SLEEPCON0_SLEEPCFG_ADC0_PD_SHIFT)) & SLEEPCON0_SLEEPCFG_ADC0_PD_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT758S/
DMIMXRT758S_cm33_core0.h69681 #define SLEEPCON0_SLEEPCFG_ADC0_PD_MASK (0x10000U) macro
69687 …(uint32_t)(((uint32_t)(x)) << SLEEPCON0_SLEEPCFG_ADC0_PD_SHIFT)) & SLEEPCON0_SLEEPCFG_ADC0_PD_MASK)
DMIMXRT758S_ezhv.h69854 #define SLEEPCON0_SLEEPCFG_ADC0_PD_MASK (0x10000U) macro
69860 …(uint32_t)(((uint32_t)(x)) << SLEEPCON0_SLEEPCFG_ADC0_PD_SHIFT)) & SLEEPCON0_SLEEPCFG_ADC0_PD_MASK)