1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2024 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32Z2_SIPI.h 10 * @version 2.3 11 * @date 2024-05-03 12 * @brief Peripheral Access Layer for S32Z2_SIPI 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32Z2_SIPI_H_) /* Check if memory map has not been already included */ 58 #define S32Z2_SIPI_H_ 59 60 #include "S32Z2_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- SIPI Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup SIPI_Peripheral_Access_Layer SIPI Peripheral Access Layer 68 * @{ 69 */ 70 71 /** SIPI - Size of Registers Arrays */ 72 #define SIPI_CDR2_COUNT 8u 73 74 /** SIPI - Register Layout Typedef */ 75 typedef struct { 76 __IO uint32_t CCR0; /**< SIPI Channel Control Register 0, offset: 0x0 */ 77 __IO uint32_t CSR0; /**< SIPI Channel Status Register 0, offset: 0x4 */ 78 uint8_t RESERVED_0[4]; 79 __IO uint32_t CIR0; /**< SIPI Channel Interrupt Register 0, offset: 0xC */ 80 __IO uint32_t CTOR0; /**< SIPI Channel Timeout Register 0, offset: 0x10 */ 81 __I uint32_t CCRC0; /**< SIPI Channel CRC Register 0, offset: 0x14 */ 82 __IO uint32_t CAR0; /**< SIPI Channel Address Register 0, offset: 0x18 */ 83 __IO uint32_t CDR0; /**< SIPI Channel Data Register 0, offset: 0x1C */ 84 __IO uint32_t CCR1; /**< SIPI Channel Control Register 1, offset: 0x20 */ 85 __IO uint32_t CSR1; /**< SIPI Channel Status Register 1, offset: 0x24 */ 86 uint8_t RESERVED_1[4]; 87 __IO uint32_t CIR1; /**< SIPI Channel Interrupt Register 1, offset: 0x2C */ 88 __IO uint32_t CTOR1; /**< SIPI Channel Timeout Register 1, offset: 0x30 */ 89 __I uint32_t CCRC1; /**< SIPI Channel CRC Register 1, offset: 0x34 */ 90 __IO uint32_t CAR1; /**< SIPI Channel Address Register 1, offset: 0x38 */ 91 __IO uint32_t CDR1; /**< SIPI Channel Data Register 1, offset: 0x3C */ 92 __IO uint32_t CCR2; /**< SIPI Channel Control Register 2, offset: 0x40 */ 93 __IO uint32_t CSR2; /**< SIPI Channel Status Register 2, offset: 0x44 */ 94 uint8_t RESERVED_2[4]; 95 __IO uint32_t CIR2; /**< SIPI Channel Interrupt Register 2, offset: 0x4C */ 96 __IO uint32_t CTOR2; /**< SIPI Channel Timeout Register 2, offset: 0x50 */ 97 __I uint32_t CCRC2; /**< SIPI Channel CRC Register 2, offset: 0x54 */ 98 __IO uint32_t CAR2; /**< SIPI Channel Address Register 2, offset: 0x58 */ 99 __IO uint32_t CDR2[SIPI_CDR2_COUNT]; /**< SIPI Channel Data Register 2, array offset: 0x5C, array step: 0x4 */ 100 __IO uint32_t CCR3; /**< SIPI Channel Control Register 3, offset: 0x7C */ 101 __IO uint32_t CSR3; /**< SIPI Channel Status Register 3, offset: 0x80 */ 102 uint8_t RESERVED_3[4]; 103 __IO uint32_t CIR3; /**< SIPI Channel Interrupt Register 3, offset: 0x88 */ 104 __IO uint32_t CTOR3; /**< SIPI Channel Timeout Register 3, offset: 0x8C */ 105 __I uint32_t CCRC3; /**< SIPI Channel CRC Register 3, offset: 0x90 */ 106 __IO uint32_t CAR3; /**< SIPI Channel Address Register 3, offset: 0x94 */ 107 __IO uint32_t CDR3; /**< SIPI Channel Data Register 3, offset: 0x98 */ 108 __IO uint32_t MCR; /**< SIPI Module Configuration Register, offset: 0x9C */ 109 __IO uint32_t SR; /**< SIPI Status Register, offset: 0xA0 */ 110 __IO uint32_t MAXCR; /**< SIPI Max Count Register, offset: 0xA4 */ 111 __IO uint32_t ARR; /**< SIPI Address Reload Register, offset: 0xA8 */ 112 __IO uint32_t ACR; /**< SIPI Address Count Register, offset: 0xAC */ 113 __IO uint32_t ERR; /**< SIPI Error Register, offset: 0xB0 */ 114 __I uint32_t DEBUGr; /**< SIPI Debug Register, offset: 0xB4, 'r' suffix has been added to avoid clash with DEBUG symbolic constant */ 115 __I uint32_t PMR; /**< SIPI Performance Monitor register, offset: 0xB8 */ 116 } SIPI_Type, *SIPI_MemMapPtr; 117 118 /** Number of instances of the SIPI module. */ 119 #define SIPI_INSTANCE_COUNT (2u) 120 121 /* SIPI - Peripheral instance base addresses */ 122 /** Peripheral SIPI_0 base address */ 123 #define IP_SIPI_0_BASE (0x40A20000u) 124 /** Peripheral SIPI_0 base pointer */ 125 #define IP_SIPI_0 ((SIPI_Type *)IP_SIPI_0_BASE) 126 /** Peripheral SIPI_1 base address */ 127 #define IP_SIPI_1_BASE (0x40A40000u) 128 /** Peripheral SIPI_1 base pointer */ 129 #define IP_SIPI_1 ((SIPI_Type *)IP_SIPI_1_BASE) 130 /** Array initializer of SIPI peripheral base addresses */ 131 #define IP_SIPI_BASE_ADDRS { IP_SIPI_0_BASE, IP_SIPI_1_BASE } 132 /** Array initializer of SIPI peripheral base pointers */ 133 #define IP_SIPI_BASE_PTRS { IP_SIPI_0, IP_SIPI_1 } 134 135 /* ---------------------------------------------------------------------------- 136 -- SIPI Register Masks 137 ---------------------------------------------------------------------------- */ 138 139 /*! 140 * @addtogroup SIPI_Register_Masks SIPI Register Masks 141 * @{ 142 */ 143 144 /*! @name CCR0 - SIPI Channel Control Register 0 */ 145 /*! @{ */ 146 147 #define SIPI_CCR0_DEN_MASK (0x1U) 148 #define SIPI_CCR0_DEN_SHIFT (0U) 149 #define SIPI_CCR0_DEN_WIDTH (1U) 150 #define SIPI_CCR0_DEN(x) (((uint32_t)(((uint32_t)(x)) << SIPI_CCR0_DEN_SHIFT)) & SIPI_CCR0_DEN_MASK) 151 152 #define SIPI_CCR0_WRT_MASK (0x2U) 153 #define SIPI_CCR0_WRT_SHIFT (1U) 154 #define SIPI_CCR0_WRT_WIDTH (1U) 155 #define SIPI_CCR0_WRT(x) (((uint32_t)(((uint32_t)(x)) << SIPI_CCR0_WRT_SHIFT)) & SIPI_CCR0_WRT_MASK) 156 157 #define SIPI_CCR0_RRT_MASK (0x4U) 158 #define SIPI_CCR0_RRT_SHIFT (2U) 159 #define SIPI_CCR0_RRT_WIDTH (1U) 160 #define SIPI_CCR0_RRT(x) (((uint32_t)(((uint32_t)(x)) << SIPI_CCR0_RRT_SHIFT)) & SIPI_CCR0_RRT_MASK) 161 162 #define SIPI_CCR0_IDT_MASK (0x8U) 163 #define SIPI_CCR0_IDT_SHIFT (3U) 164 #define SIPI_CCR0_IDT_WIDTH (1U) 165 #define SIPI_CCR0_IDT(x) (((uint32_t)(((uint32_t)(x)) << SIPI_CCR0_IDT_SHIFT)) & SIPI_CCR0_IDT_MASK) 166 167 #define SIPI_CCR0_CHEN_MASK (0x20U) 168 #define SIPI_CCR0_CHEN_SHIFT (5U) 169 #define SIPI_CCR0_CHEN_WIDTH (1U) 170 #define SIPI_CCR0_CHEN(x) (((uint32_t)(((uint32_t)(x)) << SIPI_CCR0_CHEN_SHIFT)) & SIPI_CCR0_CHEN_MASK) 171 172 #define SIPI_CCR0_WL_MASK (0xC0U) 173 #define SIPI_CCR0_WL_SHIFT (6U) 174 #define SIPI_CCR0_WL_WIDTH (2U) 175 #define SIPI_CCR0_WL(x) (((uint32_t)(((uint32_t)(x)) << SIPI_CCR0_WL_SHIFT)) & SIPI_CCR0_WL_MASK) 176 177 #define SIPI_CCR0_TC_MASK (0x10000U) 178 #define SIPI_CCR0_TC_SHIFT (16U) 179 #define SIPI_CCR0_TC_WIDTH (1U) 180 #define SIPI_CCR0_TC(x) (((uint32_t)(((uint32_t)(x)) << SIPI_CCR0_TC_SHIFT)) & SIPI_CCR0_TC_MASK) 181 /*! @} */ 182 183 /*! @name CSR0 - SIPI Channel Status Register 0 */ 184 /*! @{ */ 185 186 #define SIPI_CSR0_CB_MASK (0x4U) 187 #define SIPI_CSR0_CB_SHIFT (2U) 188 #define SIPI_CSR0_CB_WIDTH (1U) 189 #define SIPI_CSR0_CB(x) (((uint32_t)(((uint32_t)(x)) << SIPI_CSR0_CB_SHIFT)) & SIPI_CSR0_CB_MASK) 190 191 #define SIPI_CSR0_ACKR_MASK (0x8U) 192 #define SIPI_CSR0_ACKR_SHIFT (3U) 193 #define SIPI_CSR0_ACKR_WIDTH (1U) 194 #define SIPI_CSR0_ACKR(x) (((uint32_t)(((uint32_t)(x)) << SIPI_CSR0_ACKR_SHIFT)) & SIPI_CSR0_ACKR_MASK) 195 196 #define SIPI_CSR0_TID_MASK (0x70U) 197 #define SIPI_CSR0_TID_SHIFT (4U) 198 #define SIPI_CSR0_TID_WIDTH (3U) 199 #define SIPI_CSR0_TID(x) (((uint32_t)(((uint32_t)(x)) << SIPI_CSR0_TID_SHIFT)) & SIPI_CSR0_TID_MASK) 200 201 #define SIPI_CSR0_RAR_MASK (0x80U) 202 #define SIPI_CSR0_RAR_SHIFT (7U) 203 #define SIPI_CSR0_RAR_WIDTH (1U) 204 #define SIPI_CSR0_RAR(x) (((uint32_t)(((uint32_t)(x)) << SIPI_CSR0_RAR_SHIFT)) & SIPI_CSR0_RAR_MASK) 205 206 #define SIPI_CSR0_READ_RX_MASK (0x100U) 207 #define SIPI_CSR0_READ_RX_SHIFT (8U) 208 #define SIPI_CSR0_READ_RX_WIDTH (1U) 209 #define SIPI_CSR0_READ_RX(x) (((uint32_t)(((uint32_t)(x)) << SIPI_CSR0_READ_RX_SHIFT)) & SIPI_CSR0_READ_RX_MASK) 210 211 #define SIPI_CSR0_WRITE_RX_MASK (0x200U) 212 #define SIPI_CSR0_WRITE_RX_SHIFT (9U) 213 #define SIPI_CSR0_WRITE_RX_WIDTH (1U) 214 #define SIPI_CSR0_WRITE_RX(x) (((uint32_t)(((uint32_t)(x)) << SIPI_CSR0_WRITE_RX_SHIFT)) & SIPI_CSR0_WRITE_RX_MASK) 215 /*! @} */ 216 217 /*! @name CIR0 - SIPI Channel Interrupt Register 0 */ 218 /*! @{ */ 219 220 #define SIPI_CIR0_ACKIE_MASK (0x1U) 221 #define SIPI_CIR0_ACKIE_SHIFT (0U) 222 #define SIPI_CIR0_ACKIE_WIDTH (1U) 223 #define SIPI_CIR0_ACKIE(x) (((uint32_t)(((uint32_t)(x)) << SIPI_CIR0_ACKIE_SHIFT)) & SIPI_CIR0_ACKIE_MASK) 224 225 #define SIPI_CIR0_TIDIE_MASK (0x2U) 226 #define SIPI_CIR0_TIDIE_SHIFT (1U) 227 #define SIPI_CIR0_TIDIE_WIDTH (1U) 228 #define SIPI_CIR0_TIDIE(x) (((uint32_t)(((uint32_t)(x)) << SIPI_CIR0_TIDIE_SHIFT)) & SIPI_CIR0_TIDIE_MASK) 229 230 #define SIPI_CIR0_TOIE_MASK (0x4U) 231 #define SIPI_CIR0_TOIE_SHIFT (2U) 232 #define SIPI_CIR0_TOIE_WIDTH (1U) 233 #define SIPI_CIR0_TOIE(x) (((uint32_t)(((uint32_t)(x)) << SIPI_CIR0_TOIE_SHIFT)) & SIPI_CIR0_TOIE_MASK) 234 235 #define SIPI_CIR0_TCIE_MASK (0x8U) 236 #define SIPI_CIR0_TCIE_SHIFT (3U) 237 #define SIPI_CIR0_TCIE_WIDTH (1U) 238 #define SIPI_CIR0_TCIE(x) (((uint32_t)(((uint32_t)(x)) << SIPI_CIR0_TCIE_SHIFT)) & SIPI_CIR0_TCIE_MASK) 239 240 #define SIPI_CIR0_RAIE_MASK (0x10U) 241 #define SIPI_CIR0_RAIE_SHIFT (4U) 242 #define SIPI_CIR0_RAIE_WIDTH (1U) 243 #define SIPI_CIR0_RAIE(x) (((uint32_t)(((uint32_t)(x)) << SIPI_CIR0_RAIE_SHIFT)) & SIPI_CIR0_RAIE_MASK) 244 245 #define SIPI_CIR0_WAIE_MASK (0x20U) 246 #define SIPI_CIR0_WAIE_SHIFT (5U) 247 #define SIPI_CIR0_WAIE_WIDTH (1U) 248 #define SIPI_CIR0_WAIE(x) (((uint32_t)(((uint32_t)(x)) << SIPI_CIR0_WAIE_SHIFT)) & SIPI_CIR0_WAIE_MASK) 249 /*! @} */ 250 251 /*! @name CTOR0 - SIPI Channel Timeout Register 0 */ 252 /*! @{ */ 253 254 #define SIPI_CTOR0_TOR_MASK (0xFFFFFFFFU) 255 #define SIPI_CTOR0_TOR_SHIFT (0U) 256 #define SIPI_CTOR0_TOR_WIDTH (32U) 257 #define SIPI_CTOR0_TOR(x) (((uint32_t)(((uint32_t)(x)) << SIPI_CTOR0_TOR_SHIFT)) & SIPI_CTOR0_TOR_MASK) 258 /*! @} */ 259 260 /*! @name CCRC0 - SIPI Channel CRC Register 0 */ 261 /*! @{ */ 262 263 #define SIPI_CCRC0_CRCT_MASK (0xFFFFU) 264 #define SIPI_CCRC0_CRCT_SHIFT (0U) 265 #define SIPI_CCRC0_CRCT_WIDTH (16U) 266 #define SIPI_CCRC0_CRCT(x) (((uint32_t)(((uint32_t)(x)) << SIPI_CCRC0_CRCT_SHIFT)) & SIPI_CCRC0_CRCT_MASK) 267 268 #define SIPI_CCRC0_CRCI_MASK (0xFFFF0000U) 269 #define SIPI_CCRC0_CRCI_SHIFT (16U) 270 #define SIPI_CCRC0_CRCI_WIDTH (16U) 271 #define SIPI_CCRC0_CRCI(x) (((uint32_t)(((uint32_t)(x)) << SIPI_CCRC0_CRCI_SHIFT)) & SIPI_CCRC0_CRCI_MASK) 272 /*! @} */ 273 274 /*! @name CAR0 - SIPI Channel Address Register 0 */ 275 /*! @{ */ 276 277 #define SIPI_CAR0_CAR_MASK (0xFFFFFFFFU) 278 #define SIPI_CAR0_CAR_SHIFT (0U) 279 #define SIPI_CAR0_CAR_WIDTH (32U) 280 #define SIPI_CAR0_CAR(x) (((uint32_t)(((uint32_t)(x)) << SIPI_CAR0_CAR_SHIFT)) & SIPI_CAR0_CAR_MASK) 281 /*! @} */ 282 283 /*! @name CDR0 - SIPI Channel Data Register 0 */ 284 /*! @{ */ 285 286 #define SIPI_CDR0_CDR_MASK (0xFFFFFFFFU) 287 #define SIPI_CDR0_CDR_SHIFT (0U) 288 #define SIPI_CDR0_CDR_WIDTH (32U) 289 #define SIPI_CDR0_CDR(x) (((uint32_t)(((uint32_t)(x)) << SIPI_CDR0_CDR_SHIFT)) & SIPI_CDR0_CDR_MASK) 290 /*! @} */ 291 292 /*! @name CCR1 - SIPI Channel Control Register 1 */ 293 /*! @{ */ 294 295 #define SIPI_CCR1_DEN_MASK (0x1U) 296 #define SIPI_CCR1_DEN_SHIFT (0U) 297 #define SIPI_CCR1_DEN_WIDTH (1U) 298 #define SIPI_CCR1_DEN(x) (((uint32_t)(((uint32_t)(x)) << SIPI_CCR1_DEN_SHIFT)) & SIPI_CCR1_DEN_MASK) 299 300 #define SIPI_CCR1_WRT_MASK (0x2U) 301 #define SIPI_CCR1_WRT_SHIFT (1U) 302 #define SIPI_CCR1_WRT_WIDTH (1U) 303 #define SIPI_CCR1_WRT(x) (((uint32_t)(((uint32_t)(x)) << SIPI_CCR1_WRT_SHIFT)) & SIPI_CCR1_WRT_MASK) 304 305 #define SIPI_CCR1_RRT_MASK (0x4U) 306 #define SIPI_CCR1_RRT_SHIFT (2U) 307 #define SIPI_CCR1_RRT_WIDTH (1U) 308 #define SIPI_CCR1_RRT(x) (((uint32_t)(((uint32_t)(x)) << SIPI_CCR1_RRT_SHIFT)) & SIPI_CCR1_RRT_MASK) 309 310 #define SIPI_CCR1_IDT_MASK (0x8U) 311 #define SIPI_CCR1_IDT_SHIFT (3U) 312 #define SIPI_CCR1_IDT_WIDTH (1U) 313 #define SIPI_CCR1_IDT(x) (((uint32_t)(((uint32_t)(x)) << SIPI_CCR1_IDT_SHIFT)) & SIPI_CCR1_IDT_MASK) 314 315 #define SIPI_CCR1_CHEN_MASK (0x20U) 316 #define SIPI_CCR1_CHEN_SHIFT (5U) 317 #define SIPI_CCR1_CHEN_WIDTH (1U) 318 #define SIPI_CCR1_CHEN(x) (((uint32_t)(((uint32_t)(x)) << SIPI_CCR1_CHEN_SHIFT)) & SIPI_CCR1_CHEN_MASK) 319 320 #define SIPI_CCR1_WL_MASK (0xC0U) 321 #define SIPI_CCR1_WL_SHIFT (6U) 322 #define SIPI_CCR1_WL_WIDTH (2U) 323 #define SIPI_CCR1_WL(x) (((uint32_t)(((uint32_t)(x)) << SIPI_CCR1_WL_SHIFT)) & SIPI_CCR1_WL_MASK) 324 325 #define SIPI_CCR1_TC_MASK (0x10000U) 326 #define SIPI_CCR1_TC_SHIFT (16U) 327 #define SIPI_CCR1_TC_WIDTH (1U) 328 #define SIPI_CCR1_TC(x) (((uint32_t)(((uint32_t)(x)) << SIPI_CCR1_TC_SHIFT)) & SIPI_CCR1_TC_MASK) 329 /*! @} */ 330 331 /*! @name CSR1 - SIPI Channel Status Register 1 */ 332 /*! @{ */ 333 334 #define SIPI_CSR1_CB_MASK (0x4U) 335 #define SIPI_CSR1_CB_SHIFT (2U) 336 #define SIPI_CSR1_CB_WIDTH (1U) 337 #define SIPI_CSR1_CB(x) (((uint32_t)(((uint32_t)(x)) << SIPI_CSR1_CB_SHIFT)) & SIPI_CSR1_CB_MASK) 338 339 #define SIPI_CSR1_ACKR_MASK (0x8U) 340 #define SIPI_CSR1_ACKR_SHIFT (3U) 341 #define SIPI_CSR1_ACKR_WIDTH (1U) 342 #define SIPI_CSR1_ACKR(x) (((uint32_t)(((uint32_t)(x)) << SIPI_CSR1_ACKR_SHIFT)) & SIPI_CSR1_ACKR_MASK) 343 344 #define SIPI_CSR1_TID_MASK (0x70U) 345 #define SIPI_CSR1_TID_SHIFT (4U) 346 #define SIPI_CSR1_TID_WIDTH (3U) 347 #define SIPI_CSR1_TID(x) (((uint32_t)(((uint32_t)(x)) << SIPI_CSR1_TID_SHIFT)) & SIPI_CSR1_TID_MASK) 348 349 #define SIPI_CSR1_RAR_MASK (0x80U) 350 #define SIPI_CSR1_RAR_SHIFT (7U) 351 #define SIPI_CSR1_RAR_WIDTH (1U) 352 #define SIPI_CSR1_RAR(x) (((uint32_t)(((uint32_t)(x)) << SIPI_CSR1_RAR_SHIFT)) & SIPI_CSR1_RAR_MASK) 353 354 #define SIPI_CSR1_READ_RX_MASK (0x100U) 355 #define SIPI_CSR1_READ_RX_SHIFT (8U) 356 #define SIPI_CSR1_READ_RX_WIDTH (1U) 357 #define SIPI_CSR1_READ_RX(x) (((uint32_t)(((uint32_t)(x)) << SIPI_CSR1_READ_RX_SHIFT)) & SIPI_CSR1_READ_RX_MASK) 358 359 #define SIPI_CSR1_WRITE_RX_MASK (0x200U) 360 #define SIPI_CSR1_WRITE_RX_SHIFT (9U) 361 #define SIPI_CSR1_WRITE_RX_WIDTH (1U) 362 #define SIPI_CSR1_WRITE_RX(x) (((uint32_t)(((uint32_t)(x)) << SIPI_CSR1_WRITE_RX_SHIFT)) & SIPI_CSR1_WRITE_RX_MASK) 363 /*! @} */ 364 365 /*! @name CIR1 - SIPI Channel Interrupt Register 1 */ 366 /*! @{ */ 367 368 #define SIPI_CIR1_ACKIE_MASK (0x1U) 369 #define SIPI_CIR1_ACKIE_SHIFT (0U) 370 #define SIPI_CIR1_ACKIE_WIDTH (1U) 371 #define SIPI_CIR1_ACKIE(x) (((uint32_t)(((uint32_t)(x)) << SIPI_CIR1_ACKIE_SHIFT)) & SIPI_CIR1_ACKIE_MASK) 372 373 #define SIPI_CIR1_TIDIE_MASK (0x2U) 374 #define SIPI_CIR1_TIDIE_SHIFT (1U) 375 #define SIPI_CIR1_TIDIE_WIDTH (1U) 376 #define SIPI_CIR1_TIDIE(x) (((uint32_t)(((uint32_t)(x)) << SIPI_CIR1_TIDIE_SHIFT)) & SIPI_CIR1_TIDIE_MASK) 377 378 #define SIPI_CIR1_TOIE_MASK (0x4U) 379 #define SIPI_CIR1_TOIE_SHIFT (2U) 380 #define SIPI_CIR1_TOIE_WIDTH (1U) 381 #define SIPI_CIR1_TOIE(x) (((uint32_t)(((uint32_t)(x)) << SIPI_CIR1_TOIE_SHIFT)) & SIPI_CIR1_TOIE_MASK) 382 383 #define SIPI_CIR1_TCIE_MASK (0x8U) 384 #define SIPI_CIR1_TCIE_SHIFT (3U) 385 #define SIPI_CIR1_TCIE_WIDTH (1U) 386 #define SIPI_CIR1_TCIE(x) (((uint32_t)(((uint32_t)(x)) << SIPI_CIR1_TCIE_SHIFT)) & SIPI_CIR1_TCIE_MASK) 387 388 #define SIPI_CIR1_RAIE_MASK (0x10U) 389 #define SIPI_CIR1_RAIE_SHIFT (4U) 390 #define SIPI_CIR1_RAIE_WIDTH (1U) 391 #define SIPI_CIR1_RAIE(x) (((uint32_t)(((uint32_t)(x)) << SIPI_CIR1_RAIE_SHIFT)) & SIPI_CIR1_RAIE_MASK) 392 393 #define SIPI_CIR1_WAIE_MASK (0x20U) 394 #define SIPI_CIR1_WAIE_SHIFT (5U) 395 #define SIPI_CIR1_WAIE_WIDTH (1U) 396 #define SIPI_CIR1_WAIE(x) (((uint32_t)(((uint32_t)(x)) << SIPI_CIR1_WAIE_SHIFT)) & SIPI_CIR1_WAIE_MASK) 397 /*! @} */ 398 399 /*! @name CTOR1 - SIPI Channel Timeout Register 1 */ 400 /*! @{ */ 401 402 #define SIPI_CTOR1_TOR_MASK (0xFFFFFFFFU) 403 #define SIPI_CTOR1_TOR_SHIFT (0U) 404 #define SIPI_CTOR1_TOR_WIDTH (32U) 405 #define SIPI_CTOR1_TOR(x) (((uint32_t)(((uint32_t)(x)) << SIPI_CTOR1_TOR_SHIFT)) & SIPI_CTOR1_TOR_MASK) 406 /*! @} */ 407 408 /*! @name CCRC1 - SIPI Channel CRC Register 1 */ 409 /*! @{ */ 410 411 #define SIPI_CCRC1_CRCT_MASK (0xFFFFU) 412 #define SIPI_CCRC1_CRCT_SHIFT (0U) 413 #define SIPI_CCRC1_CRCT_WIDTH (16U) 414 #define SIPI_CCRC1_CRCT(x) (((uint32_t)(((uint32_t)(x)) << SIPI_CCRC1_CRCT_SHIFT)) & SIPI_CCRC1_CRCT_MASK) 415 416 #define SIPI_CCRC1_CRCI_MASK (0xFFFF0000U) 417 #define SIPI_CCRC1_CRCI_SHIFT (16U) 418 #define SIPI_CCRC1_CRCI_WIDTH (16U) 419 #define SIPI_CCRC1_CRCI(x) (((uint32_t)(((uint32_t)(x)) << SIPI_CCRC1_CRCI_SHIFT)) & SIPI_CCRC1_CRCI_MASK) 420 /*! @} */ 421 422 /*! @name CAR1 - SIPI Channel Address Register 1 */ 423 /*! @{ */ 424 425 #define SIPI_CAR1_CAR_MASK (0xFFFFFFFFU) 426 #define SIPI_CAR1_CAR_SHIFT (0U) 427 #define SIPI_CAR1_CAR_WIDTH (32U) 428 #define SIPI_CAR1_CAR(x) (((uint32_t)(((uint32_t)(x)) << SIPI_CAR1_CAR_SHIFT)) & SIPI_CAR1_CAR_MASK) 429 /*! @} */ 430 431 /*! @name CDR1 - SIPI Channel Data Register 1 */ 432 /*! @{ */ 433 434 #define SIPI_CDR1_CDR_MASK (0xFFFFFFFFU) 435 #define SIPI_CDR1_CDR_SHIFT (0U) 436 #define SIPI_CDR1_CDR_WIDTH (32U) 437 #define SIPI_CDR1_CDR(x) (((uint32_t)(((uint32_t)(x)) << SIPI_CDR1_CDR_SHIFT)) & SIPI_CDR1_CDR_MASK) 438 /*! @} */ 439 440 /*! @name CCR2 - SIPI Channel Control Register 2 */ 441 /*! @{ */ 442 443 #define SIPI_CCR2_DEN_MASK (0x1U) 444 #define SIPI_CCR2_DEN_SHIFT (0U) 445 #define SIPI_CCR2_DEN_WIDTH (1U) 446 #define SIPI_CCR2_DEN(x) (((uint32_t)(((uint32_t)(x)) << SIPI_CCR2_DEN_SHIFT)) & SIPI_CCR2_DEN_MASK) 447 448 #define SIPI_CCR2_WRT_MASK (0x2U) 449 #define SIPI_CCR2_WRT_SHIFT (1U) 450 #define SIPI_CCR2_WRT_WIDTH (1U) 451 #define SIPI_CCR2_WRT(x) (((uint32_t)(((uint32_t)(x)) << SIPI_CCR2_WRT_SHIFT)) & SIPI_CCR2_WRT_MASK) 452 453 #define SIPI_CCR2_RRT_MASK (0x4U) 454 #define SIPI_CCR2_RRT_SHIFT (2U) 455 #define SIPI_CCR2_RRT_WIDTH (1U) 456 #define SIPI_CCR2_RRT(x) (((uint32_t)(((uint32_t)(x)) << SIPI_CCR2_RRT_SHIFT)) & SIPI_CCR2_RRT_MASK) 457 458 #define SIPI_CCR2_IDT_MASK (0x8U) 459 #define SIPI_CCR2_IDT_SHIFT (3U) 460 #define SIPI_CCR2_IDT_WIDTH (1U) 461 #define SIPI_CCR2_IDT(x) (((uint32_t)(((uint32_t)(x)) << SIPI_CCR2_IDT_SHIFT)) & SIPI_CCR2_IDT_MASK) 462 463 #define SIPI_CCR2_ST_MASK (0x10U) 464 #define SIPI_CCR2_ST_SHIFT (4U) 465 #define SIPI_CCR2_ST_WIDTH (1U) 466 #define SIPI_CCR2_ST(x) (((uint32_t)(((uint32_t)(x)) << SIPI_CCR2_ST_SHIFT)) & SIPI_CCR2_ST_MASK) 467 468 #define SIPI_CCR2_CHEN_MASK (0x20U) 469 #define SIPI_CCR2_CHEN_SHIFT (5U) 470 #define SIPI_CCR2_CHEN_WIDTH (1U) 471 #define SIPI_CCR2_CHEN(x) (((uint32_t)(((uint32_t)(x)) << SIPI_CCR2_CHEN_SHIFT)) & SIPI_CCR2_CHEN_MASK) 472 473 #define SIPI_CCR2_WL_MASK (0xC0U) 474 #define SIPI_CCR2_WL_SHIFT (6U) 475 #define SIPI_CCR2_WL_WIDTH (2U) 476 #define SIPI_CCR2_WL(x) (((uint32_t)(((uint32_t)(x)) << SIPI_CCR2_WL_SHIFT)) & SIPI_CCR2_WL_MASK) 477 478 #define SIPI_CCR2_TC_MASK (0x10000U) 479 #define SIPI_CCR2_TC_SHIFT (16U) 480 #define SIPI_CCR2_TC_WIDTH (1U) 481 #define SIPI_CCR2_TC(x) (((uint32_t)(((uint32_t)(x)) << SIPI_CCR2_TC_SHIFT)) & SIPI_CCR2_TC_MASK) 482 /*! @} */ 483 484 /*! @name CSR2 - SIPI Channel Status Register 2 */ 485 /*! @{ */ 486 487 #define SIPI_CSR2_CB_MASK (0x4U) 488 #define SIPI_CSR2_CB_SHIFT (2U) 489 #define SIPI_CSR2_CB_WIDTH (1U) 490 #define SIPI_CSR2_CB(x) (((uint32_t)(((uint32_t)(x)) << SIPI_CSR2_CB_SHIFT)) & SIPI_CSR2_CB_MASK) 491 492 #define SIPI_CSR2_ACKR_MASK (0x8U) 493 #define SIPI_CSR2_ACKR_SHIFT (3U) 494 #define SIPI_CSR2_ACKR_WIDTH (1U) 495 #define SIPI_CSR2_ACKR(x) (((uint32_t)(((uint32_t)(x)) << SIPI_CSR2_ACKR_SHIFT)) & SIPI_CSR2_ACKR_MASK) 496 497 #define SIPI_CSR2_TID_MASK (0x70U) 498 #define SIPI_CSR2_TID_SHIFT (4U) 499 #define SIPI_CSR2_TID_WIDTH (3U) 500 #define SIPI_CSR2_TID(x) (((uint32_t)(((uint32_t)(x)) << SIPI_CSR2_TID_SHIFT)) & SIPI_CSR2_TID_MASK) 501 502 #define SIPI_CSR2_RAR_MASK (0x80U) 503 #define SIPI_CSR2_RAR_SHIFT (7U) 504 #define SIPI_CSR2_RAR_WIDTH (1U) 505 #define SIPI_CSR2_RAR(x) (((uint32_t)(((uint32_t)(x)) << SIPI_CSR2_RAR_SHIFT)) & SIPI_CSR2_RAR_MASK) 506 507 #define SIPI_CSR2_READ_RX_MASK (0x100U) 508 #define SIPI_CSR2_READ_RX_SHIFT (8U) 509 #define SIPI_CSR2_READ_RX_WIDTH (1U) 510 #define SIPI_CSR2_READ_RX(x) (((uint32_t)(((uint32_t)(x)) << SIPI_CSR2_READ_RX_SHIFT)) & SIPI_CSR2_READ_RX_MASK) 511 512 #define SIPI_CSR2_WRITE_RX_MASK (0x200U) 513 #define SIPI_CSR2_WRITE_RX_SHIFT (9U) 514 #define SIPI_CSR2_WRITE_RX_WIDTH (1U) 515 #define SIPI_CSR2_WRITE_RX(x) (((uint32_t)(((uint32_t)(x)) << SIPI_CSR2_WRITE_RX_SHIFT)) & SIPI_CSR2_WRITE_RX_MASK) 516 517 #define SIPI_CSR2_WRITE_STR_RX_MASK (0x400U) 518 #define SIPI_CSR2_WRITE_STR_RX_SHIFT (10U) 519 #define SIPI_CSR2_WRITE_STR_RX_WIDTH (1U) 520 #define SIPI_CSR2_WRITE_STR_RX(x) (((uint32_t)(((uint32_t)(x)) << SIPI_CSR2_WRITE_STR_RX_SHIFT)) & SIPI_CSR2_WRITE_STR_RX_MASK) 521 /*! @} */ 522 523 /*! @name CIR2 - SIPI Channel Interrupt Register 2 */ 524 /*! @{ */ 525 526 #define SIPI_CIR2_ACKIE_MASK (0x1U) 527 #define SIPI_CIR2_ACKIE_SHIFT (0U) 528 #define SIPI_CIR2_ACKIE_WIDTH (1U) 529 #define SIPI_CIR2_ACKIE(x) (((uint32_t)(((uint32_t)(x)) << SIPI_CIR2_ACKIE_SHIFT)) & SIPI_CIR2_ACKIE_MASK) 530 531 #define SIPI_CIR2_TIDIE_MASK (0x2U) 532 #define SIPI_CIR2_TIDIE_SHIFT (1U) 533 #define SIPI_CIR2_TIDIE_WIDTH (1U) 534 #define SIPI_CIR2_TIDIE(x) (((uint32_t)(((uint32_t)(x)) << SIPI_CIR2_TIDIE_SHIFT)) & SIPI_CIR2_TIDIE_MASK) 535 536 #define SIPI_CIR2_TOIE_MASK (0x4U) 537 #define SIPI_CIR2_TOIE_SHIFT (2U) 538 #define SIPI_CIR2_TOIE_WIDTH (1U) 539 #define SIPI_CIR2_TOIE(x) (((uint32_t)(((uint32_t)(x)) << SIPI_CIR2_TOIE_SHIFT)) & SIPI_CIR2_TOIE_MASK) 540 541 #define SIPI_CIR2_TCIE_MASK (0x8U) 542 #define SIPI_CIR2_TCIE_SHIFT (3U) 543 #define SIPI_CIR2_TCIE_WIDTH (1U) 544 #define SIPI_CIR2_TCIE(x) (((uint32_t)(((uint32_t)(x)) << SIPI_CIR2_TCIE_SHIFT)) & SIPI_CIR2_TCIE_MASK) 545 546 #define SIPI_CIR2_RAIE_MASK (0x10U) 547 #define SIPI_CIR2_RAIE_SHIFT (4U) 548 #define SIPI_CIR2_RAIE_WIDTH (1U) 549 #define SIPI_CIR2_RAIE(x) (((uint32_t)(((uint32_t)(x)) << SIPI_CIR2_RAIE_SHIFT)) & SIPI_CIR2_RAIE_MASK) 550 551 #define SIPI_CIR2_WAIE_MASK (0x20U) 552 #define SIPI_CIR2_WAIE_SHIFT (5U) 553 #define SIPI_CIR2_WAIE_WIDTH (1U) 554 #define SIPI_CIR2_WAIE(x) (((uint32_t)(((uint32_t)(x)) << SIPI_CIR2_WAIE_SHIFT)) & SIPI_CIR2_WAIE_MASK) 555 /*! @} */ 556 557 /*! @name CTOR2 - SIPI Channel Timeout Register 2 */ 558 /*! @{ */ 559 560 #define SIPI_CTOR2_TOR_MASK (0xFFFFFFFFU) 561 #define SIPI_CTOR2_TOR_SHIFT (0U) 562 #define SIPI_CTOR2_TOR_WIDTH (32U) 563 #define SIPI_CTOR2_TOR(x) (((uint32_t)(((uint32_t)(x)) << SIPI_CTOR2_TOR_SHIFT)) & SIPI_CTOR2_TOR_MASK) 564 /*! @} */ 565 566 /*! @name CCRC2 - SIPI Channel CRC Register 2 */ 567 /*! @{ */ 568 569 #define SIPI_CCRC2_CRCT_MASK (0xFFFFU) 570 #define SIPI_CCRC2_CRCT_SHIFT (0U) 571 #define SIPI_CCRC2_CRCT_WIDTH (16U) 572 #define SIPI_CCRC2_CRCT(x) (((uint32_t)(((uint32_t)(x)) << SIPI_CCRC2_CRCT_SHIFT)) & SIPI_CCRC2_CRCT_MASK) 573 574 #define SIPI_CCRC2_CRCI_MASK (0xFFFF0000U) 575 #define SIPI_CCRC2_CRCI_SHIFT (16U) 576 #define SIPI_CCRC2_CRCI_WIDTH (16U) 577 #define SIPI_CCRC2_CRCI(x) (((uint32_t)(((uint32_t)(x)) << SIPI_CCRC2_CRCI_SHIFT)) & SIPI_CCRC2_CRCI_MASK) 578 /*! @} */ 579 580 /*! @name CAR2 - SIPI Channel Address Register 2 */ 581 /*! @{ */ 582 583 #define SIPI_CAR2_CAR_MASK (0xFFFFFFFFU) 584 #define SIPI_CAR2_CAR_SHIFT (0U) 585 #define SIPI_CAR2_CAR_WIDTH (32U) 586 #define SIPI_CAR2_CAR(x) (((uint32_t)(((uint32_t)(x)) << SIPI_CAR2_CAR_SHIFT)) & SIPI_CAR2_CAR_MASK) 587 /*! @} */ 588 589 /*! @name CDR2 - SIPI Channel Data Register 2 */ 590 /*! @{ */ 591 592 #define SIPI_CDR2_CDR2_MASK (0xFFFFFFFFU) 593 #define SIPI_CDR2_CDR2_SHIFT (0U) 594 #define SIPI_CDR2_CDR2_WIDTH (32U) 595 #define SIPI_CDR2_CDR2(x) (((uint32_t)(((uint32_t)(x)) << SIPI_CDR2_CDR2_SHIFT)) & SIPI_CDR2_CDR2_MASK) 596 /*! @} */ 597 598 /*! @name CCR3 - SIPI Channel Control Register 3 */ 599 /*! @{ */ 600 601 #define SIPI_CCR3_DEN_MASK (0x1U) 602 #define SIPI_CCR3_DEN_SHIFT (0U) 603 #define SIPI_CCR3_DEN_WIDTH (1U) 604 #define SIPI_CCR3_DEN(x) (((uint32_t)(((uint32_t)(x)) << SIPI_CCR3_DEN_SHIFT)) & SIPI_CCR3_DEN_MASK) 605 606 #define SIPI_CCR3_WRT_MASK (0x2U) 607 #define SIPI_CCR3_WRT_SHIFT (1U) 608 #define SIPI_CCR3_WRT_WIDTH (1U) 609 #define SIPI_CCR3_WRT(x) (((uint32_t)(((uint32_t)(x)) << SIPI_CCR3_WRT_SHIFT)) & SIPI_CCR3_WRT_MASK) 610 611 #define SIPI_CCR3_RRT_MASK (0x4U) 612 #define SIPI_CCR3_RRT_SHIFT (2U) 613 #define SIPI_CCR3_RRT_WIDTH (1U) 614 #define SIPI_CCR3_RRT(x) (((uint32_t)(((uint32_t)(x)) << SIPI_CCR3_RRT_SHIFT)) & SIPI_CCR3_RRT_MASK) 615 616 #define SIPI_CCR3_IDT_MASK (0x8U) 617 #define SIPI_CCR3_IDT_SHIFT (3U) 618 #define SIPI_CCR3_IDT_WIDTH (1U) 619 #define SIPI_CCR3_IDT(x) (((uint32_t)(((uint32_t)(x)) << SIPI_CCR3_IDT_SHIFT)) & SIPI_CCR3_IDT_MASK) 620 621 #define SIPI_CCR3_CHEN_MASK (0x20U) 622 #define SIPI_CCR3_CHEN_SHIFT (5U) 623 #define SIPI_CCR3_CHEN_WIDTH (1U) 624 #define SIPI_CCR3_CHEN(x) (((uint32_t)(((uint32_t)(x)) << SIPI_CCR3_CHEN_SHIFT)) & SIPI_CCR3_CHEN_MASK) 625 626 #define SIPI_CCR3_WL_MASK (0xC0U) 627 #define SIPI_CCR3_WL_SHIFT (6U) 628 #define SIPI_CCR3_WL_WIDTH (2U) 629 #define SIPI_CCR3_WL(x) (((uint32_t)(((uint32_t)(x)) << SIPI_CCR3_WL_SHIFT)) & SIPI_CCR3_WL_MASK) 630 631 #define SIPI_CCR3_TC_MASK (0x10000U) 632 #define SIPI_CCR3_TC_SHIFT (16U) 633 #define SIPI_CCR3_TC_WIDTH (1U) 634 #define SIPI_CCR3_TC(x) (((uint32_t)(((uint32_t)(x)) << SIPI_CCR3_TC_SHIFT)) & SIPI_CCR3_TC_MASK) 635 /*! @} */ 636 637 /*! @name CSR3 - SIPI Channel Status Register 3 */ 638 /*! @{ */ 639 640 #define SIPI_CSR3_CB_MASK (0x4U) 641 #define SIPI_CSR3_CB_SHIFT (2U) 642 #define SIPI_CSR3_CB_WIDTH (1U) 643 #define SIPI_CSR3_CB(x) (((uint32_t)(((uint32_t)(x)) << SIPI_CSR3_CB_SHIFT)) & SIPI_CSR3_CB_MASK) 644 645 #define SIPI_CSR3_ACKR_MASK (0x8U) 646 #define SIPI_CSR3_ACKR_SHIFT (3U) 647 #define SIPI_CSR3_ACKR_WIDTH (1U) 648 #define SIPI_CSR3_ACKR(x) (((uint32_t)(((uint32_t)(x)) << SIPI_CSR3_ACKR_SHIFT)) & SIPI_CSR3_ACKR_MASK) 649 650 #define SIPI_CSR3_TID_MASK (0x70U) 651 #define SIPI_CSR3_TID_SHIFT (4U) 652 #define SIPI_CSR3_TID_WIDTH (3U) 653 #define SIPI_CSR3_TID(x) (((uint32_t)(((uint32_t)(x)) << SIPI_CSR3_TID_SHIFT)) & SIPI_CSR3_TID_MASK) 654 655 #define SIPI_CSR3_RAR_MASK (0x80U) 656 #define SIPI_CSR3_RAR_SHIFT (7U) 657 #define SIPI_CSR3_RAR_WIDTH (1U) 658 #define SIPI_CSR3_RAR(x) (((uint32_t)(((uint32_t)(x)) << SIPI_CSR3_RAR_SHIFT)) & SIPI_CSR3_RAR_MASK) 659 660 #define SIPI_CSR3_READ_RX_MASK (0x100U) 661 #define SIPI_CSR3_READ_RX_SHIFT (8U) 662 #define SIPI_CSR3_READ_RX_WIDTH (1U) 663 #define SIPI_CSR3_READ_RX(x) (((uint32_t)(((uint32_t)(x)) << SIPI_CSR3_READ_RX_SHIFT)) & SIPI_CSR3_READ_RX_MASK) 664 665 #define SIPI_CSR3_WRITE_RX_MASK (0x200U) 666 #define SIPI_CSR3_WRITE_RX_SHIFT (9U) 667 #define SIPI_CSR3_WRITE_RX_WIDTH (1U) 668 #define SIPI_CSR3_WRITE_RX(x) (((uint32_t)(((uint32_t)(x)) << SIPI_CSR3_WRITE_RX_SHIFT)) & SIPI_CSR3_WRITE_RX_MASK) 669 /*! @} */ 670 671 /*! @name CIR3 - SIPI Channel Interrupt Register 3 */ 672 /*! @{ */ 673 674 #define SIPI_CIR3_ACKIE_MASK (0x1U) 675 #define SIPI_CIR3_ACKIE_SHIFT (0U) 676 #define SIPI_CIR3_ACKIE_WIDTH (1U) 677 #define SIPI_CIR3_ACKIE(x) (((uint32_t)(((uint32_t)(x)) << SIPI_CIR3_ACKIE_SHIFT)) & SIPI_CIR3_ACKIE_MASK) 678 679 #define SIPI_CIR3_TIDIE_MASK (0x2U) 680 #define SIPI_CIR3_TIDIE_SHIFT (1U) 681 #define SIPI_CIR3_TIDIE_WIDTH (1U) 682 #define SIPI_CIR3_TIDIE(x) (((uint32_t)(((uint32_t)(x)) << SIPI_CIR3_TIDIE_SHIFT)) & SIPI_CIR3_TIDIE_MASK) 683 684 #define SIPI_CIR3_TOIE_MASK (0x4U) 685 #define SIPI_CIR3_TOIE_SHIFT (2U) 686 #define SIPI_CIR3_TOIE_WIDTH (1U) 687 #define SIPI_CIR3_TOIE(x) (((uint32_t)(((uint32_t)(x)) << SIPI_CIR3_TOIE_SHIFT)) & SIPI_CIR3_TOIE_MASK) 688 689 #define SIPI_CIR3_TCIE_MASK (0x8U) 690 #define SIPI_CIR3_TCIE_SHIFT (3U) 691 #define SIPI_CIR3_TCIE_WIDTH (1U) 692 #define SIPI_CIR3_TCIE(x) (((uint32_t)(((uint32_t)(x)) << SIPI_CIR3_TCIE_SHIFT)) & SIPI_CIR3_TCIE_MASK) 693 694 #define SIPI_CIR3_RAIE_MASK (0x10U) 695 #define SIPI_CIR3_RAIE_SHIFT (4U) 696 #define SIPI_CIR3_RAIE_WIDTH (1U) 697 #define SIPI_CIR3_RAIE(x) (((uint32_t)(((uint32_t)(x)) << SIPI_CIR3_RAIE_SHIFT)) & SIPI_CIR3_RAIE_MASK) 698 699 #define SIPI_CIR3_WAIE_MASK (0x20U) 700 #define SIPI_CIR3_WAIE_SHIFT (5U) 701 #define SIPI_CIR3_WAIE_WIDTH (1U) 702 #define SIPI_CIR3_WAIE(x) (((uint32_t)(((uint32_t)(x)) << SIPI_CIR3_WAIE_SHIFT)) & SIPI_CIR3_WAIE_MASK) 703 /*! @} */ 704 705 /*! @name CTOR3 - SIPI Channel Timeout Register 3 */ 706 /*! @{ */ 707 708 #define SIPI_CTOR3_TOR_MASK (0xFFFFFFFFU) 709 #define SIPI_CTOR3_TOR_SHIFT (0U) 710 #define SIPI_CTOR3_TOR_WIDTH (32U) 711 #define SIPI_CTOR3_TOR(x) (((uint32_t)(((uint32_t)(x)) << SIPI_CTOR3_TOR_SHIFT)) & SIPI_CTOR3_TOR_MASK) 712 /*! @} */ 713 714 /*! @name CCRC3 - SIPI Channel CRC Register 3 */ 715 /*! @{ */ 716 717 #define SIPI_CCRC3_CRCT_MASK (0xFFFFU) 718 #define SIPI_CCRC3_CRCT_SHIFT (0U) 719 #define SIPI_CCRC3_CRCT_WIDTH (16U) 720 #define SIPI_CCRC3_CRCT(x) (((uint32_t)(((uint32_t)(x)) << SIPI_CCRC3_CRCT_SHIFT)) & SIPI_CCRC3_CRCT_MASK) 721 722 #define SIPI_CCRC3_CRCI_MASK (0xFFFF0000U) 723 #define SIPI_CCRC3_CRCI_SHIFT (16U) 724 #define SIPI_CCRC3_CRCI_WIDTH (16U) 725 #define SIPI_CCRC3_CRCI(x) (((uint32_t)(((uint32_t)(x)) << SIPI_CCRC3_CRCI_SHIFT)) & SIPI_CCRC3_CRCI_MASK) 726 /*! @} */ 727 728 /*! @name CAR3 - SIPI Channel Address Register 3 */ 729 /*! @{ */ 730 731 #define SIPI_CAR3_CAR_MASK (0xFFFFFFFFU) 732 #define SIPI_CAR3_CAR_SHIFT (0U) 733 #define SIPI_CAR3_CAR_WIDTH (32U) 734 #define SIPI_CAR3_CAR(x) (((uint32_t)(((uint32_t)(x)) << SIPI_CAR3_CAR_SHIFT)) & SIPI_CAR3_CAR_MASK) 735 /*! @} */ 736 737 /*! @name CDR3 - SIPI Channel Data Register 3 */ 738 /*! @{ */ 739 740 #define SIPI_CDR3_CDR_MASK (0xFFFFFFFFU) 741 #define SIPI_CDR3_CDR_SHIFT (0U) 742 #define SIPI_CDR3_CDR_WIDTH (32U) 743 #define SIPI_CDR3_CDR(x) (((uint32_t)(((uint32_t)(x)) << SIPI_CDR3_CDR_SHIFT)) & SIPI_CDR3_CDR_MASK) 744 /*! @} */ 745 746 /*! @name MCR - SIPI Module Configuration Register */ 747 /*! @{ */ 748 749 #define SIPI_MCR_SR_MASK (0x1U) 750 #define SIPI_MCR_SR_SHIFT (0U) 751 #define SIPI_MCR_SR_WIDTH (1U) 752 #define SIPI_MCR_SR(x) (((uint32_t)(((uint32_t)(x)) << SIPI_MCR_SR_SHIFT)) & SIPI_MCR_SR_MASK) 753 754 #define SIPI_MCR_MOEN_MASK (0x2U) 755 #define SIPI_MCR_MOEN_SHIFT (1U) 756 #define SIPI_MCR_MOEN_WIDTH (1U) 757 #define SIPI_MCR_MOEN(x) (((uint32_t)(((uint32_t)(x)) << SIPI_MCR_MOEN_SHIFT)) & SIPI_MCR_MOEN_MASK) 758 759 #define SIPI_MCR_INIT_MASK (0x4U) 760 #define SIPI_MCR_INIT_SHIFT (2U) 761 #define SIPI_MCR_INIT_WIDTH (1U) 762 #define SIPI_MCR_INIT(x) (((uint32_t)(((uint32_t)(x)) << SIPI_MCR_INIT_SHIFT)) & SIPI_MCR_INIT_MASK) 763 764 #define SIPI_MCR_TEN_MASK (0x8U) 765 #define SIPI_MCR_TEN_SHIFT (3U) 766 #define SIPI_MCR_TEN_WIDTH (1U) 767 #define SIPI_MCR_TEN(x) (((uint32_t)(((uint32_t)(x)) << SIPI_MCR_TEN_SHIFT)) & SIPI_MCR_TEN_MASK) 768 769 #define SIPI_MCR_CHNSB_MASK (0x10U) 770 #define SIPI_MCR_CHNSB_SHIFT (4U) 771 #define SIPI_MCR_CHNSB_WIDTH (1U) 772 #define SIPI_MCR_CHNSB(x) (((uint32_t)(((uint32_t)(x)) << SIPI_MCR_CHNSB_SHIFT)) & SIPI_MCR_CHNSB_MASK) 773 774 #define SIPI_MCR_LEGACY_MODE_BIT_MASK (0x20U) 775 #define SIPI_MCR_LEGACY_MODE_BIT_SHIFT (5U) 776 #define SIPI_MCR_LEGACY_MODE_BIT_WIDTH (1U) 777 #define SIPI_MCR_LEGACY_MODE_BIT(x) (((uint32_t)(((uint32_t)(x)) << SIPI_MCR_LEGACY_MODE_BIT_SHIFT)) & SIPI_MCR_LEGACY_MODE_BIT_MASK) 778 779 #define SIPI_MCR_MCRIE_MASK (0x200U) 780 #define SIPI_MCR_MCRIE_SHIFT (9U) 781 #define SIPI_MCR_MCRIE_WIDTH (1U) 782 #define SIPI_MCR_MCRIE(x) (((uint32_t)(((uint32_t)(x)) << SIPI_MCR_MCRIE_SHIFT)) & SIPI_MCR_MCRIE_MASK) 783 784 #define SIPI_MCR_CRCIE_MASK (0x400U) 785 #define SIPI_MCR_CRCIE_SHIFT (10U) 786 #define SIPI_MCR_CRCIE_WIDTH (1U) 787 #define SIPI_MCR_CRCIE(x) (((uint32_t)(((uint32_t)(x)) << SIPI_MCR_CRCIE_SHIFT)) & SIPI_MCR_CRCIE_MASK) 788 789 #define SIPI_MCR_AID_MASK (0xC000U) 790 #define SIPI_MCR_AID_SHIFT (14U) 791 #define SIPI_MCR_AID_WIDTH (2U) 792 #define SIPI_MCR_AID(x) (((uint32_t)(((uint32_t)(x)) << SIPI_MCR_AID_SHIFT)) & SIPI_MCR_AID_MASK) 793 794 #define SIPI_MCR_PRSCLR_MASK (0x7FF0000U) 795 #define SIPI_MCR_PRSCLR_SHIFT (16U) 796 #define SIPI_MCR_PRSCLR_WIDTH (11U) 797 #define SIPI_MCR_PRSCLR(x) (((uint32_t)(((uint32_t)(x)) << SIPI_MCR_PRSCLR_SHIFT)) & SIPI_MCR_PRSCLR_MASK) 798 799 #define SIPI_MCR_HALT_MASK (0x20000000U) 800 #define SIPI_MCR_HALT_SHIFT (29U) 801 #define SIPI_MCR_HALT_WIDTH (1U) 802 #define SIPI_MCR_HALT(x) (((uint32_t)(((uint32_t)(x)) << SIPI_MCR_HALT_SHIFT)) & SIPI_MCR_HALT_MASK) 803 804 #define SIPI_MCR_FRZ_MASK (0x80000000U) 805 #define SIPI_MCR_FRZ_SHIFT (31U) 806 #define SIPI_MCR_FRZ_WIDTH (1U) 807 #define SIPI_MCR_FRZ(x) (((uint32_t)(((uint32_t)(x)) << SIPI_MCR_FRZ_SHIFT)) & SIPI_MCR_FRZ_MASK) 808 /*! @} */ 809 810 /*! @name SR - SIPI Status Register */ 811 /*! @{ */ 812 813 #define SIPI_SR_STATE_MASK (0xFU) 814 #define SIPI_SR_STATE_SHIFT (0U) 815 #define SIPI_SR_STATE_WIDTH (4U) 816 #define SIPI_SR_STATE(x) (((uint32_t)(((uint32_t)(x)) << SIPI_SR_STATE_SHIFT)) & SIPI_SR_STATE_MASK) 817 818 #define SIPI_SR_TE_MASK (0xF0U) 819 #define SIPI_SR_TE_SHIFT (4U) 820 #define SIPI_SR_TE_WIDTH (4U) 821 #define SIPI_SR_TE(x) (((uint32_t)(((uint32_t)(x)) << SIPI_SR_TE_SHIFT)) & SIPI_SR_TE_MASK) 822 823 #define SIPI_SR_FRAME_TX_MASK (0x100U) 824 #define SIPI_SR_FRAME_TX_SHIFT (8U) 825 #define SIPI_SR_FRAME_TX_WIDTH (1U) 826 #define SIPI_SR_FRAME_TX(x) (((uint32_t)(((uint32_t)(x)) << SIPI_SR_FRAME_TX_SHIFT)) & SIPI_SR_FRAME_TX_MASK) 827 828 #define SIPI_SR_MCR_MASK (0x200U) 829 #define SIPI_SR_MCR_SHIFT (9U) 830 #define SIPI_SR_MCR_WIDTH (1U) 831 #define SIPI_SR_MCR(x) (((uint32_t)(((uint32_t)(x)) << SIPI_SR_MCR_SHIFT)) & SIPI_SR_MCR_MASK) 832 833 #define SIPI_SR_GCRCE_MASK (0x400U) 834 #define SIPI_SR_GCRCE_SHIFT (10U) 835 #define SIPI_SR_GCRCE_WIDTH (1U) 836 #define SIPI_SR_GCRCE(x) (((uint32_t)(((uint32_t)(x)) << SIPI_SR_GCRCE_SHIFT)) & SIPI_SR_GCRCE_MASK) 837 838 #define SIPI_SR_ACK_TX_MASK (0x800U) 839 #define SIPI_SR_ACK_TX_SHIFT (11U) 840 #define SIPI_SR_ACK_TX_WIDTH (1U) 841 #define SIPI_SR_ACK_TX(x) (((uint32_t)(((uint32_t)(x)) << SIPI_SR_ACK_TX_SHIFT)) & SIPI_SR_ACK_TX_MASK) 842 843 #define SIPI_SR_READ_OK_TX_MASK (0x1000U) 844 #define SIPI_SR_READ_OK_TX_SHIFT (12U) 845 #define SIPI_SR_READ_OK_TX_WIDTH (1U) 846 #define SIPI_SR_READ_OK_TX(x) (((uint32_t)(((uint32_t)(x)) << SIPI_SR_READ_OK_TX_SHIFT)) & SIPI_SR_READ_OK_TX_MASK) 847 848 #define SIPI_SR_INVALID_FRAME_RX_MASK (0x2000U) 849 #define SIPI_SR_INVALID_FRAME_RX_SHIFT (13U) 850 #define SIPI_SR_INVALID_FRAME_RX_WIDTH (1U) 851 #define SIPI_SR_INVALID_FRAME_RX(x) (((uint32_t)(((uint32_t)(x)) << SIPI_SR_INVALID_FRAME_RX_SHIFT)) & SIPI_SR_INVALID_FRAME_RX_MASK) 852 853 #define SIPI_SR_LPMACK_MASK (0x40000000U) 854 #define SIPI_SR_LPMACK_SHIFT (30U) 855 #define SIPI_SR_LPMACK_WIDTH (1U) 856 #define SIPI_SR_LPMACK(x) (((uint32_t)(((uint32_t)(x)) << SIPI_SR_LPMACK_SHIFT)) & SIPI_SR_LPMACK_MASK) 857 858 #define SIPI_SR_FRZACK_MASK (0x80000000U) 859 #define SIPI_SR_FRZACK_SHIFT (31U) 860 #define SIPI_SR_FRZACK_WIDTH (1U) 861 #define SIPI_SR_FRZACK(x) (((uint32_t)(((uint32_t)(x)) << SIPI_SR_FRZACK_SHIFT)) & SIPI_SR_FRZACK_MASK) 862 /*! @} */ 863 864 /*! @name MAXCR - SIPI Max Count Register */ 865 /*! @{ */ 866 867 #define SIPI_MAXCR_MXCNT_MASK (0xFFFFFFFCU) 868 #define SIPI_MAXCR_MXCNT_SHIFT (2U) 869 #define SIPI_MAXCR_MXCNT_WIDTH (30U) 870 #define SIPI_MAXCR_MXCNT(x) (((uint32_t)(((uint32_t)(x)) << SIPI_MAXCR_MXCNT_SHIFT)) & SIPI_MAXCR_MXCNT_MASK) 871 /*! @} */ 872 873 /*! @name ARR - SIPI Address Reload Register */ 874 /*! @{ */ 875 876 #define SIPI_ARR_ADRLD_MASK (0xFFFFFFFCU) 877 #define SIPI_ARR_ADRLD_SHIFT (2U) 878 #define SIPI_ARR_ADRLD_WIDTH (30U) 879 #define SIPI_ARR_ADRLD(x) (((uint32_t)(((uint32_t)(x)) << SIPI_ARR_ADRLD_SHIFT)) & SIPI_ARR_ADRLD_MASK) 880 /*! @} */ 881 882 /*! @name ACR - SIPI Address Count Register */ 883 /*! @{ */ 884 885 #define SIPI_ACR_ADCNT_MASK (0xFFFFFFFCU) 886 #define SIPI_ACR_ADCNT_SHIFT (2U) 887 #define SIPI_ACR_ADCNT_WIDTH (30U) 888 #define SIPI_ACR_ADCNT(x) (((uint32_t)(((uint32_t)(x)) << SIPI_ACR_ADCNT_SHIFT)) & SIPI_ACR_ADCNT_MASK) 889 /*! @} */ 890 891 /*! @name ERR - SIPI Error Register */ 892 /*! @{ */ 893 894 #define SIPI_ERR_ACKE0_MASK (0x1U) 895 #define SIPI_ERR_ACKE0_SHIFT (0U) 896 #define SIPI_ERR_ACKE0_WIDTH (1U) 897 #define SIPI_ERR_ACKE0(x) (((uint32_t)(((uint32_t)(x)) << SIPI_ERR_ACKE0_SHIFT)) & SIPI_ERR_ACKE0_MASK) 898 899 #define SIPI_ERR_TIDE0_MASK (0x2U) 900 #define SIPI_ERR_TIDE0_SHIFT (1U) 901 #define SIPI_ERR_TIDE0_WIDTH (1U) 902 #define SIPI_ERR_TIDE0(x) (((uint32_t)(((uint32_t)(x)) << SIPI_ERR_TIDE0_SHIFT)) & SIPI_ERR_TIDE0_MASK) 903 904 #define SIPI_ERR_TOE0_MASK (0x4U) 905 #define SIPI_ERR_TOE0_SHIFT (2U) 906 #define SIPI_ERR_TOE0_WIDTH (1U) 907 #define SIPI_ERR_TOE0(x) (((uint32_t)(((uint32_t)(x)) << SIPI_ERR_TOE0_SHIFT)) & SIPI_ERR_TOE0_MASK) 908 909 #define SIPI_ERR_ACKE1_MASK (0x100U) 910 #define SIPI_ERR_ACKE1_SHIFT (8U) 911 #define SIPI_ERR_ACKE1_WIDTH (1U) 912 #define SIPI_ERR_ACKE1(x) (((uint32_t)(((uint32_t)(x)) << SIPI_ERR_ACKE1_SHIFT)) & SIPI_ERR_ACKE1_MASK) 913 914 #define SIPI_ERR_TIDE1_MASK (0x200U) 915 #define SIPI_ERR_TIDE1_SHIFT (9U) 916 #define SIPI_ERR_TIDE1_WIDTH (1U) 917 #define SIPI_ERR_TIDE1(x) (((uint32_t)(((uint32_t)(x)) << SIPI_ERR_TIDE1_SHIFT)) & SIPI_ERR_TIDE1_MASK) 918 919 #define SIPI_ERR_TOE1_MASK (0x400U) 920 #define SIPI_ERR_TOE1_SHIFT (10U) 921 #define SIPI_ERR_TOE1_WIDTH (1U) 922 #define SIPI_ERR_TOE1(x) (((uint32_t)(((uint32_t)(x)) << SIPI_ERR_TOE1_SHIFT)) & SIPI_ERR_TOE1_MASK) 923 924 #define SIPI_ERR_ACKE2_MASK (0x10000U) 925 #define SIPI_ERR_ACKE2_SHIFT (16U) 926 #define SIPI_ERR_ACKE2_WIDTH (1U) 927 #define SIPI_ERR_ACKE2(x) (((uint32_t)(((uint32_t)(x)) << SIPI_ERR_ACKE2_SHIFT)) & SIPI_ERR_ACKE2_MASK) 928 929 #define SIPI_ERR_TIDE2_MASK (0x20000U) 930 #define SIPI_ERR_TIDE2_SHIFT (17U) 931 #define SIPI_ERR_TIDE2_WIDTH (1U) 932 #define SIPI_ERR_TIDE2(x) (((uint32_t)(((uint32_t)(x)) << SIPI_ERR_TIDE2_SHIFT)) & SIPI_ERR_TIDE2_MASK) 933 934 #define SIPI_ERR_TOE2_MASK (0x40000U) 935 #define SIPI_ERR_TOE2_SHIFT (18U) 936 #define SIPI_ERR_TOE2_WIDTH (1U) 937 #define SIPI_ERR_TOE2(x) (((uint32_t)(((uint32_t)(x)) << SIPI_ERR_TOE2_SHIFT)) & SIPI_ERR_TOE2_MASK) 938 939 #define SIPI_ERR_ACKE3_MASK (0x1000000U) 940 #define SIPI_ERR_ACKE3_SHIFT (24U) 941 #define SIPI_ERR_ACKE3_WIDTH (1U) 942 #define SIPI_ERR_ACKE3(x) (((uint32_t)(((uint32_t)(x)) << SIPI_ERR_ACKE3_SHIFT)) & SIPI_ERR_ACKE3_MASK) 943 944 #define SIPI_ERR_TIDE3_MASK (0x2000000U) 945 #define SIPI_ERR_TIDE3_SHIFT (25U) 946 #define SIPI_ERR_TIDE3_WIDTH (1U) 947 #define SIPI_ERR_TIDE3(x) (((uint32_t)(((uint32_t)(x)) << SIPI_ERR_TIDE3_SHIFT)) & SIPI_ERR_TIDE3_MASK) 948 949 #define SIPI_ERR_TOE3_MASK (0x4000000U) 950 #define SIPI_ERR_TOE3_SHIFT (26U) 951 #define SIPI_ERR_TOE3_WIDTH (1U) 952 #define SIPI_ERR_TOE3(x) (((uint32_t)(((uint32_t)(x)) << SIPI_ERR_TOE3_SHIFT)) & SIPI_ERR_TOE3_MASK) 953 /*! @} */ 954 955 /*! @name DEBUG - SIPI Debug Register */ 956 /*! @{ */ 957 958 #define SIPI_DEBUG_STATE_MASK (0xFFFFU) 959 #define SIPI_DEBUG_STATE_SHIFT (0U) 960 #define SIPI_DEBUG_STATE_WIDTH (16U) 961 #define SIPI_DEBUG_STATE(x) (((uint32_t)(((uint32_t)(x)) << SIPI_DEBUG_STATE_SHIFT)) & SIPI_DEBUG_STATE_MASK) 962 963 #define SIPI_DEBUG_OUTSTANDING_MASK (0xF0000U) 964 #define SIPI_DEBUG_OUTSTANDING_SHIFT (16U) 965 #define SIPI_DEBUG_OUTSTANDING_WIDTH (4U) 966 #define SIPI_DEBUG_OUTSTANDING(x) (((uint32_t)(((uint32_t)(x)) << SIPI_DEBUG_OUTSTANDING_SHIFT)) & SIPI_DEBUG_OUTSTANDING_MASK) 967 /*! @} */ 968 969 /*! @name PMR - SIPI Performance Monitor register */ 970 /*! @{ */ 971 972 #define SIPI_PMR_BIN0_MASK (0xFFU) 973 #define SIPI_PMR_BIN0_SHIFT (0U) 974 #define SIPI_PMR_BIN0_WIDTH (8U) 975 #define SIPI_PMR_BIN0(x) (((uint32_t)(((uint32_t)(x)) << SIPI_PMR_BIN0_SHIFT)) & SIPI_PMR_BIN0_MASK) 976 977 #define SIPI_PMR_BIN1_MASK (0xFF00U) 978 #define SIPI_PMR_BIN1_SHIFT (8U) 979 #define SIPI_PMR_BIN1_WIDTH (8U) 980 #define SIPI_PMR_BIN1(x) (((uint32_t)(((uint32_t)(x)) << SIPI_PMR_BIN1_SHIFT)) & SIPI_PMR_BIN1_MASK) 981 982 #define SIPI_PMR_BIN2_MASK (0xFF0000U) 983 #define SIPI_PMR_BIN2_SHIFT (16U) 984 #define SIPI_PMR_BIN2_WIDTH (8U) 985 #define SIPI_PMR_BIN2(x) (((uint32_t)(((uint32_t)(x)) << SIPI_PMR_BIN2_SHIFT)) & SIPI_PMR_BIN2_MASK) 986 987 #define SIPI_PMR_BIN3_MASK (0xFF000000U) 988 #define SIPI_PMR_BIN3_SHIFT (24U) 989 #define SIPI_PMR_BIN3_WIDTH (8U) 990 #define SIPI_PMR_BIN3(x) (((uint32_t)(((uint32_t)(x)) << SIPI_PMR_BIN3_SHIFT)) & SIPI_PMR_BIN3_MASK) 991 /*! @} */ 992 993 /*! 994 * @} 995 */ /* end of group SIPI_Register_Masks */ 996 997 /*! 998 * @} 999 */ /* end of group SIPI_Peripheral_Access_Layer */ 1000 1001 #endif /* #if !defined(S32Z2_SIPI_H_) */ 1002
