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Searched refs:SIM_SOPT1CFG_URWE_MASK (Results 1 – 25 of 26) sorted by relevance

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/hal_nxp-latest/mcux/mcux-sdk/drivers/sim/
Dfsl_sim.c35 SIM->SOPT1CFG |= (SIM_SOPT1CFG_URWE_MASK | SIM_SOPT1CFG_UVSWE_MASK | SIM_SOPT1CFG_USSWE_MASK); in SIM_SetUsbVoltRegulatorEnableMode()
/hal_nxp-latest/mcux/mcux-sdk/devices/MKL25Z4/
DMKL25Z4.h3671 #define SIM_SOPT1CFG_URWE_MASK (0x1000000U) macro
3673 … (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1CFG_URWE_SHIFT)) & SIM_SOPT1CFG_URWE_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXC243/
DMCXC243.h8317 #define SIM_SOPT1CFG_URWE_MASK (0x1000000U) macro
8323 … (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1CFG_URWE_SHIFT)) & SIM_SOPT1CFG_URWE_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXC244/
DMCXC244.h8319 #define SIM_SOPT1CFG_URWE_MASK (0x1000000U) macro
8325 … (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1CFG_URWE_SHIFT)) & SIM_SOPT1CFG_URWE_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/K32L2B21A/
DK32L2B21A.h11426 #define SIM_SOPT1CFG_URWE_MASK (0x1000000U) macro
11432 …OPT1CFG_URWE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1CFG_URWE_SHIFT)) & SIM_SOPT1CFG_URWE_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/K32L2B31A/
DK32L2B31A.h11426 #define SIM_SOPT1CFG_URWE_MASK (0x1000000U) macro
11432 …OPT1CFG_URWE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1CFG_URWE_SHIFT)) & SIM_SOPT1CFG_URWE_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/K32L2B11A/
DK32L2B11A.h11426 #define SIM_SOPT1CFG_URWE_MASK (0x1000000U) macro
11432 …OPT1CFG_URWE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1CFG_URWE_SHIFT)) & SIM_SOPT1CFG_URWE_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXC444/
DMCXC444.h13027 #define SIM_SOPT1CFG_URWE_MASK (0x1000000U) macro
13033 … (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1CFG_URWE_SHIFT)) & SIM_SOPT1CFG_URWE_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXC443/
DMCXC443.h13027 #define SIM_SOPT1CFG_URWE_MASK (0x1000000U) macro
13033 … (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1CFG_URWE_SHIFT)) & SIM_SOPT1CFG_URWE_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKW22D5/
DMKW22D5.h6453 #define SIM_SOPT1CFG_URWE_MASK (0x1000000U) macro
6455 … (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1CFG_URWE_SHIFT)) & SIM_SOPT1CFG_URWE_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKW24D5/
DMKW24D5.h6453 #define SIM_SOPT1CFG_URWE_MASK (0x1000000U) macro
6455 … (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1CFG_URWE_SHIFT)) & SIM_SOPT1CFG_URWE_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MK22F25612/
DMK22F25612.h11248 #define SIM_SOPT1CFG_URWE_MASK (0x1000000U) macro
11254 … (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1CFG_URWE_SHIFT)) & SIM_SOPT1CFG_URWE_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MK22F51212/
DMK22F51212.h11504 #define SIM_SOPT1CFG_URWE_MASK (0x1000000U) macro
11510 … (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1CFG_URWE_SHIFT)) & SIM_SOPT1CFG_URWE_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/K32L2A41A/
DK32L2A41A.h15395 #define SIM_SOPT1CFG_URWE_MASK (0x1000000U) macro
15401 … (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1CFG_URWE_SHIFT)) & SIM_SOPT1CFG_URWE_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/K32L2A31A/
DK32L2A31A.h15395 #define SIM_SOPT1CFG_URWE_MASK (0x1000000U) macro
15401 … (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1CFG_URWE_SHIFT)) & SIM_SOPT1CFG_URWE_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MK22F12/
DMK22F12.h15817 #define SIM_SOPT1CFG_URWE_MASK (0x1000000U) macro
15823 … (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1CFG_URWE_SHIFT)) & SIM_SOPT1CFG_URWE_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MK24F12/
DMK24F12.h19270 #define SIM_SOPT1CFG_URWE_MASK (0x1000000U) macro
19276 … (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1CFG_URWE_SHIFT)) & SIM_SOPT1CFG_URWE_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MK64F12/
DMK64F12.h21101 #define SIM_SOPT1CFG_URWE_MASK (0x1000000U) macro
21107 … (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1CFG_URWE_SHIFT)) & SIM_SOPT1CFG_URWE_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MK63F12/
DMK63F12.h21055 #define SIM_SOPT1CFG_URWE_MASK (0x1000000U) macro
21061 … (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1CFG_URWE_SHIFT)) & SIM_SOPT1CFG_URWE_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MK80F25615/
DMK80F25615.h21447 #define SIM_SOPT1CFG_URWE_MASK (0x1000000U) macro
21453 … (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1CFG_URWE_SHIFT)) & SIM_SOPT1CFG_URWE_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MK82F25615/
DMK82F25615.h22420 #define SIM_SOPT1CFG_URWE_MASK (0x1000000U) macro
22426 … (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1CFG_URWE_SHIFT)) & SIM_SOPT1CFG_URWE_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MK28FA15/
DMK28FA15.h20983 #define SIM_SOPT1CFG_URWE_MASK (0x1000000U) macro
20989 … (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1CFG_URWE_SHIFT)) & SIM_SOPT1CFG_URWE_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MK27FA15/
DMK27FA15.h20981 #define SIM_SOPT1CFG_URWE_MASK (0x1000000U) macro
20987 … (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1CFG_URWE_SHIFT)) & SIM_SOPT1CFG_URWE_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MK26F18/
DMK26F18.h23426 #define SIM_SOPT1CFG_URWE_MASK (0x1000000U) macro
23432 … (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1CFG_URWE_SHIFT)) & SIM_SOPT1CFG_URWE_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MK65F18/
DMK65F18.h25243 #define SIM_SOPT1CFG_URWE_MASK (0x1000000U) macro
25249 … (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1CFG_URWE_SHIFT)) & SIM_SOPT1CFG_URWE_MASK)

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