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Searched refs:SIM_SCGC4_CMP_MASK (Results 1 – 25 of 37) sorted by relevance

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/hal_nxp-latest/mcux/mcux-sdk/devices/MCXC041/
DMCXC041.h5768 #define SIM_SCGC4_CMP_MASK (0x80000U) macro
5774 … (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_CMP_SHIFT)) & SIM_SCGC4_CMP_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKL25Z4/
DMKL25Z4.h3794 #define SIM_SCGC4_CMP_MASK (0x80000U) macro
3796 … (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_CMP_SHIFT)) & SIM_SCGC4_CMP_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MK02F12810/
DMK02F12810.h8596 #define SIM_SCGC4_CMP_MASK (0x80000U) macro
8602 … (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_CMP_SHIFT)) & SIM_SCGC4_CMP_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKV30F12810/
DMKV30F12810.h8622 #define SIM_SCGC4_CMP_MASK (0x80000U) macro
8628 … (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_CMP_SHIFT)) & SIM_SCGC4_CMP_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKV10Z7/
DMKV10Z7.h8556 #define SIM_SCGC4_CMP_MASK (0x80000U) macro
8562 … (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_CMP_SHIFT)) & SIM_SCGC4_CMP_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKV31F12810/
DMKV31F12810.h9391 #define SIM_SCGC4_CMP_MASK (0x80000U) macro
9397 … (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_CMP_SHIFT)) & SIM_SCGC4_CMP_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKV10Z1287/
DMKV10Z1287.h9564 #define SIM_SCGC4_CMP_MASK (0x80000U) macro
9570 … (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_CMP_SHIFT)) & SIM_SCGC4_CMP_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKV11Z7/
DMKV11Z7.h10352 #define SIM_SCGC4_CMP_MASK (0x80000U) macro
10358 … (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_CMP_SHIFT)) & SIM_SCGC4_CMP_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKV31F25612/
DMKV31F25612.h10459 #define SIM_SCGC4_CMP_MASK (0x80000U) macro
10465 … (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_CMP_SHIFT)) & SIM_SCGC4_CMP_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKV31F51212/
DMKV31F51212.h10805 #define SIM_SCGC4_CMP_MASK (0x80000U) macro
10811 … (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_CMP_SHIFT)) & SIM_SCGC4_CMP_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MK22F12810/
DMK22F12810.h10633 #define SIM_SCGC4_CMP_MASK (0x80000U) macro
10639 … (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_CMP_SHIFT)) & SIM_SCGC4_CMP_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKW22D5/
DMKW22D5.h6585 #define SIM_SCGC4_CMP_MASK (0x80000U) macro
6587 … (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_CMP_SHIFT)) & SIM_SCGC4_CMP_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKW24D5/
DMKW24D5.h6585 #define SIM_SCGC4_CMP_MASK (0x80000U) macro
6587 … (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_CMP_SHIFT)) & SIM_SCGC4_CMP_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MK22F25612/
DMK22F25612.h11750 #define SIM_SCGC4_CMP_MASK (0x80000U) macro
11756 … (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_CMP_SHIFT)) & SIM_SCGC4_CMP_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MK22F51212/
DMK22F51212.h12106 #define SIM_SCGC4_CMP_MASK (0x80000U) macro
12112 … (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_CMP_SHIFT)) & SIM_SCGC4_CMP_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MK22F12/
DMK22F12.h16335 #define SIM_SCGC4_CMP_MASK (0x80000U) macro
16341 … (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_CMP_SHIFT)) & SIM_SCGC4_CMP_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKM35Z7/
DMKM35Z7.h16182 #define SIM_SCGC4_CMP_MASK (0x40000U) macro
16188 … (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_CMP_SHIFT)) & SIM_SCGC4_CMP_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKM34Z7/
DMKM34Z7.h16298 #define SIM_SCGC4_CMP_MASK (0x40000U) macro
16304 …ne SIM_SCGC4_CMP(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_CMP_SHIFT)) & SIM_SCGC4_CMP_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MK24F12/
DMK24F12.h19898 #define SIM_SCGC4_CMP_MASK (0x80000U) macro
19904 … (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_CMP_SHIFT)) & SIM_SCGC4_CMP_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKW31Z4/
DMKW31Z4.h6398 #define SIM_SCGC4_CMP_MASK (0x80000U) macro
6400 … (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_CMP_SHIFT)) & SIM_SCGC4_CMP_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKW30Z4/
DMKW30Z4.h6962 #define SIM_SCGC4_CMP_MASK 0x80000u macro
6965 …(x) (((uint32_t)(((uint32_t)(x))<<SIM_SCGC4_CMP_SHIFT))&SIM_SCGC4_CMP_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKW21Z4/
DMKW21Z4.h6327 #define SIM_SCGC4_CMP_MASK (0x80000U) macro
6329 … (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_CMP_SHIFT)) & SIM_SCGC4_CMP_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKW20Z4/
DMKW20Z4.h6962 #define SIM_SCGC4_CMP_MASK 0x80000u macro
6965 …(x) (((uint32_t)(((uint32_t)(x))<<SIM_SCGC4_CMP_SHIFT))&SIM_SCGC4_CMP_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MK64F12/
DMK64F12.h21755 #define SIM_SCGC4_CMP_MASK (0x80000U) macro
21761 … (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_CMP_SHIFT)) & SIM_SCGC4_CMP_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MK63F12/
DMK63F12.h21709 #define SIM_SCGC4_CMP_MASK (0x80000U) macro
21715 … (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_CMP_SHIFT)) & SIM_SCGC4_CMP_MASK)

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