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Searched refs:SIM_FCFG2_MAXADDR_MASK (Results 1 – 8 of 8) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/devices/MKV10Z7/
DMKV10Z7.h8793 #define SIM_FCFG2_MAXADDR_MASK (0x7F000000U) macro
8795 … (((uint32_t)(((uint32_t)(x)) << SIM_FCFG2_MAXADDR_SHIFT)) & SIM_FCFG2_MAXADDR_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKV10Z1287/
DMKV10Z1287.h9836 #define SIM_FCFG2_MAXADDR_MASK (0x7F000000U) macro
9838 … (((uint32_t)(((uint32_t)(x)) << SIM_FCFG2_MAXADDR_SHIFT)) & SIM_FCFG2_MAXADDR_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKM14ZA5/
DMKM14ZA5.h10302 #define SIM_FCFG2_MAXADDR_MASK (0x7F000000U) macro
10306 … (((uint32_t)(((uint32_t)(x)) << SIM_FCFG2_MAXADDR_SHIFT)) & SIM_FCFG2_MAXADDR_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKV11Z7/
DMKV11Z7.h10624 #define SIM_FCFG2_MAXADDR_MASK (0x7F000000U) macro
10626 … (((uint32_t)(((uint32_t)(x)) << SIM_FCFG2_MAXADDR_SHIFT)) & SIM_FCFG2_MAXADDR_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKM33ZA5/
DMKM33ZA5.h15007 #define SIM_FCFG2_MAXADDR_MASK (0x7F000000U) macro
15011 … (((uint32_t)(((uint32_t)(x)) << SIM_FCFG2_MAXADDR_SHIFT)) & SIM_FCFG2_MAXADDR_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKM34ZA5/
DMKM34ZA5.h15003 #define SIM_FCFG2_MAXADDR_MASK (0x7F000000U) macro
15007 … (((uint32_t)(((uint32_t)(x)) << SIM_FCFG2_MAXADDR_SHIFT)) & SIM_FCFG2_MAXADDR_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKL25Z4/
DMKL25Z4.h5488 #define SIM_FCFG2_MAXADDR_MASK SIM_FCFG2_MAXADDR0_MASK macro
/hal_nxp-latest/mcux/mcux-sdk/devices/MKM34Z7/
DMKM34Z7.h16646 #define SIM_FCFG2_MAXADDR_MASK (0x7F000000U) macro
16650 …CFG2_MAXADDR(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG2_MAXADDR_SHIFT)) & SIM_FCFG2_MAXADDR_MASK)