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Searched refs:SIMR (Results 1 – 25 of 46) sorted by relevance

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/hal_nxp-latest/mcux/mcux-sdk/drivers/netc/netc_hw/
Dfsl_netc_hw_si.h87 base->SIMR |= ENETC_SI_SIMR_EN_MASK; in NETC_SIEnable()
91 base->SIMR &= ~ENETC_SI_SIMR_EN_MASK; in NETC_SIEnable()
125 base->SIMR |= ((uint32_t)1U << ((uint32_t)type + 1U)); in NETC_SIEnablePromisc()
129 base->SIMR &= ~((uint32_t)1U << ((uint32_t)type + 1U)); in NETC_SIEnablePromisc()
231 base->SIMR |= ENETC_SI_SIMR_V2IPVE_MASK; in NETC_SIEnableVlanToIpv()
235 base->SIMR &= ~ENETC_SI_SIMR_V2IPVE_MASK; in NETC_SIEnableVlanToIpv()
279 …base->SIMR = (base->SIMR & (~ENETC_SI_SIMR_DEFAULT_RX_GROUP_MASK)) | ENETC_SI_SIMR_DEFAULT_RX_GROU… in NETC_SISetDefaultRxBDRGroup()
/hal_nxp-latest/s32/drivers/s32ze/Eth_NETC/src/
DNetc_Eth_Ip.c1175 …netcSIsBase[ctrlIndex]->SIMR &= (netcSIsBase[ctrlIndex]->SIMR ^ NETC_F3_SI0_SIMR_DEFAULT_RX_GROUP(… in Netc_Eth_Ip_Init_VlanToIpvMapping()
1181 netcSIsBase[ctrlIndex]->SIMR |= (NETC_F3_SI1_SIMR_V2IPVE(1U)); in Netc_Eth_Ip_Init_VlanToIpvMapping()
1205 … netcSIsBase[ctrlIndex]->SIMR &= (netcSIsBase[ctrlIndex]->SIMR ^ NETC_F3_SI0_SIMR_V2IPVE(1U)); in Netc_Eth_Ip_Init_VlanToIpvMapping()
1456 netcSIsBase[ctrlIndex]->SIMR |= NETC_F3_SI0_SIMR_EN_MASK; in Netc_Eth_Ip_InitIngressPortFilterTable()
1468 netcSIsBase[ctrlIndex]->SIMR &= ~NETC_F3_SI0_SIMR_EN_MASK; in Netc_Eth_Ip_InitIngressPortFilterTable()
5954 netcSIsBase[ctrlIndex]->SIMR |= NETC_F3_SI0_SIMR_EN_MASK;
5993 netcSIsBase[ctrlIndex]->SIMR &= ~NETC_F3_SI0_SIMR_EN_MASK;
6722 netcSIsBase[ctrlIndex]->SIMR |= NETC_F3_SI0_SIMR_EN_MASK;
6760 netcSIsBase[ctrlIndex]->SIMR &= ~NETC_F3_SI0_SIMR_EN_MASK;
7149 netcSIsBase[siHwId]->SIMR &= ~(NETC_F3_SI0_SIMR_EN_MASK);
[all …]
DNetc_Eth_Ip_Irq.c549 netcSIsBase[siHwId]->SIMR &= ~(NETC_F3_SI0_SIMR_EN_MASK); in Netc_Eth_Ip_InitVSIAfterFlr()
/hal_nxp-latest/s32/drivers/s32ze/BaseNXP/header/
DS32Z2_NETC_F3_SI5.h79 …__IO uint32_t SIMR; /**< Station interface mode register, offset: 0x0… member
DS32Z2_NETC_F3_SI6.h79 …__IO uint32_t SIMR; /**< Station interface mode register, offset: 0x0… member
DS32Z2_NETC_F3_SI7.h79 …__IO uint32_t SIMR; /**< Station interface mode register, offset: 0x0… member
DS32Z2_NETC_F3_SI4.h79 …__IO uint32_t SIMR; /**< Station interface mode register, offset: 0x0… member
DS32Z2_NETC_F3_SI1.h79 …__IO uint32_t SIMR; /**< Station interface mode register, offset: 0x0… member
DS32Z2_NETC_F3_SI2.h79 …__IO uint32_t SIMR; /**< Station interface mode register, offset: 0x0… member
DS32Z2_NETC_F3_SI3.h79 …__IO uint32_t SIMR; /**< Station interface mode register, offset: 0x0… member
DS32Z2_NETC_F3_SI0.h79 …__IO uint32_t SIMR; /**< Station interface mode register, offset: 0x0… member
/hal_nxp-latest/imx/devices/MCIMX6X/
DMCIMX6X_M4.h34159 …__IO uint32_t SIMR; /**< SRC Interrupt Mask Register, offset: 0… member
34187 #define SRC_SIMR_REG(base) ((base)->SIMR)
/hal_nxp-latest/imx/devices/MCIMX7D/
DMCIMX7D_M4.h40535 …__IO uint32_t SIMR; /**< SRC Interrupt Mask Register, offset: 0… member
40574 #define SRC_SIMR_REG(base) ((base)->SIMR)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MN5/
DMIMX8MN5_cm7.h48991 __IO uint32_t SIMR; /**< SRC Interrupt Mask Register, offset: 0x6C */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MN2/
DMIMX8MN2_cm7.h48989 __IO uint32_t SIMR; /**< SRC Interrupt Mask Register, offset: 0x6C */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MN4/
DMIMX8MN4_cm7.h48989 __IO uint32_t SIMR; /**< SRC Interrupt Mask Register, offset: 0x6C */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MN3/
DMIMX8MN3_cm7.h48991 __IO uint32_t SIMR; /**< SRC Interrupt Mask Register, offset: 0x6C */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MN1/
DMIMX8MN1_cm7.h48991 __IO uint32_t SIMR; /**< SRC Interrupt Mask Register, offset: 0x6C */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MN6/
DMIMX8MN6_cm7.h48989 __IO uint32_t SIMR; /**< SRC Interrupt Mask Register, offset: 0x6C */ member
DMIMX8MN6_ca53.h49003 __IO uint32_t SIMR; /**< SRC Interrupt Mask Register, offset: 0x6C */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MQ5/
DMIMX8MQ5_cm4.h50895 __IO uint32_t SIMR; /**< SRC Interrupt Mask Register, offset: 0x6C */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MD7/
DMIMX8MD7_cm4.h53068 __IO uint32_t SIMR; /**< SRC Interrupt Mask Register, offset: 0x6C */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MD6/
DMIMX8MD6_cm4.h53068 __IO uint32_t SIMR; /**< SRC Interrupt Mask Register, offset: 0x6C */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MQ6/
DMIMX8MQ6_cm4.h53068 __IO uint32_t SIMR; /**< SRC Interrupt Mask Register, offset: 0x6C */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MQ7/
DMIMX8MQ7_cm4.h53068 __IO uint32_t SIMR; /**< SRC Interrupt Mask Register, offset: 0x6C */ member

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