Searched refs:SEMC_SRAMCR5_CEH_SHIFT (Results 1 – 16 of 16) sorted by relevance
66661 #define SEMC_SRAMCR5_CEH_SHIFT (4U) macro66663 …MCR5_CEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR5_CEH_SHIFT)) & SEMC_S…
65759 #define SEMC_SRAMCR5_CEH_SHIFT (4U) macro65761 …MCR5_CEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR5_CEH_SHIFT)) & SEMC_S…
65257 #define SEMC_SRAMCR5_CEH_SHIFT (4U) macro65259 …MCR5_CEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR5_CEH_SHIFT)) & SEMC_S…
66159 #define SEMC_SRAMCR5_CEH_SHIFT (4U) macro66161 …MCR5_CEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR5_CEH_SHIFT)) & SEMC_S…
71622 #define SEMC_SRAMCR5_CEH_SHIFT (4U) macro71624 …MCR5_CEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR5_CEH_SHIFT)) & SEMC_S…
70720 #define SEMC_SRAMCR5_CEH_SHIFT (4U) macro70722 …MCR5_CEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR5_CEH_SHIFT)) & SEMC_S…
72121 #define SEMC_SRAMCR5_CEH_SHIFT (4U) macro72123 …MCR5_CEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR5_CEH_SHIFT)) & SEMC_S…
71219 #define SEMC_SRAMCR5_CEH_SHIFT (4U) macro71221 …MCR5_CEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR5_CEH_SHIFT)) & SEMC_S…
71222 #define SEMC_SRAMCR5_CEH_SHIFT (4U) macro71224 …MCR5_CEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR5_CEH_SHIFT)) & SEMC_S…
81889 #define SEMC_SRAMCR5_CEH_SHIFT (4U) macro81891 …MCR5_CEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR5_CEH_SHIFT)) & SEMC_S…
82791 #define SEMC_SRAMCR5_CEH_SHIFT (4U) macro82793 …MCR5_CEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR5_CEH_SHIFT)) & SEMC_S…
75716 #define SEMC_SRAMCR5_CEH_SHIFT (4U) macro75718 …MCR5_CEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR5_CEH_SHIFT)) & SEMC_S…
73690 #define SEMC_SRAMCR5_CEH_SHIFT (4U) macro73692 …MCR5_CEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR5_CEH_SHIFT)) & SEMC_S…
79564 #define SEMC_SRAMCR5_CEH_SHIFT (4U) macro79566 …MCR5_CEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR5_CEH_SHIFT)) & SEMC_S…
77519 #define SEMC_SRAMCR5_CEH_SHIFT (4U) macro77521 …MCR5_CEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR5_CEH_SHIFT)) & SEMC_S…