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Searched refs:SEMC_SRAMCR4_BL_MASK (Results 1 – 16 of 16) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1175/
DMIMXRT1175_cm4.h66589 #define SEMC_SRAMCR4_BL_MASK (0x70U) macro
66601 … (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR4_BL_SHIFT)) & SEMC_SRAMCR4_BL_MASK)
DMIMXRT1175_cm7.h65687 #define SEMC_SRAMCR4_BL_MASK (0x70U) macro
65699 … (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR4_BL_SHIFT)) & SEMC_SRAMCR4_BL_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1165/
DMIMXRT1165_cm7.h65185 #define SEMC_SRAMCR4_BL_MASK (0x70U) macro
65197 … (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR4_BL_SHIFT)) & SEMC_SRAMCR4_BL_MASK)
DMIMXRT1165_cm4.h66087 #define SEMC_SRAMCR4_BL_MASK (0x70U) macro
66099 … (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR4_BL_SHIFT)) & SEMC_SRAMCR4_BL_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1171/
DMIMXRT1171.h65687 #define SEMC_SRAMCR4_BL_MASK (0x70U) macro
65699 … (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR4_BL_SHIFT)) & SEMC_SRAMCR4_BL_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1166/
DMIMXRT1166_cm4.h71550 #define SEMC_SRAMCR4_BL_MASK (0x70U) macro
71562 … (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR4_BL_SHIFT)) & SEMC_SRAMCR4_BL_MASK)
DMIMXRT1166_cm7.h70648 #define SEMC_SRAMCR4_BL_MASK (0x70U) macro
70660 … (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR4_BL_SHIFT)) & SEMC_SRAMCR4_BL_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1173/
DMIMXRT1173_cm4.h72049 #define SEMC_SRAMCR4_BL_MASK (0x70U) macro
72061 … (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR4_BL_SHIFT)) & SEMC_SRAMCR4_BL_MASK)
DMIMXRT1173_cm7.h71147 #define SEMC_SRAMCR4_BL_MASK (0x70U) macro
71159 … (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR4_BL_SHIFT)) & SEMC_SRAMCR4_BL_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1172/
DMIMXRT1172.h71150 #define SEMC_SRAMCR4_BL_MASK (0x70U) macro
71162 … (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR4_BL_SHIFT)) & SEMC_SRAMCR4_BL_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1176/
DMIMXRT1176_cm7.h81817 #define SEMC_SRAMCR4_BL_MASK (0x70U) macro
81829 … (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR4_BL_SHIFT)) & SEMC_SRAMCR4_BL_MASK)
DMIMXRT1176_cm4.h82719 #define SEMC_SRAMCR4_BL_MASK (0x70U) macro
82731 … (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR4_BL_SHIFT)) & SEMC_SRAMCR4_BL_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1187/
DMIMXRT1187_cm33.h75644 #define SEMC_SRAMCR4_BL_MASK (0x70U) macro
75656 … (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR4_BL_SHIFT)) & SEMC_SRAMCR4_BL_MASK)
DMIMXRT1187_cm7.h73618 #define SEMC_SRAMCR4_BL_MASK (0x70U) macro
73630 … (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR4_BL_SHIFT)) & SEMC_SRAMCR4_BL_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1189/
DMIMXRT1189_cm33.h79492 #define SEMC_SRAMCR4_BL_MASK (0x70U) macro
79504 … (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR4_BL_SHIFT)) & SEMC_SRAMCR4_BL_MASK)
DMIMXRT1189_cm7.h77447 #define SEMC_SRAMCR4_BL_MASK (0x70U) macro
77459 … (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR4_BL_SHIFT)) & SEMC_SRAMCR4_BL_MASK)