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Searched refs:SEMC_SDRAMCR3_REN_MASK (Results 1 – 25 of 26) sorted by relevance

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/hal_nxp-latest/mcux/mcux-sdk/drivers/semc/
Dfsl_semc.c549 base->SDRAMCR3 |= SEMC_SDRAMCR3_REN_MASK; in SEMC_ConfigureSDRAM()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1024/
DMIMXRT1024.h33733 #define SEMC_SDRAMCR3_REN_MASK (0x1U) macro
33739 … (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_REN_SHIFT)) & SEMC_SDRAMCR3_REN_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1021/
DMIMXRT1021.h33754 #define SEMC_SDRAMCR3_REN_MASK (0x1U) macro
33760 … (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_REN_SHIFT)) & SEMC_SDRAMCR3_REN_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1051/
DMIMXRT1051.h35311 #define SEMC_SDRAMCR3_REN_MASK (0x1U) macro
35314 … (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_REN_SHIFT)) & SEMC_SDRAMCR3_REN_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1041/
DMIMXRT1041.h36604 #define SEMC_SDRAMCR3_REN_MASK (0x1U) macro
36610 … (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_REN_SHIFT)) & SEMC_SDRAMCR3_REN_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1052/
DMIMXRT1052.h39577 #define SEMC_SDRAMCR3_REN_MASK (0x1U) macro
39580 … (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_REN_SHIFT)) & SEMC_SDRAMCR3_REN_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1042/
DMIMXRT1042.h40014 #define SEMC_SDRAMCR3_REN_MASK (0x1U) macro
40020 … (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_REN_SHIFT)) & SEMC_SDRAMCR3_REN_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1061/
DMIMXRT1061.h37488 #define SEMC_SDRAMCR3_REN_MASK (0x1U) macro
37494 … (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_REN_SHIFT)) & SEMC_SDRAMCR3_REN_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1064/
DMIMXRT1064.h41689 #define SEMC_SDRAMCR3_REN_MASK (0x1U) macro
41695 … (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_REN_SHIFT)) & SEMC_SDRAMCR3_REN_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1062/
DMIMXRT1062.h41682 #define SEMC_SDRAMCR3_REN_MASK (0x1U) macro
41688 … (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_REN_SHIFT)) & SEMC_SDRAMCR3_REN_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1175/
DMIMXRT1175_cm4.h65587 #define SEMC_SDRAMCR3_REN_MASK (0x1U) macro
65593 … (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_REN_SHIFT)) & SEMC_SDRAMCR3_REN_MASK)
DMIMXRT1175_cm7.h64685 #define SEMC_SDRAMCR3_REN_MASK (0x1U) macro
64691 … (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_REN_SHIFT)) & SEMC_SDRAMCR3_REN_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1165/
DMIMXRT1165_cm7.h64183 #define SEMC_SDRAMCR3_REN_MASK (0x1U) macro
64189 … (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_REN_SHIFT)) & SEMC_SDRAMCR3_REN_MASK)
DMIMXRT1165_cm4.h65085 #define SEMC_SDRAMCR3_REN_MASK (0x1U) macro
65091 … (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_REN_SHIFT)) & SEMC_SDRAMCR3_REN_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1171/
DMIMXRT1171.h64685 #define SEMC_SDRAMCR3_REN_MASK (0x1U) macro
64691 … (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_REN_SHIFT)) & SEMC_SDRAMCR3_REN_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1166/
DMIMXRT1166_cm4.h70548 #define SEMC_SDRAMCR3_REN_MASK (0x1U) macro
70554 … (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_REN_SHIFT)) & SEMC_SDRAMCR3_REN_MASK)
DMIMXRT1166_cm7.h69646 #define SEMC_SDRAMCR3_REN_MASK (0x1U) macro
69652 … (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_REN_SHIFT)) & SEMC_SDRAMCR3_REN_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1173/
DMIMXRT1173_cm4.h71047 #define SEMC_SDRAMCR3_REN_MASK (0x1U) macro
71053 … (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_REN_SHIFT)) & SEMC_SDRAMCR3_REN_MASK)
DMIMXRT1173_cm7.h70145 #define SEMC_SDRAMCR3_REN_MASK (0x1U) macro
70151 … (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_REN_SHIFT)) & SEMC_SDRAMCR3_REN_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1172/
DMIMXRT1172.h70148 #define SEMC_SDRAMCR3_REN_MASK (0x1U) macro
70154 … (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_REN_SHIFT)) & SEMC_SDRAMCR3_REN_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1176/
DMIMXRT1176_cm7.h80815 #define SEMC_SDRAMCR3_REN_MASK (0x1U) macro
80821 … (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_REN_SHIFT)) & SEMC_SDRAMCR3_REN_MASK)
DMIMXRT1176_cm4.h81717 #define SEMC_SDRAMCR3_REN_MASK (0x1U) macro
81723 … (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_REN_SHIFT)) & SEMC_SDRAMCR3_REN_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1187/
DMIMXRT1187_cm33.h74609 #define SEMC_SDRAMCR3_REN_MASK (0x1U) macro
74615 … (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_REN_SHIFT)) & SEMC_SDRAMCR3_REN_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1189/
DMIMXRT1189_cm33.h78457 #define SEMC_SDRAMCR3_REN_MASK (0x1U) macro
78463 … (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_REN_SHIFT)) & SEMC_SDRAMCR3_REN_MASK)
DMIMXRT1189_cm7.h76412 #define SEMC_SDRAMCR3_REN_MASK (0x1U) macro
76418 … (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_REN_SHIFT)) & SEMC_SDRAMCR3_REN_MASK)

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