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Searched refs:SEMC_NORCR2_RDH_MASK (Results 1 – 21 of 21) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1041/
DMIMXRT1041.h36973 #define SEMC_NORCR2_RDH_MASK (0xF0000000U) macro
36976 … (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_RDH_SHIFT)) & SEMC_NORCR2_RDH_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1042/
DMIMXRT1042.h40383 #define SEMC_NORCR2_RDH_MASK (0xF0000000U) macro
40386 … (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_RDH_SHIFT)) & SEMC_NORCR2_RDH_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1061/
DMIMXRT1061.h37857 #define SEMC_NORCR2_RDH_MASK (0xF0000000U) macro
37860 … (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_RDH_SHIFT)) & SEMC_NORCR2_RDH_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1064/
DMIMXRT1064.h42058 #define SEMC_NORCR2_RDH_MASK (0xF0000000U) macro
42061 … (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_RDH_SHIFT)) & SEMC_NORCR2_RDH_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1062/
DMIMXRT1062.h42051 #define SEMC_NORCR2_RDH_MASK (0xF0000000U) macro
42054 … (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_RDH_SHIFT)) & SEMC_NORCR2_RDH_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1175/
DMIMXRT1175_cm4.h65961 #define SEMC_NORCR2_RDH_MASK (0xF0000000U) macro
65964 … (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_RDH_SHIFT)) & SEMC_NORCR2_RDH_MASK)
DMIMXRT1175_cm7.h65059 #define SEMC_NORCR2_RDH_MASK (0xF0000000U) macro
65062 … (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_RDH_SHIFT)) & SEMC_NORCR2_RDH_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1165/
DMIMXRT1165_cm7.h64557 #define SEMC_NORCR2_RDH_MASK (0xF0000000U) macro
64560 … (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_RDH_SHIFT)) & SEMC_NORCR2_RDH_MASK)
DMIMXRT1165_cm4.h65459 #define SEMC_NORCR2_RDH_MASK (0xF0000000U) macro
65462 … (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_RDH_SHIFT)) & SEMC_NORCR2_RDH_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1171/
DMIMXRT1171.h65059 #define SEMC_NORCR2_RDH_MASK (0xF0000000U) macro
65062 … (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_RDH_SHIFT)) & SEMC_NORCR2_RDH_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1166/
DMIMXRT1166_cm4.h70922 #define SEMC_NORCR2_RDH_MASK (0xF0000000U) macro
70925 … (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_RDH_SHIFT)) & SEMC_NORCR2_RDH_MASK)
DMIMXRT1166_cm7.h70020 #define SEMC_NORCR2_RDH_MASK (0xF0000000U) macro
70023 … (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_RDH_SHIFT)) & SEMC_NORCR2_RDH_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1173/
DMIMXRT1173_cm4.h71421 #define SEMC_NORCR2_RDH_MASK (0xF0000000U) macro
71424 … (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_RDH_SHIFT)) & SEMC_NORCR2_RDH_MASK)
DMIMXRT1173_cm7.h70519 #define SEMC_NORCR2_RDH_MASK (0xF0000000U) macro
70522 … (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_RDH_SHIFT)) & SEMC_NORCR2_RDH_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1172/
DMIMXRT1172.h70522 #define SEMC_NORCR2_RDH_MASK (0xF0000000U) macro
70525 … (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_RDH_SHIFT)) & SEMC_NORCR2_RDH_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1176/
DMIMXRT1176_cm7.h81189 #define SEMC_NORCR2_RDH_MASK (0xF0000000U) macro
81192 … (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_RDH_SHIFT)) & SEMC_NORCR2_RDH_MASK)
DMIMXRT1176_cm4.h82091 #define SEMC_NORCR2_RDH_MASK (0xF0000000U) macro
82094 … (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_RDH_SHIFT)) & SEMC_NORCR2_RDH_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1187/
DMIMXRT1187_cm33.h75016 #define SEMC_NORCR2_RDH_MASK (0xF0000000U) macro
75019 … (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_RDH_SHIFT)) & SEMC_NORCR2_RDH_MASK)
DMIMXRT1187_cm7.h72990 #define SEMC_NORCR2_RDH_MASK (0xF0000000U) macro
72993 … (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_RDH_SHIFT)) & SEMC_NORCR2_RDH_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1189/
DMIMXRT1189_cm33.h78864 #define SEMC_NORCR2_RDH_MASK (0xF0000000U) macro
78867 … (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_RDH_SHIFT)) & SEMC_NORCR2_RDH_MASK)
DMIMXRT1189_cm7.h76819 #define SEMC_NORCR2_RDH_MASK (0xF0000000U) macro
76822 … (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_RDH_SHIFT)) & SEMC_NORCR2_RDH_MASK)