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Searched refs:SEMC_MCR_SWRST_MASK (Results 1 – 25 of 26) sorted by relevance

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/hal_nxp-latest/mcux/mcux-sdk/drivers/semc/
Dfsl_semc.c355 base->MCR = SEMC_MCR_SWRST_MASK; in SEMC_Init()
356 while ((base->MCR & (uint32_t)SEMC_MCR_SWRST_MASK) != 0x00U) in SEMC_Init()
403 base->MCR |= SEMC_MCR_MDIS_MASK | SEMC_MCR_SWRST_MASK; in SEMC_Deinit()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1024/
DMIMXRT1024.h33278 #define SEMC_MCR_SWRST_MASK (0x1U) macro
33284 … (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_SWRST_SHIFT)) & SEMC_MCR_SWRST_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1021/
DMIMXRT1021.h33299 #define SEMC_MCR_SWRST_MASK (0x1U) macro
33305 … (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_SWRST_SHIFT)) & SEMC_MCR_SWRST_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1051/
DMIMXRT1051.h34862 #define SEMC_MCR_SWRST_MASK (0x1U) macro
34865 … (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_SWRST_SHIFT)) & SEMC_MCR_SWRST_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1041/
DMIMXRT1041.h36079 #define SEMC_MCR_SWRST_MASK (0x1U) macro
36085 … (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_SWRST_SHIFT)) & SEMC_MCR_SWRST_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1052/
DMIMXRT1052.h39128 #define SEMC_MCR_SWRST_MASK (0x1U) macro
39131 … (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_SWRST_SHIFT)) & SEMC_MCR_SWRST_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1042/
DMIMXRT1042.h39489 #define SEMC_MCR_SWRST_MASK (0x1U) macro
39495 … (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_SWRST_SHIFT)) & SEMC_MCR_SWRST_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1061/
DMIMXRT1061.h36963 #define SEMC_MCR_SWRST_MASK (0x1U) macro
36969 … (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_SWRST_SHIFT)) & SEMC_MCR_SWRST_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1064/
DMIMXRT1064.h41164 #define SEMC_MCR_SWRST_MASK (0x1U) macro
41170 … (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_SWRST_SHIFT)) & SEMC_MCR_SWRST_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1062/
DMIMXRT1062.h41157 #define SEMC_MCR_SWRST_MASK (0x1U) macro
41163 … (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_SWRST_SHIFT)) & SEMC_MCR_SWRST_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1175/
DMIMXRT1175_cm4.h65017 #define SEMC_MCR_SWRST_MASK (0x1U) macro
65023 … (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_SWRST_SHIFT)) & SEMC_MCR_SWRST_MASK)
DMIMXRT1175_cm7.h64115 #define SEMC_MCR_SWRST_MASK (0x1U) macro
64121 … (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_SWRST_SHIFT)) & SEMC_MCR_SWRST_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1165/
DMIMXRT1165_cm7.h63613 #define SEMC_MCR_SWRST_MASK (0x1U) macro
63619 … (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_SWRST_SHIFT)) & SEMC_MCR_SWRST_MASK)
DMIMXRT1165_cm4.h64515 #define SEMC_MCR_SWRST_MASK (0x1U) macro
64521 … (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_SWRST_SHIFT)) & SEMC_MCR_SWRST_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1171/
DMIMXRT1171.h64115 #define SEMC_MCR_SWRST_MASK (0x1U) macro
64121 … (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_SWRST_SHIFT)) & SEMC_MCR_SWRST_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1166/
DMIMXRT1166_cm4.h69978 #define SEMC_MCR_SWRST_MASK (0x1U) macro
69984 … (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_SWRST_SHIFT)) & SEMC_MCR_SWRST_MASK)
DMIMXRT1166_cm7.h69076 #define SEMC_MCR_SWRST_MASK (0x1U) macro
69082 … (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_SWRST_SHIFT)) & SEMC_MCR_SWRST_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1173/
DMIMXRT1173_cm4.h70477 #define SEMC_MCR_SWRST_MASK (0x1U) macro
70483 … (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_SWRST_SHIFT)) & SEMC_MCR_SWRST_MASK)
DMIMXRT1173_cm7.h69575 #define SEMC_MCR_SWRST_MASK (0x1U) macro
69581 … (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_SWRST_SHIFT)) & SEMC_MCR_SWRST_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1172/
DMIMXRT1172.h69578 #define SEMC_MCR_SWRST_MASK (0x1U) macro
69584 … (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_SWRST_SHIFT)) & SEMC_MCR_SWRST_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1176/
DMIMXRT1176_cm7.h80245 #define SEMC_MCR_SWRST_MASK (0x1U) macro
80251 … (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_SWRST_SHIFT)) & SEMC_MCR_SWRST_MASK)
DMIMXRT1176_cm4.h81147 #define SEMC_MCR_SWRST_MASK (0x1U) macro
81153 … (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_SWRST_SHIFT)) & SEMC_MCR_SWRST_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1187/
DMIMXRT1187_cm33.h74007 #define SEMC_MCR_SWRST_MASK (0x1U) macro
74013 … (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_SWRST_SHIFT)) & SEMC_MCR_SWRST_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1189/
DMIMXRT1189_cm33.h77855 #define SEMC_MCR_SWRST_MASK (0x1U) macro
77861 … (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_SWRST_SHIFT)) & SEMC_MCR_SWRST_MASK)
DMIMXRT1189_cm7.h75810 #define SEMC_MCR_SWRST_MASK (0x1U) macro
75816 … (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_SWRST_SHIFT)) & SEMC_MCR_SWRST_MASK)

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