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Searched refs:SEMC_IPCR2_BM3_MASK (Results 1 – 25 of 26) sorted by relevance

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/hal_nxp-latest/mcux/mcux-sdk/drivers/semc/
Dfsl_semc.c247 base->IPCR2 |= SEMC_IPCR2_BM3_MASK; in SEMC_ConfigureIPCommand()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1021/
DMIMXRT1021.h34356 #define SEMC_IPCR2_BM3_MASK (0x8U) macro
34362 … (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR2_BM3_SHIFT)) & SEMC_IPCR2_BM3_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1024/
DMIMXRT1024.h34335 #define SEMC_IPCR2_BM3_MASK (0x8U) macro
34341 … (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR2_BM3_SHIFT)) & SEMC_IPCR2_BM3_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1041/
DMIMXRT1041.h37319 #define SEMC_IPCR2_BM3_MASK (0x8U) macro
37325 … (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR2_BM3_SHIFT)) & SEMC_IPCR2_BM3_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1051/
DMIMXRT1051.h35904 #define SEMC_IPCR2_BM3_MASK (0x8U) macro
35910 … (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR2_BM3_SHIFT)) & SEMC_IPCR2_BM3_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1042/
DMIMXRT1042.h40729 #define SEMC_IPCR2_BM3_MASK (0x8U) macro
40735 … (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR2_BM3_SHIFT)) & SEMC_IPCR2_BM3_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1052/
DMIMXRT1052.h40170 #define SEMC_IPCR2_BM3_MASK (0x8U) macro
40176 … (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR2_BM3_SHIFT)) & SEMC_IPCR2_BM3_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1061/
DMIMXRT1061.h38203 #define SEMC_IPCR2_BM3_MASK (0x8U) macro
38209 … (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR2_BM3_SHIFT)) & SEMC_IPCR2_BM3_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1062/
DMIMXRT1062.h42397 #define SEMC_IPCR2_BM3_MASK (0x8U) macro
42403 … (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR2_BM3_SHIFT)) & SEMC_IPCR2_BM3_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1064/
DMIMXRT1064.h42404 #define SEMC_IPCR2_BM3_MASK (0x8U) macro
42410 … (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR2_BM3_SHIFT)) & SEMC_IPCR2_BM3_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1165/
DMIMXRT1165_cm4.h65815 #define SEMC_IPCR2_BM3_MASK (0x8U) macro
65821 … (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR2_BM3_SHIFT)) & SEMC_IPCR2_BM3_MASK)
DMIMXRT1165_cm7.h64913 #define SEMC_IPCR2_BM3_MASK (0x8U) macro
64919 … (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR2_BM3_SHIFT)) & SEMC_IPCR2_BM3_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1171/
DMIMXRT1171.h65415 #define SEMC_IPCR2_BM3_MASK (0x8U) macro
65421 … (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR2_BM3_SHIFT)) & SEMC_IPCR2_BM3_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1175/
DMIMXRT1175_cm4.h66317 #define SEMC_IPCR2_BM3_MASK (0x8U) macro
66323 … (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR2_BM3_SHIFT)) & SEMC_IPCR2_BM3_MASK)
DMIMXRT1175_cm7.h65415 #define SEMC_IPCR2_BM3_MASK (0x8U) macro
65421 … (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR2_BM3_SHIFT)) & SEMC_IPCR2_BM3_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1173/
DMIMXRT1173_cm7.h70875 #define SEMC_IPCR2_BM3_MASK (0x8U) macro
70881 … (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR2_BM3_SHIFT)) & SEMC_IPCR2_BM3_MASK)
DMIMXRT1173_cm4.h71777 #define SEMC_IPCR2_BM3_MASK (0x8U) macro
71783 … (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR2_BM3_SHIFT)) & SEMC_IPCR2_BM3_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1166/
DMIMXRT1166_cm7.h70376 #define SEMC_IPCR2_BM3_MASK (0x8U) macro
70382 … (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR2_BM3_SHIFT)) & SEMC_IPCR2_BM3_MASK)
DMIMXRT1166_cm4.h71278 #define SEMC_IPCR2_BM3_MASK (0x8U) macro
71284 … (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR2_BM3_SHIFT)) & SEMC_IPCR2_BM3_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1172/
DMIMXRT1172.h70878 #define SEMC_IPCR2_BM3_MASK (0x8U) macro
70884 … (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR2_BM3_SHIFT)) & SEMC_IPCR2_BM3_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1176/
DMIMXRT1176_cm7.h81545 #define SEMC_IPCR2_BM3_MASK (0x8U) macro
81551 … (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR2_BM3_SHIFT)) & SEMC_IPCR2_BM3_MASK)
DMIMXRT1176_cm4.h82447 #define SEMC_IPCR2_BM3_MASK (0x8U) macro
82453 … (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR2_BM3_SHIFT)) & SEMC_IPCR2_BM3_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1187/
DMIMXRT1187_cm33.h75372 #define SEMC_IPCR2_BM3_MASK (0x8U) macro
75378 … (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR2_BM3_SHIFT)) & SEMC_IPCR2_BM3_MASK)
DMIMXRT1187_cm7.h73346 #define SEMC_IPCR2_BM3_MASK (0x8U) macro
73352 … (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR2_BM3_SHIFT)) & SEMC_IPCR2_BM3_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1189/
DMIMXRT1189_cm7.h77175 #define SEMC_IPCR2_BM3_MASK (0x8U) macro
77181 … (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR2_BM3_SHIFT)) & SEMC_IPCR2_BM3_MASK)

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