| /hal_nxp-latest/mcux/mcux-sdk/drivers/semc/ |
| D | fsl_semc.c | 513 base->SDRAMCR3 = SEMC_SDRAMCR3_REBL((uint32_t)config->refreshBurstLen - 1UL) | in SEMC_ConfigureSDRAM()
549 base->SDRAMCR3 |= SEMC_SDRAMCR3_REN_MASK; in SEMC_ConfigureSDRAM()
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| /hal_nxp-latest/mcux/mcux-sdk/boards/evkmimxrt1170/ |
| D | evkmimxrt1170_connect_cm4_cm4side_sdram.jlinkscript | 312 MEM_WriteU32(0x400d404C, 0x21210408); // SDRAMCR3
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| /hal_nxp-latest/mcux/mcux-sdk/boards/evkbmimxrt1170/ |
| D | evkbmimxrt1170_connect_cm4_cm4side_sdram.jlinkscript | 312 MEM_WriteU32(0x400d404C, 0x21210408); // SDRAMCR3
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1021/ |
| D | MIMXRT1021.h | 33245 __IO uint32_t SDRAMCR3; /**< SDRAM Control Register 3, offset: 0x4C */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1024/ |
| D | MIMXRT1024.h | 33224 __IO uint32_t SDRAMCR3; /**< SDRAM Control Register 3, offset: 0x4C */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1041/ |
| D | MIMXRT1041.h | 36025 __IO uint32_t SDRAMCR3; /**< SDRAM Control Register 3, offset: 0x4C */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1051/ |
| D | MIMXRT1051.h | 34808 __IO uint32_t SDRAMCR3; /**< SDRAM control register 3, offset: 0x4C */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1042/ |
| D | MIMXRT1042.h | 39435 __IO uint32_t SDRAMCR3; /**< SDRAM Control Register 3, offset: 0x4C */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1052/ |
| D | MIMXRT1052.h | 39074 __IO uint32_t SDRAMCR3; /**< SDRAM control register 3, offset: 0x4C */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1061/ |
| D | MIMXRT1061.h | 36909 __IO uint32_t SDRAMCR3; /**< SDRAM Control Register 3, offset: 0x4C */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1062/ |
| D | MIMXRT1062.h | 41103 __IO uint32_t SDRAMCR3; /**< SDRAM Control Register 3, offset: 0x4C */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1064/ |
| D | MIMXRT1064.h | 41110 __IO uint32_t SDRAMCR3; /**< SDRAM Control Register 3, offset: 0x4C */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1165/ |
| D | MIMXRT1165_cm4.h | 64451 __IO uint32_t SDRAMCR3; /**< SDRAM Control Register 3, offset: 0x4C */ member
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| D | MIMXRT1165_cm7.h | 63549 __IO uint32_t SDRAMCR3; /**< SDRAM Control Register 3, offset: 0x4C */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1171/ |
| D | MIMXRT1171.h | 64051 __IO uint32_t SDRAMCR3; /**< SDRAM Control Register 3, offset: 0x4C */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1175/ |
| D | MIMXRT1175_cm4.h | 64953 __IO uint32_t SDRAMCR3; /**< SDRAM Control Register 3, offset: 0x4C */ member
|
| D | MIMXRT1175_cm7.h | 64051 __IO uint32_t SDRAMCR3; /**< SDRAM Control Register 3, offset: 0x4C */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1173/ |
| D | MIMXRT1173_cm7.h | 69511 __IO uint32_t SDRAMCR3; /**< SDRAM Control Register 3, offset: 0x4C */ member
|
| D | MIMXRT1173_cm4.h | 70413 __IO uint32_t SDRAMCR3; /**< SDRAM Control Register 3, offset: 0x4C */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1166/ |
| D | MIMXRT1166_cm7.h | 69012 __IO uint32_t SDRAMCR3; /**< SDRAM Control Register 3, offset: 0x4C */ member
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| D | MIMXRT1166_cm4.h | 69914 __IO uint32_t SDRAMCR3; /**< SDRAM Control Register 3, offset: 0x4C */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1172/ |
| D | MIMXRT1172.h | 69514 __IO uint32_t SDRAMCR3; /**< SDRAM Control Register 3, offset: 0x4C */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1176/ |
| D | MIMXRT1176_cm7.h | 80181 __IO uint32_t SDRAMCR3; /**< SDRAM Control Register 3, offset: 0x4C */ member
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| D | MIMXRT1176_cm4.h | 81083 __IO uint32_t SDRAMCR3; /**< SDRAM Control Register 3, offset: 0x4C */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1187/ |
| D | MIMXRT1187_cm33.h | 73939 __IO uint32_t SDRAMCR3; /**< SDRAM Control Register 3, offset: 0x4C */ member
|
